diff options
-rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index 2a139ef5ae30..2e9e61c1a50d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | |||
@@ -158,18 +158,6 @@ static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) | |||
158 | napi_disable(&tqp_vector->napi); | 158 | napi_disable(&tqp_vector->napi); |
159 | } | 159 | } |
160 | 160 | ||
161 | static void hns3_set_vector_coalesc_gl(struct hns3_enet_tqp_vector *tqp_vector, | ||
162 | u32 gl_value) | ||
163 | { | ||
164 | /* this defines the configuration for GL (Interrupt Gap Limiter) | ||
165 | * GL defines inter interrupt gap. | ||
166 | * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing | ||
167 | */ | ||
168 | writel(gl_value, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); | ||
169 | writel(gl_value, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); | ||
170 | writel(gl_value, tqp_vector->mask_addr + HNS3_VECTOR_GL2_OFFSET); | ||
171 | } | ||
172 | |||
173 | void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, | 161 | void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, |
174 | u32 rl_value) | 162 | u32 rl_value) |
175 | { | 163 | { |