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-rw-r--r--drivers/clk/meson/Kconfig12
-rw-r--r--drivers/clk/meson/Makefile1
-rw-r--r--drivers/clk/meson/clk-regmap.h9
-rw-r--r--drivers/clk/meson/g12a.c2399
-rw-r--r--drivers/clk/meson/g12a.h175
5 files changed, 2594 insertions, 2 deletions
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index f2e757aea4f1..4f61dd71f26d 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -88,3 +88,15 @@ config COMMON_CLK_AXG_AUDIO
88 help 88 help
89 Support for the audio clock controller on AmLogic A113D devices, 89 Support for the audio clock controller on AmLogic A113D devices,
90 aka axg, Say Y if you want audio subsystem to work. 90 aka axg, Say Y if you want audio subsystem to work.
91
92config COMMON_CLK_G12A
93 bool
94 depends on ARCH_MESON
95 select COMMON_CLK_MESON_INPUT
96 select COMMON_CLK_MESON_REGMAP
97 select COMMON_CLK_MESON_MPLL
98 select COMMON_CLK_MESON_PLL
99 select MFD_SYSCON
100 help
101 Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
102 devices, aka g12a. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index e339d8f58488..c3dd3901afe3 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
15obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o 15obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
16obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o 16obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
17obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 17obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
18obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
18obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 19obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index b7a085bbf072..1dd0abe3ba91 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk)
111extern const struct clk_ops clk_regmap_mux_ops; 111extern const struct clk_ops clk_regmap_mux_ops;
112extern const struct clk_ops clk_regmap_mux_ro_ops; 112extern const struct clk_ops clk_regmap_mux_ro_ops;
113 113
114#define MESON_GATE(_name, _reg, _bit) \ 114#define __MESON_GATE(_name, _reg, _bit, _ops) \
115struct clk_regmap _name = { \ 115struct clk_regmap _name = { \
116 .data = &(struct clk_regmap_gate_data){ \ 116 .data = &(struct clk_regmap_gate_data){ \
117 .offset = (_reg), \ 117 .offset = (_reg), \
@@ -119,11 +119,16 @@ struct clk_regmap _name = { \
119 }, \ 119 }, \
120 .hw.init = &(struct clk_init_data) { \ 120 .hw.init = &(struct clk_init_data) { \
121 .name = #_name, \ 121 .name = #_name, \
122 .ops = &clk_regmap_gate_ops, \ 122 .ops = _ops, \
123 .parent_names = (const char *[]){ "clk81" }, \ 123 .parent_names = (const char *[]){ "clk81" }, \
124 .num_parents = 1, \ 124 .num_parents = 1, \
125 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ 125 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
126 }, \ 126 }, \
127} 127}
128 128
129#define MESON_GATE(_name, _reg, _bit) \
130 __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops)
131
132#define MESON_GATE_RO(_name, _reg, _bit) \
133 __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops)
129#endif /* __CLK_REGMAP_H */ 134#endif /* __CLK_REGMAP_H */
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000000000000..4d9ec6026ef6
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,2399 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-G12A Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/init.h>
15#include <linux/of_device.h>
16#include <linux/mfd/syscon.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19
20#include "clk-input.h"
21#include "clk-mpll.h"
22#include "clk-pll.h"
23#include "clk-regmap.h"
24#include "vid-pll-div.h"
25#include "g12a.h"
26
27#define IN_PREFIX "ee-in-"
28
29static DEFINE_SPINLOCK(meson_clk_lock);
30
31static struct clk_regmap g12a_fixed_pll_dco = {
32 .data = &(struct meson_clk_pll_data){
33 .en = {
34 .reg_off = HHI_FIX_PLL_CNTL0,
35 .shift = 28,
36 .width = 1,
37 },
38 .m = {
39 .reg_off = HHI_FIX_PLL_CNTL0,
40 .shift = 0,
41 .width = 8,
42 },
43 .n = {
44 .reg_off = HHI_FIX_PLL_CNTL0,
45 .shift = 10,
46 .width = 5,
47 },
48 .frac = {
49 .reg_off = HHI_FIX_PLL_CNTL1,
50 .shift = 0,
51 .width = 17,
52 },
53 .l = {
54 .reg_off = HHI_FIX_PLL_CNTL0,
55 .shift = 31,
56 .width = 1,
57 },
58 .rst = {
59 .reg_off = HHI_FIX_PLL_CNTL0,
60 .shift = 29,
61 .width = 1,
62 },
63 },
64 .hw.init = &(struct clk_init_data){
65 .name = "fixed_pll_dco",
66 .ops = &meson_clk_pll_ro_ops,
67 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
68 .num_parents = 1,
69 },
70};
71
72static struct clk_regmap g12a_fixed_pll = {
73 .data = &(struct clk_regmap_div_data){
74 .offset = HHI_FIX_PLL_CNTL0,
75 .shift = 16,
76 .width = 2,
77 .flags = CLK_DIVIDER_POWER_OF_TWO,
78 },
79 .hw.init = &(struct clk_init_data){
80 .name = "fixed_pll",
81 .ops = &clk_regmap_divider_ro_ops,
82 .parent_names = (const char *[]){ "fixed_pll_dco" },
83 .num_parents = 1,
84 /*
85 * This clock won't ever change at runtime so
86 * CLK_SET_RATE_PARENT is not required
87 */
88 },
89};
90
91/*
92 * Internal sys pll emulation configuration parameters
93 */
94static const struct reg_sequence g12a_sys_init_regs[] = {
95 { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
96 { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
97 { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
98 { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
99 { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
100 { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
101};
102
103static struct clk_regmap g12a_sys_pll_dco = {
104 .data = &(struct meson_clk_pll_data){
105 .en = {
106 .reg_off = HHI_SYS_PLL_CNTL0,
107 .shift = 28,
108 .width = 1,
109 },
110 .m = {
111 .reg_off = HHI_SYS_PLL_CNTL0,
112 .shift = 0,
113 .width = 8,
114 },
115 .n = {
116 .reg_off = HHI_SYS_PLL_CNTL0,
117 .shift = 10,
118 .width = 5,
119 },
120 .l = {
121 .reg_off = HHI_SYS_PLL_CNTL0,
122 .shift = 31,
123 .width = 1,
124 },
125 .rst = {
126 .reg_off = HHI_SYS_PLL_CNTL0,
127 .shift = 29,
128 .width = 1,
129 },
130 .init_regs = g12a_sys_init_regs,
131 .init_count = ARRAY_SIZE(g12a_sys_init_regs),
132 },
133 .hw.init = &(struct clk_init_data){
134 .name = "sys_pll_dco",
135 .ops = &meson_clk_pll_ro_ops,
136 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
137 .num_parents = 1,
138 },
139};
140
141static struct clk_regmap g12a_sys_pll = {
142 .data = &(struct clk_regmap_div_data){
143 .offset = HHI_SYS_PLL_CNTL0,
144 .shift = 16,
145 .width = 3,
146 .flags = CLK_DIVIDER_POWER_OF_TWO,
147 },
148 .hw.init = &(struct clk_init_data){
149 .name = "sys_pll",
150 .ops = &clk_regmap_divider_ro_ops,
151 .parent_names = (const char *[]){ "sys_pll_dco" },
152 .num_parents = 1,
153 },
154};
155
156static const struct pll_mult_range g12a_gp0_pll_mult_range = {
157 .min = 55,
158 .max = 255,
159};
160
161/*
162 * Internal gp0 pll emulation configuration parameters
163 */
164static const struct reg_sequence g12a_gp0_init_regs[] = {
165 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
166 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
167 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
168 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
169 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
170 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
171};
172
173static struct clk_regmap g12a_gp0_pll_dco = {
174 .data = &(struct meson_clk_pll_data){
175 .en = {
176 .reg_off = HHI_GP0_PLL_CNTL0,
177 .shift = 28,
178 .width = 1,
179 },
180 .m = {
181 .reg_off = HHI_GP0_PLL_CNTL0,
182 .shift = 0,
183 .width = 8,
184 },
185 .n = {
186 .reg_off = HHI_GP0_PLL_CNTL0,
187 .shift = 10,
188 .width = 5,
189 },
190 .frac = {
191 .reg_off = HHI_GP0_PLL_CNTL1,
192 .shift = 0,
193 .width = 17,
194 },
195 .l = {
196 .reg_off = HHI_GP0_PLL_CNTL0,
197 .shift = 31,
198 .width = 1,
199 },
200 .rst = {
201 .reg_off = HHI_GP0_PLL_CNTL0,
202 .shift = 29,
203 .width = 1,
204 },
205 .range = &g12a_gp0_pll_mult_range,
206 .init_regs = g12a_gp0_init_regs,
207 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
208 },
209 .hw.init = &(struct clk_init_data){
210 .name = "gp0_pll_dco",
211 .ops = &meson_clk_pll_ops,
212 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
213 .num_parents = 1,
214 },
215};
216
217static struct clk_regmap g12a_gp0_pll = {
218 .data = &(struct clk_regmap_div_data){
219 .offset = HHI_GP0_PLL_CNTL0,
220 .shift = 16,
221 .width = 3,
222 .flags = (CLK_DIVIDER_POWER_OF_TWO |
223 CLK_DIVIDER_ROUND_CLOSEST),
224 },
225 .hw.init = &(struct clk_init_data){
226 .name = "gp0_pll",
227 .ops = &clk_regmap_divider_ops,
228 .parent_names = (const char *[]){ "gp0_pll_dco" },
229 .num_parents = 1,
230 .flags = CLK_SET_RATE_PARENT,
231 },
232};
233
234/*
235 * Internal hifi pll emulation configuration parameters
236 */
237static const struct reg_sequence g12a_hifi_init_regs[] = {
238 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
239 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
240 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
241 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
242 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
243 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
244};
245
246static struct clk_regmap g12a_hifi_pll_dco = {
247 .data = &(struct meson_clk_pll_data){
248 .en = {
249 .reg_off = HHI_HIFI_PLL_CNTL0,
250 .shift = 28,
251 .width = 1,
252 },
253 .m = {
254 .reg_off = HHI_HIFI_PLL_CNTL0,
255 .shift = 0,
256 .width = 8,
257 },
258 .n = {
259 .reg_off = HHI_HIFI_PLL_CNTL0,
260 .shift = 10,
261 .width = 5,
262 },
263 .frac = {
264 .reg_off = HHI_HIFI_PLL_CNTL1,
265 .shift = 0,
266 .width = 17,
267 },
268 .l = {
269 .reg_off = HHI_HIFI_PLL_CNTL0,
270 .shift = 31,
271 .width = 1,
272 },
273 .rst = {
274 .reg_off = HHI_HIFI_PLL_CNTL0,
275 .shift = 29,
276 .width = 1,
277 },
278 .range = &g12a_gp0_pll_mult_range,
279 .init_regs = g12a_hifi_init_regs,
280 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
281 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
282 },
283 .hw.init = &(struct clk_init_data){
284 .name = "hifi_pll_dco",
285 .ops = &meson_clk_pll_ops,
286 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
287 .num_parents = 1,
288 },
289};
290
291static struct clk_regmap g12a_hifi_pll = {
292 .data = &(struct clk_regmap_div_data){
293 .offset = HHI_HIFI_PLL_CNTL0,
294 .shift = 16,
295 .width = 2,
296 .flags = (CLK_DIVIDER_POWER_OF_TWO |
297 CLK_DIVIDER_ROUND_CLOSEST),
298 },
299 .hw.init = &(struct clk_init_data){
300 .name = "hifi_pll",
301 .ops = &clk_regmap_divider_ops,
302 .parent_names = (const char *[]){ "hifi_pll_dco" },
303 .num_parents = 1,
304 .flags = CLK_SET_RATE_PARENT,
305 },
306};
307
308static struct clk_regmap g12a_hdmi_pll_dco = {
309 .data = &(struct meson_clk_pll_data){
310 .en = {
311 .reg_off = HHI_HDMI_PLL_CNTL0,
312 .shift = 28,
313 .width = 1,
314 },
315 .m = {
316 .reg_off = HHI_HDMI_PLL_CNTL0,
317 .shift = 0,
318 .width = 8,
319 },
320 .n = {
321 .reg_off = HHI_HDMI_PLL_CNTL0,
322 .shift = 10,
323 .width = 5,
324 },
325 .frac = {
326 .reg_off = HHI_HDMI_PLL_CNTL1,
327 .shift = 0,
328 .width = 16,
329 },
330 .l = {
331 .reg_off = HHI_HDMI_PLL_CNTL0,
332 .shift = 30,
333 .width = 1,
334 },
335 .rst = {
336 .reg_off = HHI_HDMI_PLL_CNTL0,
337 .shift = 29,
338 .width = 1,
339 },
340 },
341 .hw.init = &(struct clk_init_data){
342 .name = "hdmi_pll_dco",
343 .ops = &meson_clk_pll_ro_ops,
344 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
345 .num_parents = 1,
346 /*
347 * Display directly handle hdmi pll registers ATM, we need
348 * NOCACHE to keep our view of the clock as accurate as possible
349 */
350 .flags = CLK_GET_RATE_NOCACHE,
351 },
352};
353
354static struct clk_regmap g12a_hdmi_pll_od = {
355 .data = &(struct clk_regmap_div_data){
356 .offset = HHI_HDMI_PLL_CNTL0,
357 .shift = 16,
358 .width = 2,
359 .flags = CLK_DIVIDER_POWER_OF_TWO,
360 },
361 .hw.init = &(struct clk_init_data){
362 .name = "hdmi_pll_od",
363 .ops = &clk_regmap_divider_ro_ops,
364 .parent_names = (const char *[]){ "hdmi_pll_dco" },
365 .num_parents = 1,
366 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
367 },
368};
369
370static struct clk_regmap g12a_hdmi_pll_od2 = {
371 .data = &(struct clk_regmap_div_data){
372 .offset = HHI_HDMI_PLL_CNTL0,
373 .shift = 18,
374 .width = 2,
375 .flags = CLK_DIVIDER_POWER_OF_TWO,
376 },
377 .hw.init = &(struct clk_init_data){
378 .name = "hdmi_pll_od2",
379 .ops = &clk_regmap_divider_ro_ops,
380 .parent_names = (const char *[]){ "hdmi_pll_od" },
381 .num_parents = 1,
382 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
383 },
384};
385
386static struct clk_regmap g12a_hdmi_pll = {
387 .data = &(struct clk_regmap_div_data){
388 .offset = HHI_HDMI_PLL_CNTL0,
389 .shift = 20,
390 .width = 2,
391 .flags = CLK_DIVIDER_POWER_OF_TWO,
392 },
393 .hw.init = &(struct clk_init_data){
394 .name = "hdmi_pll",
395 .ops = &clk_regmap_divider_ro_ops,
396 .parent_names = (const char *[]){ "hdmi_pll_od2" },
397 .num_parents = 1,
398 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
399 },
400};
401
402static struct clk_fixed_factor g12a_fclk_div2_div = {
403 .mult = 1,
404 .div = 2,
405 .hw.init = &(struct clk_init_data){
406 .name = "fclk_div2_div",
407 .ops = &clk_fixed_factor_ops,
408 .parent_names = (const char *[]){ "fixed_pll" },
409 .num_parents = 1,
410 },
411};
412
413static struct clk_regmap g12a_fclk_div2 = {
414 .data = &(struct clk_regmap_gate_data){
415 .offset = HHI_FIX_PLL_CNTL1,
416 .bit_idx = 24,
417 },
418 .hw.init = &(struct clk_init_data){
419 .name = "fclk_div2",
420 .ops = &clk_regmap_gate_ops,
421 .parent_names = (const char *[]){ "fclk_div2_div" },
422 .num_parents = 1,
423 },
424};
425
426static struct clk_fixed_factor g12a_fclk_div3_div = {
427 .mult = 1,
428 .div = 3,
429 .hw.init = &(struct clk_init_data){
430 .name = "fclk_div3_div",
431 .ops = &clk_fixed_factor_ops,
432 .parent_names = (const char *[]){ "fixed_pll" },
433 .num_parents = 1,
434 },
435};
436
437static struct clk_regmap g12a_fclk_div3 = {
438 .data = &(struct clk_regmap_gate_data){
439 .offset = HHI_FIX_PLL_CNTL1,
440 .bit_idx = 20,
441 },
442 .hw.init = &(struct clk_init_data){
443 .name = "fclk_div3",
444 .ops = &clk_regmap_gate_ops,
445 .parent_names = (const char *[]){ "fclk_div3_div" },
446 .num_parents = 1,
447 },
448};
449
450static struct clk_fixed_factor g12a_fclk_div4_div = {
451 .mult = 1,
452 .div = 4,
453 .hw.init = &(struct clk_init_data){
454 .name = "fclk_div4_div",
455 .ops = &clk_fixed_factor_ops,
456 .parent_names = (const char *[]){ "fixed_pll" },
457 .num_parents = 1,
458 },
459};
460
461static struct clk_regmap g12a_fclk_div4 = {
462 .data = &(struct clk_regmap_gate_data){
463 .offset = HHI_FIX_PLL_CNTL1,
464 .bit_idx = 21,
465 },
466 .hw.init = &(struct clk_init_data){
467 .name = "fclk_div4",
468 .ops = &clk_regmap_gate_ops,
469 .parent_names = (const char *[]){ "fclk_div4_div" },
470 .num_parents = 1,
471 },
472};
473
474static struct clk_fixed_factor g12a_fclk_div5_div = {
475 .mult = 1,
476 .div = 5,
477 .hw.init = &(struct clk_init_data){
478 .name = "fclk_div5_div",
479 .ops = &clk_fixed_factor_ops,
480 .parent_names = (const char *[]){ "fixed_pll" },
481 .num_parents = 1,
482 },
483};
484
485static struct clk_regmap g12a_fclk_div5 = {
486 .data = &(struct clk_regmap_gate_data){
487 .offset = HHI_FIX_PLL_CNTL1,
488 .bit_idx = 22,
489 },
490 .hw.init = &(struct clk_init_data){
491 .name = "fclk_div5",
492 .ops = &clk_regmap_gate_ops,
493 .parent_names = (const char *[]){ "fclk_div5_div" },
494 .num_parents = 1,
495 },
496};
497
498static struct clk_fixed_factor g12a_fclk_div7_div = {
499 .mult = 1,
500 .div = 7,
501 .hw.init = &(struct clk_init_data){
502 .name = "fclk_div7_div",
503 .ops = &clk_fixed_factor_ops,
504 .parent_names = (const char *[]){ "fixed_pll" },
505 .num_parents = 1,
506 },
507};
508
509static struct clk_regmap g12a_fclk_div7 = {
510 .data = &(struct clk_regmap_gate_data){
511 .offset = HHI_FIX_PLL_CNTL1,
512 .bit_idx = 23,
513 },
514 .hw.init = &(struct clk_init_data){
515 .name = "fclk_div7",
516 .ops = &clk_regmap_gate_ops,
517 .parent_names = (const char *[]){ "fclk_div7_div" },
518 .num_parents = 1,
519 },
520};
521
522static struct clk_fixed_factor g12a_fclk_div2p5_div = {
523 .mult = 1,
524 .div = 5,
525 .hw.init = &(struct clk_init_data){
526 .name = "fclk_div2p5_div",
527 .ops = &clk_fixed_factor_ops,
528 .parent_names = (const char *[]){ "fixed_pll_dco" },
529 .num_parents = 1,
530 },
531};
532
533static struct clk_regmap g12a_fclk_div2p5 = {
534 .data = &(struct clk_regmap_gate_data){
535 .offset = HHI_FIX_PLL_CNTL1,
536 .bit_idx = 25,
537 },
538 .hw.init = &(struct clk_init_data){
539 .name = "fclk_div2p5",
540 .ops = &clk_regmap_gate_ops,
541 .parent_names = (const char *[]){ "fclk_div2p5_div" },
542 .num_parents = 1,
543 },
544};
545
546static struct clk_fixed_factor g12a_mpll_50m_div = {
547 .mult = 1,
548 .div = 80,
549 .hw.init = &(struct clk_init_data){
550 .name = "mpll_50m_div",
551 .ops = &clk_fixed_factor_ops,
552 .parent_names = (const char *[]){ "fixed_pll_dco" },
553 .num_parents = 1,
554 },
555};
556
557static struct clk_regmap g12a_mpll_50m = {
558 .data = &(struct clk_regmap_mux_data){
559 .offset = HHI_FIX_PLL_CNTL3,
560 .mask = 0x1,
561 .shift = 5,
562 },
563 .hw.init = &(struct clk_init_data){
564 .name = "mpll_50m",
565 .ops = &clk_regmap_mux_ro_ops,
566 .parent_names = (const char *[]){ IN_PREFIX "xtal",
567 "mpll_50m_div" },
568 .num_parents = 2,
569 },
570};
571
572static struct clk_fixed_factor g12a_mpll_prediv = {
573 .mult = 1,
574 .div = 2,
575 .hw.init = &(struct clk_init_data){
576 .name = "mpll_prediv",
577 .ops = &clk_fixed_factor_ops,
578 .parent_names = (const char *[]){ "fixed_pll_dco" },
579 .num_parents = 1,
580 },
581};
582
583static struct clk_regmap g12a_mpll0_div = {
584 .data = &(struct meson_clk_mpll_data){
585 .sdm = {
586 .reg_off = HHI_MPLL_CNTL1,
587 .shift = 0,
588 .width = 14,
589 },
590 .sdm_en = {
591 .reg_off = HHI_MPLL_CNTL1,
592 .shift = 30,
593 .width = 1,
594 },
595 .n2 = {
596 .reg_off = HHI_MPLL_CNTL1,
597 .shift = 20,
598 .width = 9,
599 },
600 .ssen = {
601 .reg_off = HHI_MPLL_CNTL1,
602 .shift = 29,
603 .width = 1,
604 },
605 .lock = &meson_clk_lock,
606 },
607 .hw.init = &(struct clk_init_data){
608 .name = "mpll0_div",
609 .ops = &meson_clk_mpll_ops,
610 .parent_names = (const char *[]){ "mpll_prediv" },
611 .num_parents = 1,
612 },
613};
614
615static struct clk_regmap g12a_mpll0 = {
616 .data = &(struct clk_regmap_gate_data){
617 .offset = HHI_MPLL_CNTL1,
618 .bit_idx = 31,
619 },
620 .hw.init = &(struct clk_init_data){
621 .name = "mpll0",
622 .ops = &clk_regmap_gate_ops,
623 .parent_names = (const char *[]){ "mpll0_div" },
624 .num_parents = 1,
625 .flags = CLK_SET_RATE_PARENT,
626 },
627};
628
629static struct clk_regmap g12a_mpll1_div = {
630 .data = &(struct meson_clk_mpll_data){
631 .sdm = {
632 .reg_off = HHI_MPLL_CNTL3,
633 .shift = 0,
634 .width = 14,
635 },
636 .sdm_en = {
637 .reg_off = HHI_MPLL_CNTL3,
638 .shift = 30,
639 .width = 1,
640 },
641 .n2 = {
642 .reg_off = HHI_MPLL_CNTL3,
643 .shift = 20,
644 .width = 9,
645 },
646 .ssen = {
647 .reg_off = HHI_MPLL_CNTL3,
648 .shift = 29,
649 .width = 1,
650 },
651 .lock = &meson_clk_lock,
652 },
653 .hw.init = &(struct clk_init_data){
654 .name = "mpll1_div",
655 .ops = &meson_clk_mpll_ops,
656 .parent_names = (const char *[]){ "mpll_prediv" },
657 .num_parents = 1,
658 },
659};
660
661static struct clk_regmap g12a_mpll1 = {
662 .data = &(struct clk_regmap_gate_data){
663 .offset = HHI_MPLL_CNTL3,
664 .bit_idx = 31,
665 },
666 .hw.init = &(struct clk_init_data){
667 .name = "mpll1",
668 .ops = &clk_regmap_gate_ops,
669 .parent_names = (const char *[]){ "mpll1_div" },
670 .num_parents = 1,
671 .flags = CLK_SET_RATE_PARENT,
672 },
673};
674
675static struct clk_regmap g12a_mpll2_div = {
676 .data = &(struct meson_clk_mpll_data){
677 .sdm = {
678 .reg_off = HHI_MPLL_CNTL5,
679 .shift = 0,
680 .width = 14,
681 },
682 .sdm_en = {
683 .reg_off = HHI_MPLL_CNTL5,
684 .shift = 30,
685 .width = 1,
686 },
687 .n2 = {
688 .reg_off = HHI_MPLL_CNTL5,
689 .shift = 20,
690 .width = 9,
691 },
692 .ssen = {
693 .reg_off = HHI_MPLL_CNTL5,
694 .shift = 29,
695 .width = 1,
696 },
697 .lock = &meson_clk_lock,
698 },
699 .hw.init = &(struct clk_init_data){
700 .name = "mpll2_div",
701 .ops = &meson_clk_mpll_ops,
702 .parent_names = (const char *[]){ "mpll_prediv" },
703 .num_parents = 1,
704 },
705};
706
707static struct clk_regmap g12a_mpll2 = {
708 .data = &(struct clk_regmap_gate_data){
709 .offset = HHI_MPLL_CNTL5,
710 .bit_idx = 31,
711 },
712 .hw.init = &(struct clk_init_data){
713 .name = "mpll2",
714 .ops = &clk_regmap_gate_ops,
715 .parent_names = (const char *[]){ "mpll2_div" },
716 .num_parents = 1,
717 .flags = CLK_SET_RATE_PARENT,
718 },
719};
720
721static struct clk_regmap g12a_mpll3_div = {
722 .data = &(struct meson_clk_mpll_data){
723 .sdm = {
724 .reg_off = HHI_MPLL_CNTL7,
725 .shift = 0,
726 .width = 14,
727 },
728 .sdm_en = {
729 .reg_off = HHI_MPLL_CNTL7,
730 .shift = 30,
731 .width = 1,
732 },
733 .n2 = {
734 .reg_off = HHI_MPLL_CNTL7,
735 .shift = 20,
736 .width = 9,
737 },
738 .ssen = {
739 .reg_off = HHI_MPLL_CNTL7,
740 .shift = 29,
741 .width = 1,
742 },
743 .lock = &meson_clk_lock,
744 },
745 .hw.init = &(struct clk_init_data){
746 .name = "mpll3_div",
747 .ops = &meson_clk_mpll_ops,
748 .parent_names = (const char *[]){ "mpll_prediv" },
749 .num_parents = 1,
750 },
751};
752
753static struct clk_regmap g12a_mpll3 = {
754 .data = &(struct clk_regmap_gate_data){
755 .offset = HHI_MPLL_CNTL7,
756 .bit_idx = 31,
757 },
758 .hw.init = &(struct clk_init_data){
759 .name = "mpll3",
760 .ops = &clk_regmap_gate_ops,
761 .parent_names = (const char *[]){ "mpll3_div" },
762 .num_parents = 1,
763 .flags = CLK_SET_RATE_PARENT,
764 },
765};
766
767static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
768static const char * const clk81_parent_names[] = {
769 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
770 "fclk_div3", "fclk_div5"
771};
772
773static struct clk_regmap g12a_mpeg_clk_sel = {
774 .data = &(struct clk_regmap_mux_data){
775 .offset = HHI_MPEG_CLK_CNTL,
776 .mask = 0x7,
777 .shift = 12,
778 .table = mux_table_clk81,
779 },
780 .hw.init = &(struct clk_init_data){
781 .name = "mpeg_clk_sel",
782 .ops = &clk_regmap_mux_ro_ops,
783 .parent_names = clk81_parent_names,
784 .num_parents = ARRAY_SIZE(clk81_parent_names),
785 },
786};
787
788static struct clk_regmap g12a_mpeg_clk_div = {
789 .data = &(struct clk_regmap_div_data){
790 .offset = HHI_MPEG_CLK_CNTL,
791 .shift = 0,
792 .width = 7,
793 },
794 .hw.init = &(struct clk_init_data){
795 .name = "mpeg_clk_div",
796 .ops = &clk_regmap_divider_ops,
797 .parent_names = (const char *[]){ "mpeg_clk_sel" },
798 .num_parents = 1,
799 .flags = CLK_SET_RATE_PARENT,
800 },
801};
802
803static struct clk_regmap g12a_clk81 = {
804 .data = &(struct clk_regmap_gate_data){
805 .offset = HHI_MPEG_CLK_CNTL,
806 .bit_idx = 7,
807 },
808 .hw.init = &(struct clk_init_data){
809 .name = "clk81",
810 .ops = &clk_regmap_gate_ops,
811 .parent_names = (const char *[]){ "mpeg_clk_div" },
812 .num_parents = 1,
813 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
814 },
815};
816
817static const char * const g12a_sd_emmc_clk0_parent_names[] = {
818 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
819
820 /*
821 * Following these parent clocks, we should also have had mpll2, mpll3
822 * and gp0_pll but these clocks are too precious to be used here. All
823 * the necessary rates for MMC and NAND operation can be acheived using
824 * g12a_ee_core or fclk_div clocks
825 */
826};
827
828/* SDIO clock */
829static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
830 .data = &(struct clk_regmap_mux_data){
831 .offset = HHI_SD_EMMC_CLK_CNTL,
832 .mask = 0x7,
833 .shift = 9,
834 },
835 .hw.init = &(struct clk_init_data) {
836 .name = "sd_emmc_a_clk0_sel",
837 .ops = &clk_regmap_mux_ops,
838 .parent_names = g12a_sd_emmc_clk0_parent_names,
839 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
840 .flags = CLK_SET_RATE_PARENT,
841 },
842};
843
844static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
845 .data = &(struct clk_regmap_div_data){
846 .offset = HHI_SD_EMMC_CLK_CNTL,
847 .shift = 0,
848 .width = 7,
849 },
850 .hw.init = &(struct clk_init_data) {
851 .name = "sd_emmc_a_clk0_div",
852 .ops = &clk_regmap_divider_ops,
853 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
854 .num_parents = 1,
855 .flags = CLK_SET_RATE_PARENT,
856 },
857};
858
859static struct clk_regmap g12a_sd_emmc_a_clk0 = {
860 .data = &(struct clk_regmap_gate_data){
861 .offset = HHI_SD_EMMC_CLK_CNTL,
862 .bit_idx = 7,
863 },
864 .hw.init = &(struct clk_init_data){
865 .name = "sd_emmc_a_clk0",
866 .ops = &clk_regmap_gate_ops,
867 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT,
870 },
871};
872
873/* SDcard clock */
874static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
875 .data = &(struct clk_regmap_mux_data){
876 .offset = HHI_SD_EMMC_CLK_CNTL,
877 .mask = 0x7,
878 .shift = 25,
879 },
880 .hw.init = &(struct clk_init_data) {
881 .name = "sd_emmc_b_clk0_sel",
882 .ops = &clk_regmap_mux_ops,
883 .parent_names = g12a_sd_emmc_clk0_parent_names,
884 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
885 .flags = CLK_SET_RATE_PARENT,
886 },
887};
888
889static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
890 .data = &(struct clk_regmap_div_data){
891 .offset = HHI_SD_EMMC_CLK_CNTL,
892 .shift = 16,
893 .width = 7,
894 },
895 .hw.init = &(struct clk_init_data) {
896 .name = "sd_emmc_b_clk0_div",
897 .ops = &clk_regmap_divider_ops,
898 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
899 .num_parents = 1,
900 .flags = CLK_SET_RATE_PARENT,
901 },
902};
903
904static struct clk_regmap g12a_sd_emmc_b_clk0 = {
905 .data = &(struct clk_regmap_gate_data){
906 .offset = HHI_SD_EMMC_CLK_CNTL,
907 .bit_idx = 23,
908 },
909 .hw.init = &(struct clk_init_data){
910 .name = "sd_emmc_b_clk0",
911 .ops = &clk_regmap_gate_ops,
912 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
913 .num_parents = 1,
914 .flags = CLK_SET_RATE_PARENT,
915 },
916};
917
918/* EMMC/NAND clock */
919static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
920 .data = &(struct clk_regmap_mux_data){
921 .offset = HHI_NAND_CLK_CNTL,
922 .mask = 0x7,
923 .shift = 9,
924 },
925 .hw.init = &(struct clk_init_data) {
926 .name = "sd_emmc_c_clk0_sel",
927 .ops = &clk_regmap_mux_ops,
928 .parent_names = g12a_sd_emmc_clk0_parent_names,
929 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
930 .flags = CLK_SET_RATE_PARENT,
931 },
932};
933
934static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
935 .data = &(struct clk_regmap_div_data){
936 .offset = HHI_NAND_CLK_CNTL,
937 .shift = 0,
938 .width = 7,
939 },
940 .hw.init = &(struct clk_init_data) {
941 .name = "sd_emmc_c_clk0_div",
942 .ops = &clk_regmap_divider_ops,
943 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
944 .num_parents = 1,
945 .flags = CLK_SET_RATE_PARENT,
946 },
947};
948
949static struct clk_regmap g12a_sd_emmc_c_clk0 = {
950 .data = &(struct clk_regmap_gate_data){
951 .offset = HHI_NAND_CLK_CNTL,
952 .bit_idx = 7,
953 },
954 .hw.init = &(struct clk_init_data){
955 .name = "sd_emmc_c_clk0",
956 .ops = &clk_regmap_gate_ops,
957 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
958 .num_parents = 1,
959 .flags = CLK_SET_RATE_PARENT,
960 },
961};
962
963/* VPU Clock */
964
965static const char * const g12a_vpu_parent_names[] = {
966 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
967 "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
968};
969
970static struct clk_regmap g12a_vpu_0_sel = {
971 .data = &(struct clk_regmap_mux_data){
972 .offset = HHI_VPU_CLK_CNTL,
973 .mask = 0x3,
974 .shift = 9,
975 },
976 .hw.init = &(struct clk_init_data){
977 .name = "vpu_0_sel",
978 .ops = &clk_regmap_mux_ops,
979 .parent_names = g12a_vpu_parent_names,
980 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
981 .flags = CLK_SET_RATE_NO_REPARENT,
982 },
983};
984
985static struct clk_regmap g12a_vpu_0_div = {
986 .data = &(struct clk_regmap_div_data){
987 .offset = HHI_VPU_CLK_CNTL,
988 .shift = 0,
989 .width = 7,
990 },
991 .hw.init = &(struct clk_init_data){
992 .name = "vpu_0_div",
993 .ops = &clk_regmap_divider_ops,
994 .parent_names = (const char *[]){ "vpu_0_sel" },
995 .num_parents = 1,
996 .flags = CLK_SET_RATE_PARENT,
997 },
998};
999
1000static struct clk_regmap g12a_vpu_0 = {
1001 .data = &(struct clk_regmap_gate_data){
1002 .offset = HHI_VPU_CLK_CNTL,
1003 .bit_idx = 8,
1004 },
1005 .hw.init = &(struct clk_init_data) {
1006 .name = "vpu_0",
1007 .ops = &clk_regmap_gate_ops,
1008 .parent_names = (const char *[]){ "vpu_0_div" },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1011 },
1012};
1013
1014static struct clk_regmap g12a_vpu_1_sel = {
1015 .data = &(struct clk_regmap_mux_data){
1016 .offset = HHI_VPU_CLK_CNTL,
1017 .mask = 0x3,
1018 .shift = 25,
1019 },
1020 .hw.init = &(struct clk_init_data){
1021 .name = "vpu_1_sel",
1022 .ops = &clk_regmap_mux_ops,
1023 .parent_names = g12a_vpu_parent_names,
1024 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1025 .flags = CLK_SET_RATE_NO_REPARENT,
1026 },
1027};
1028
1029static struct clk_regmap g12a_vpu_1_div = {
1030 .data = &(struct clk_regmap_div_data){
1031 .offset = HHI_VPU_CLK_CNTL,
1032 .shift = 16,
1033 .width = 7,
1034 },
1035 .hw.init = &(struct clk_init_data){
1036 .name = "vpu_1_div",
1037 .ops = &clk_regmap_divider_ops,
1038 .parent_names = (const char *[]){ "vpu_1_sel" },
1039 .num_parents = 1,
1040 .flags = CLK_SET_RATE_PARENT,
1041 },
1042};
1043
1044static struct clk_regmap g12a_vpu_1 = {
1045 .data = &(struct clk_regmap_gate_data){
1046 .offset = HHI_VPU_CLK_CNTL,
1047 .bit_idx = 24,
1048 },
1049 .hw.init = &(struct clk_init_data) {
1050 .name = "vpu_1",
1051 .ops = &clk_regmap_gate_ops,
1052 .parent_names = (const char *[]){ "vpu_1_div" },
1053 .num_parents = 1,
1054 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1055 },
1056};
1057
1058static struct clk_regmap g12a_vpu = {
1059 .data = &(struct clk_regmap_mux_data){
1060 .offset = HHI_VPU_CLK_CNTL,
1061 .mask = 1,
1062 .shift = 31,
1063 },
1064 .hw.init = &(struct clk_init_data){
1065 .name = "vpu",
1066 .ops = &clk_regmap_mux_ops,
1067 /*
1068 * bit 31 selects from 2 possible parents:
1069 * vpu_0 or vpu_1
1070 */
1071 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1072 .num_parents = 2,
1073 .flags = CLK_SET_RATE_NO_REPARENT,
1074 },
1075};
1076
1077/* VAPB Clock */
1078
1079static const char * const g12a_vapb_parent_names[] = {
1080 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
1081 "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
1082};
1083
1084static struct clk_regmap g12a_vapb_0_sel = {
1085 .data = &(struct clk_regmap_mux_data){
1086 .offset = HHI_VAPBCLK_CNTL,
1087 .mask = 0x3,
1088 .shift = 9,
1089 },
1090 .hw.init = &(struct clk_init_data){
1091 .name = "vapb_0_sel",
1092 .ops = &clk_regmap_mux_ops,
1093 .parent_names = g12a_vapb_parent_names,
1094 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1095 .flags = CLK_SET_RATE_NO_REPARENT,
1096 },
1097};
1098
1099static struct clk_regmap g12a_vapb_0_div = {
1100 .data = &(struct clk_regmap_div_data){
1101 .offset = HHI_VAPBCLK_CNTL,
1102 .shift = 0,
1103 .width = 7,
1104 },
1105 .hw.init = &(struct clk_init_data){
1106 .name = "vapb_0_div",
1107 .ops = &clk_regmap_divider_ops,
1108 .parent_names = (const char *[]){ "vapb_0_sel" },
1109 .num_parents = 1,
1110 .flags = CLK_SET_RATE_PARENT,
1111 },
1112};
1113
1114static struct clk_regmap g12a_vapb_0 = {
1115 .data = &(struct clk_regmap_gate_data){
1116 .offset = HHI_VAPBCLK_CNTL,
1117 .bit_idx = 8,
1118 },
1119 .hw.init = &(struct clk_init_data) {
1120 .name = "vapb_0",
1121 .ops = &clk_regmap_gate_ops,
1122 .parent_names = (const char *[]){ "vapb_0_div" },
1123 .num_parents = 1,
1124 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1125 },
1126};
1127
1128static struct clk_regmap g12a_vapb_1_sel = {
1129 .data = &(struct clk_regmap_mux_data){
1130 .offset = HHI_VAPBCLK_CNTL,
1131 .mask = 0x3,
1132 .shift = 25,
1133 },
1134 .hw.init = &(struct clk_init_data){
1135 .name = "vapb_1_sel",
1136 .ops = &clk_regmap_mux_ops,
1137 .parent_names = g12a_vapb_parent_names,
1138 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1139 .flags = CLK_SET_RATE_NO_REPARENT,
1140 },
1141};
1142
1143static struct clk_regmap g12a_vapb_1_div = {
1144 .data = &(struct clk_regmap_div_data){
1145 .offset = HHI_VAPBCLK_CNTL,
1146 .shift = 16,
1147 .width = 7,
1148 },
1149 .hw.init = &(struct clk_init_data){
1150 .name = "vapb_1_div",
1151 .ops = &clk_regmap_divider_ops,
1152 .parent_names = (const char *[]){ "vapb_1_sel" },
1153 .num_parents = 1,
1154 .flags = CLK_SET_RATE_PARENT,
1155 },
1156};
1157
1158static struct clk_regmap g12a_vapb_1 = {
1159 .data = &(struct clk_regmap_gate_data){
1160 .offset = HHI_VAPBCLK_CNTL,
1161 .bit_idx = 24,
1162 },
1163 .hw.init = &(struct clk_init_data) {
1164 .name = "vapb_1",
1165 .ops = &clk_regmap_gate_ops,
1166 .parent_names = (const char *[]){ "vapb_1_div" },
1167 .num_parents = 1,
1168 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1169 },
1170};
1171
1172static struct clk_regmap g12a_vapb_sel = {
1173 .data = &(struct clk_regmap_mux_data){
1174 .offset = HHI_VAPBCLK_CNTL,
1175 .mask = 1,
1176 .shift = 31,
1177 },
1178 .hw.init = &(struct clk_init_data){
1179 .name = "vapb_sel",
1180 .ops = &clk_regmap_mux_ops,
1181 /*
1182 * bit 31 selects from 2 possible parents:
1183 * vapb_0 or vapb_1
1184 */
1185 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1186 .num_parents = 2,
1187 .flags = CLK_SET_RATE_NO_REPARENT,
1188 },
1189};
1190
1191static struct clk_regmap g12a_vapb = {
1192 .data = &(struct clk_regmap_gate_data){
1193 .offset = HHI_VAPBCLK_CNTL,
1194 .bit_idx = 30,
1195 },
1196 .hw.init = &(struct clk_init_data) {
1197 .name = "vapb",
1198 .ops = &clk_regmap_gate_ops,
1199 .parent_names = (const char *[]){ "vapb_sel" },
1200 .num_parents = 1,
1201 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1202 },
1203};
1204
1205/* Video Clocks */
1206
1207static struct clk_regmap g12a_vid_pll_div = {
1208 .data = &(struct meson_vid_pll_div_data){
1209 .val = {
1210 .reg_off = HHI_VID_PLL_CLK_DIV,
1211 .shift = 0,
1212 .width = 15,
1213 },
1214 .sel = {
1215 .reg_off = HHI_VID_PLL_CLK_DIV,
1216 .shift = 16,
1217 .width = 2,
1218 },
1219 },
1220 .hw.init = &(struct clk_init_data) {
1221 .name = "vid_pll_div",
1222 .ops = &meson_vid_pll_div_ro_ops,
1223 .parent_names = (const char *[]){ "hdmi_pll" },
1224 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1226 },
1227};
1228
1229static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
1230 "hdmi_pll" };
1231
1232static struct clk_regmap g12a_vid_pll_sel = {
1233 .data = &(struct clk_regmap_mux_data){
1234 .offset = HHI_VID_PLL_CLK_DIV,
1235 .mask = 0x1,
1236 .shift = 18,
1237 },
1238 .hw.init = &(struct clk_init_data){
1239 .name = "vid_pll_sel",
1240 .ops = &clk_regmap_mux_ops,
1241 /*
1242 * bit 18 selects from 2 possible parents:
1243 * vid_pll_div or hdmi_pll
1244 */
1245 .parent_names = g12a_vid_pll_parent_names,
1246 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
1247 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1248 },
1249};
1250
1251static struct clk_regmap g12a_vid_pll = {
1252 .data = &(struct clk_regmap_gate_data){
1253 .offset = HHI_VID_PLL_CLK_DIV,
1254 .bit_idx = 19,
1255 },
1256 .hw.init = &(struct clk_init_data) {
1257 .name = "vid_pll",
1258 .ops = &clk_regmap_gate_ops,
1259 .parent_names = (const char *[]){ "vid_pll_sel" },
1260 .num_parents = 1,
1261 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1262 },
1263};
1264
1265static const char * const g12a_vclk_parent_names[] = {
1266 "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
1267 "fclk_div5", "fclk_div7"
1268};
1269
1270static struct clk_regmap g12a_vclk_sel = {
1271 .data = &(struct clk_regmap_mux_data){
1272 .offset = HHI_VID_CLK_CNTL,
1273 .mask = 0x7,
1274 .shift = 16,
1275 },
1276 .hw.init = &(struct clk_init_data){
1277 .name = "vclk_sel",
1278 .ops = &clk_regmap_mux_ops,
1279 .parent_names = g12a_vclk_parent_names,
1280 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1281 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1282 },
1283};
1284
1285static struct clk_regmap g12a_vclk2_sel = {
1286 .data = &(struct clk_regmap_mux_data){
1287 .offset = HHI_VIID_CLK_CNTL,
1288 .mask = 0x7,
1289 .shift = 16,
1290 },
1291 .hw.init = &(struct clk_init_data){
1292 .name = "vclk2_sel",
1293 .ops = &clk_regmap_mux_ops,
1294 .parent_names = g12a_vclk_parent_names,
1295 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1296 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1297 },
1298};
1299
1300static struct clk_regmap g12a_vclk_input = {
1301 .data = &(struct clk_regmap_gate_data){
1302 .offset = HHI_VID_CLK_DIV,
1303 .bit_idx = 16,
1304 },
1305 .hw.init = &(struct clk_init_data) {
1306 .name = "vclk_input",
1307 .ops = &clk_regmap_gate_ops,
1308 .parent_names = (const char *[]){ "vclk_sel" },
1309 .num_parents = 1,
1310 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1311 },
1312};
1313
1314static struct clk_regmap g12a_vclk2_input = {
1315 .data = &(struct clk_regmap_gate_data){
1316 .offset = HHI_VIID_CLK_DIV,
1317 .bit_idx = 16,
1318 },
1319 .hw.init = &(struct clk_init_data) {
1320 .name = "vclk2_input",
1321 .ops = &clk_regmap_gate_ops,
1322 .parent_names = (const char *[]){ "vclk2_sel" },
1323 .num_parents = 1,
1324 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1325 },
1326};
1327
1328static struct clk_regmap g12a_vclk_div = {
1329 .data = &(struct clk_regmap_div_data){
1330 .offset = HHI_VID_CLK_DIV,
1331 .shift = 0,
1332 .width = 8,
1333 },
1334 .hw.init = &(struct clk_init_data){
1335 .name = "vclk_div",
1336 .ops = &clk_regmap_divider_ops,
1337 .parent_names = (const char *[]){ "vclk_input" },
1338 .num_parents = 1,
1339 .flags = CLK_GET_RATE_NOCACHE,
1340 },
1341};
1342
1343static struct clk_regmap g12a_vclk2_div = {
1344 .data = &(struct clk_regmap_div_data){
1345 .offset = HHI_VIID_CLK_DIV,
1346 .shift = 0,
1347 .width = 8,
1348 },
1349 .hw.init = &(struct clk_init_data){
1350 .name = "vclk2_div",
1351 .ops = &clk_regmap_divider_ops,
1352 .parent_names = (const char *[]){ "vclk2_input" },
1353 .num_parents = 1,
1354 .flags = CLK_GET_RATE_NOCACHE,
1355 },
1356};
1357
1358static struct clk_regmap g12a_vclk = {
1359 .data = &(struct clk_regmap_gate_data){
1360 .offset = HHI_VID_CLK_CNTL,
1361 .bit_idx = 19,
1362 },
1363 .hw.init = &(struct clk_init_data) {
1364 .name = "vclk",
1365 .ops = &clk_regmap_gate_ops,
1366 .parent_names = (const char *[]){ "vclk_div" },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1369 },
1370};
1371
1372static struct clk_regmap g12a_vclk2 = {
1373 .data = &(struct clk_regmap_gate_data){
1374 .offset = HHI_VIID_CLK_CNTL,
1375 .bit_idx = 19,
1376 },
1377 .hw.init = &(struct clk_init_data) {
1378 .name = "vclk2",
1379 .ops = &clk_regmap_gate_ops,
1380 .parent_names = (const char *[]){ "vclk2_div" },
1381 .num_parents = 1,
1382 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1383 },
1384};
1385
1386static struct clk_regmap g12a_vclk_div1 = {
1387 .data = &(struct clk_regmap_gate_data){
1388 .offset = HHI_VID_CLK_CNTL,
1389 .bit_idx = 0,
1390 },
1391 .hw.init = &(struct clk_init_data) {
1392 .name = "vclk_div1",
1393 .ops = &clk_regmap_gate_ops,
1394 .parent_names = (const char *[]){ "vclk" },
1395 .num_parents = 1,
1396 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1397 },
1398};
1399
1400static struct clk_regmap g12a_vclk_div2_en = {
1401 .data = &(struct clk_regmap_gate_data){
1402 .offset = HHI_VID_CLK_CNTL,
1403 .bit_idx = 1,
1404 },
1405 .hw.init = &(struct clk_init_data) {
1406 .name = "vclk_div2_en",
1407 .ops = &clk_regmap_gate_ops,
1408 .parent_names = (const char *[]){ "vclk" },
1409 .num_parents = 1,
1410 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1411 },
1412};
1413
1414static struct clk_regmap g12a_vclk_div4_en = {
1415 .data = &(struct clk_regmap_gate_data){
1416 .offset = HHI_VID_CLK_CNTL,
1417 .bit_idx = 2,
1418 },
1419 .hw.init = &(struct clk_init_data) {
1420 .name = "vclk_div4_en",
1421 .ops = &clk_regmap_gate_ops,
1422 .parent_names = (const char *[]){ "vclk" },
1423 .num_parents = 1,
1424 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1425 },
1426};
1427
1428static struct clk_regmap g12a_vclk_div6_en = {
1429 .data = &(struct clk_regmap_gate_data){
1430 .offset = HHI_VID_CLK_CNTL,
1431 .bit_idx = 3,
1432 },
1433 .hw.init = &(struct clk_init_data) {
1434 .name = "vclk_div6_en",
1435 .ops = &clk_regmap_gate_ops,
1436 .parent_names = (const char *[]){ "vclk" },
1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1439 },
1440};
1441
1442static struct clk_regmap g12a_vclk_div12_en = {
1443 .data = &(struct clk_regmap_gate_data){
1444 .offset = HHI_VID_CLK_CNTL,
1445 .bit_idx = 4,
1446 },
1447 .hw.init = &(struct clk_init_data) {
1448 .name = "vclk_div12_en",
1449 .ops = &clk_regmap_gate_ops,
1450 .parent_names = (const char *[]){ "vclk" },
1451 .num_parents = 1,
1452 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1453 },
1454};
1455
1456static struct clk_regmap g12a_vclk2_div1 = {
1457 .data = &(struct clk_regmap_gate_data){
1458 .offset = HHI_VIID_CLK_CNTL,
1459 .bit_idx = 0,
1460 },
1461 .hw.init = &(struct clk_init_data) {
1462 .name = "vclk2_div1",
1463 .ops = &clk_regmap_gate_ops,
1464 .parent_names = (const char *[]){ "vclk2" },
1465 .num_parents = 1,
1466 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1467 },
1468};
1469
1470static struct clk_regmap g12a_vclk2_div2_en = {
1471 .data = &(struct clk_regmap_gate_data){
1472 .offset = HHI_VIID_CLK_CNTL,
1473 .bit_idx = 1,
1474 },
1475 .hw.init = &(struct clk_init_data) {
1476 .name = "vclk2_div2_en",
1477 .ops = &clk_regmap_gate_ops,
1478 .parent_names = (const char *[]){ "vclk2" },
1479 .num_parents = 1,
1480 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1481 },
1482};
1483
1484static struct clk_regmap g12a_vclk2_div4_en = {
1485 .data = &(struct clk_regmap_gate_data){
1486 .offset = HHI_VIID_CLK_CNTL,
1487 .bit_idx = 2,
1488 },
1489 .hw.init = &(struct clk_init_data) {
1490 .name = "vclk2_div4_en",
1491 .ops = &clk_regmap_gate_ops,
1492 .parent_names = (const char *[]){ "vclk2" },
1493 .num_parents = 1,
1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1495 },
1496};
1497
1498static struct clk_regmap g12a_vclk2_div6_en = {
1499 .data = &(struct clk_regmap_gate_data){
1500 .offset = HHI_VIID_CLK_CNTL,
1501 .bit_idx = 3,
1502 },
1503 .hw.init = &(struct clk_init_data) {
1504 .name = "vclk2_div6_en",
1505 .ops = &clk_regmap_gate_ops,
1506 .parent_names = (const char *[]){ "vclk2" },
1507 .num_parents = 1,
1508 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1509 },
1510};
1511
1512static struct clk_regmap g12a_vclk2_div12_en = {
1513 .data = &(struct clk_regmap_gate_data){
1514 .offset = HHI_VIID_CLK_CNTL,
1515 .bit_idx = 4,
1516 },
1517 .hw.init = &(struct clk_init_data) {
1518 .name = "vclk2_div12_en",
1519 .ops = &clk_regmap_gate_ops,
1520 .parent_names = (const char *[]){ "vclk2" },
1521 .num_parents = 1,
1522 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1523 },
1524};
1525
1526static struct clk_fixed_factor g12a_vclk_div2 = {
1527 .mult = 1,
1528 .div = 2,
1529 .hw.init = &(struct clk_init_data){
1530 .name = "vclk_div2",
1531 .ops = &clk_fixed_factor_ops,
1532 .parent_names = (const char *[]){ "vclk_div2_en" },
1533 .num_parents = 1,
1534 },
1535};
1536
1537static struct clk_fixed_factor g12a_vclk_div4 = {
1538 .mult = 1,
1539 .div = 4,
1540 .hw.init = &(struct clk_init_data){
1541 .name = "vclk_div4",
1542 .ops = &clk_fixed_factor_ops,
1543 .parent_names = (const char *[]){ "vclk_div4_en" },
1544 .num_parents = 1,
1545 },
1546};
1547
1548static struct clk_fixed_factor g12a_vclk_div6 = {
1549 .mult = 1,
1550 .div = 6,
1551 .hw.init = &(struct clk_init_data){
1552 .name = "vclk_div6",
1553 .ops = &clk_fixed_factor_ops,
1554 .parent_names = (const char *[]){ "vclk_div6_en" },
1555 .num_parents = 1,
1556 },
1557};
1558
1559static struct clk_fixed_factor g12a_vclk_div12 = {
1560 .mult = 1,
1561 .div = 12,
1562 .hw.init = &(struct clk_init_data){
1563 .name = "vclk_div12",
1564 .ops = &clk_fixed_factor_ops,
1565 .parent_names = (const char *[]){ "vclk_div12_en" },
1566 .num_parents = 1,
1567 },
1568};
1569
1570static struct clk_fixed_factor g12a_vclk2_div2 = {
1571 .mult = 1,
1572 .div = 2,
1573 .hw.init = &(struct clk_init_data){
1574 .name = "vclk2_div2",
1575 .ops = &clk_fixed_factor_ops,
1576 .parent_names = (const char *[]){ "vclk2_div2_en" },
1577 .num_parents = 1,
1578 },
1579};
1580
1581static struct clk_fixed_factor g12a_vclk2_div4 = {
1582 .mult = 1,
1583 .div = 4,
1584 .hw.init = &(struct clk_init_data){
1585 .name = "vclk2_div4",
1586 .ops = &clk_fixed_factor_ops,
1587 .parent_names = (const char *[]){ "vclk2_div4_en" },
1588 .num_parents = 1,
1589 },
1590};
1591
1592static struct clk_fixed_factor g12a_vclk2_div6 = {
1593 .mult = 1,
1594 .div = 6,
1595 .hw.init = &(struct clk_init_data){
1596 .name = "vclk2_div6",
1597 .ops = &clk_fixed_factor_ops,
1598 .parent_names = (const char *[]){ "vclk2_div6_en" },
1599 .num_parents = 1,
1600 },
1601};
1602
1603static struct clk_fixed_factor g12a_vclk2_div12 = {
1604 .mult = 1,
1605 .div = 12,
1606 .hw.init = &(struct clk_init_data){
1607 .name = "vclk2_div12",
1608 .ops = &clk_fixed_factor_ops,
1609 .parent_names = (const char *[]){ "vclk2_div12_en" },
1610 .num_parents = 1,
1611 },
1612};
1613
1614static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1615static const char * const g12a_cts_parent_names[] = {
1616 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
1617 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
1618 "vclk2_div6", "vclk2_div12"
1619};
1620
1621static struct clk_regmap g12a_cts_enci_sel = {
1622 .data = &(struct clk_regmap_mux_data){
1623 .offset = HHI_VID_CLK_DIV,
1624 .mask = 0xf,
1625 .shift = 28,
1626 .table = mux_table_cts_sel,
1627 },
1628 .hw.init = &(struct clk_init_data){
1629 .name = "cts_enci_sel",
1630 .ops = &clk_regmap_mux_ops,
1631 .parent_names = g12a_cts_parent_names,
1632 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
1633 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1634 },
1635};
1636
1637static struct clk_regmap g12a_cts_encp_sel = {
1638 .data = &(struct clk_regmap_mux_data){
1639 .offset = HHI_VID_CLK_DIV,
1640 .mask = 0xf,
1641 .shift = 20,
1642 .table = mux_table_cts_sel,
1643 },
1644 .hw.init = &(struct clk_init_data){
1645 .name = "cts_encp_sel",
1646 .ops = &clk_regmap_mux_ops,
1647 .parent_names = g12a_cts_parent_names,
1648 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
1649 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1650 },
1651};
1652
1653static struct clk_regmap g12a_cts_vdac_sel = {
1654 .data = &(struct clk_regmap_mux_data){
1655 .offset = HHI_VIID_CLK_DIV,
1656 .mask = 0xf,
1657 .shift = 28,
1658 .table = mux_table_cts_sel,
1659 },
1660 .hw.init = &(struct clk_init_data){
1661 .name = "cts_vdac_sel",
1662 .ops = &clk_regmap_mux_ops,
1663 .parent_names = g12a_cts_parent_names,
1664 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
1665 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1666 },
1667};
1668
1669/* TOFIX: add support for cts_tcon */
1670static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1671static const char * const g12a_cts_hdmi_tx_parent_names[] = {
1672 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
1673 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
1674 "vclk2_div6", "vclk2_div12"
1675};
1676
1677static struct clk_regmap g12a_hdmi_tx_sel = {
1678 .data = &(struct clk_regmap_mux_data){
1679 .offset = HHI_HDMI_CLK_CNTL,
1680 .mask = 0xf,
1681 .shift = 16,
1682 .table = mux_table_hdmi_tx_sel,
1683 },
1684 .hw.init = &(struct clk_init_data){
1685 .name = "hdmi_tx_sel",
1686 .ops = &clk_regmap_mux_ops,
1687 .parent_names = g12a_cts_hdmi_tx_parent_names,
1688 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),
1689 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1690 },
1691};
1692
1693static struct clk_regmap g12a_cts_enci = {
1694 .data = &(struct clk_regmap_gate_data){
1695 .offset = HHI_VID_CLK_CNTL2,
1696 .bit_idx = 0,
1697 },
1698 .hw.init = &(struct clk_init_data) {
1699 .name = "cts_enci",
1700 .ops = &clk_regmap_gate_ops,
1701 .parent_names = (const char *[]){ "cts_enci_sel" },
1702 .num_parents = 1,
1703 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1704 },
1705};
1706
1707static struct clk_regmap g12a_cts_encp = {
1708 .data = &(struct clk_regmap_gate_data){
1709 .offset = HHI_VID_CLK_CNTL2,
1710 .bit_idx = 2,
1711 },
1712 .hw.init = &(struct clk_init_data) {
1713 .name = "cts_encp",
1714 .ops = &clk_regmap_gate_ops,
1715 .parent_names = (const char *[]){ "cts_encp_sel" },
1716 .num_parents = 1,
1717 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1718 },
1719};
1720
1721static struct clk_regmap g12a_cts_vdac = {
1722 .data = &(struct clk_regmap_gate_data){
1723 .offset = HHI_VID_CLK_CNTL2,
1724 .bit_idx = 4,
1725 },
1726 .hw.init = &(struct clk_init_data) {
1727 .name = "cts_vdac",
1728 .ops = &clk_regmap_gate_ops,
1729 .parent_names = (const char *[]){ "cts_vdac_sel" },
1730 .num_parents = 1,
1731 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1732 },
1733};
1734
1735static struct clk_regmap g12a_hdmi_tx = {
1736 .data = &(struct clk_regmap_gate_data){
1737 .offset = HHI_VID_CLK_CNTL2,
1738 .bit_idx = 5,
1739 },
1740 .hw.init = &(struct clk_init_data) {
1741 .name = "hdmi_tx",
1742 .ops = &clk_regmap_gate_ops,
1743 .parent_names = (const char *[]){ "hdmi_tx_sel" },
1744 .num_parents = 1,
1745 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1746 },
1747};
1748
1749/* HDMI Clocks */
1750
1751static const char * const g12a_hdmi_parent_names[] = {
1752 IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
1753};
1754
1755static struct clk_regmap g12a_hdmi_sel = {
1756 .data = &(struct clk_regmap_mux_data){
1757 .offset = HHI_HDMI_CLK_CNTL,
1758 .mask = 0x3,
1759 .shift = 9,
1760 .flags = CLK_MUX_ROUND_CLOSEST,
1761 },
1762 .hw.init = &(struct clk_init_data){
1763 .name = "hdmi_sel",
1764 .ops = &clk_regmap_mux_ops,
1765 .parent_names = g12a_hdmi_parent_names,
1766 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),
1767 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1768 },
1769};
1770
1771static struct clk_regmap g12a_hdmi_div = {
1772 .data = &(struct clk_regmap_div_data){
1773 .offset = HHI_HDMI_CLK_CNTL,
1774 .shift = 0,
1775 .width = 7,
1776 },
1777 .hw.init = &(struct clk_init_data){
1778 .name = "hdmi_div",
1779 .ops = &clk_regmap_divider_ops,
1780 .parent_names = (const char *[]){ "hdmi_sel" },
1781 .num_parents = 1,
1782 .flags = CLK_GET_RATE_NOCACHE,
1783 },
1784};
1785
1786static struct clk_regmap g12a_hdmi = {
1787 .data = &(struct clk_regmap_gate_data){
1788 .offset = HHI_HDMI_CLK_CNTL,
1789 .bit_idx = 8,
1790 },
1791 .hw.init = &(struct clk_init_data) {
1792 .name = "hdmi",
1793 .ops = &clk_regmap_gate_ops,
1794 .parent_names = (const char *[]){ "hdmi_div" },
1795 .num_parents = 1,
1796 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1797 },
1798};
1799
1800/*
1801 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1802 * muxed by a glitch-free switch.
1803 */
1804
1805static const char * const g12a_mali_0_1_parent_names[] = {
1806 IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
1807 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
1808};
1809
1810static struct clk_regmap g12a_mali_0_sel = {
1811 .data = &(struct clk_regmap_mux_data){
1812 .offset = HHI_MALI_CLK_CNTL,
1813 .mask = 0x7,
1814 .shift = 9,
1815 },
1816 .hw.init = &(struct clk_init_data){
1817 .name = "mali_0_sel",
1818 .ops = &clk_regmap_mux_ops,
1819 .parent_names = g12a_mali_0_1_parent_names,
1820 .num_parents = 8,
1821 .flags = CLK_SET_RATE_NO_REPARENT,
1822 },
1823};
1824
1825static struct clk_regmap g12a_mali_0_div = {
1826 .data = &(struct clk_regmap_div_data){
1827 .offset = HHI_MALI_CLK_CNTL,
1828 .shift = 0,
1829 .width = 7,
1830 },
1831 .hw.init = &(struct clk_init_data){
1832 .name = "mali_0_div",
1833 .ops = &clk_regmap_divider_ops,
1834 .parent_names = (const char *[]){ "mali_0_sel" },
1835 .num_parents = 1,
1836 .flags = CLK_SET_RATE_NO_REPARENT,
1837 },
1838};
1839
1840static struct clk_regmap g12a_mali_0 = {
1841 .data = &(struct clk_regmap_gate_data){
1842 .offset = HHI_MALI_CLK_CNTL,
1843 .bit_idx = 8,
1844 },
1845 .hw.init = &(struct clk_init_data){
1846 .name = "mali_0",
1847 .ops = &clk_regmap_gate_ops,
1848 .parent_names = (const char *[]){ "mali_0_div" },
1849 .num_parents = 1,
1850 .flags = CLK_SET_RATE_PARENT,
1851 },
1852};
1853
1854static struct clk_regmap g12a_mali_1_sel = {
1855 .data = &(struct clk_regmap_mux_data){
1856 .offset = HHI_MALI_CLK_CNTL,
1857 .mask = 0x7,
1858 .shift = 25,
1859 },
1860 .hw.init = &(struct clk_init_data){
1861 .name = "mali_1_sel",
1862 .ops = &clk_regmap_mux_ops,
1863 .parent_names = g12a_mali_0_1_parent_names,
1864 .num_parents = 8,
1865 .flags = CLK_SET_RATE_NO_REPARENT,
1866 },
1867};
1868
1869static struct clk_regmap g12a_mali_1_div = {
1870 .data = &(struct clk_regmap_div_data){
1871 .offset = HHI_MALI_CLK_CNTL,
1872 .shift = 16,
1873 .width = 7,
1874 },
1875 .hw.init = &(struct clk_init_data){
1876 .name = "mali_1_div",
1877 .ops = &clk_regmap_divider_ops,
1878 .parent_names = (const char *[]){ "mali_1_sel" },
1879 .num_parents = 1,
1880 .flags = CLK_SET_RATE_NO_REPARENT,
1881 },
1882};
1883
1884static struct clk_regmap g12a_mali_1 = {
1885 .data = &(struct clk_regmap_gate_data){
1886 .offset = HHI_MALI_CLK_CNTL,
1887 .bit_idx = 24,
1888 },
1889 .hw.init = &(struct clk_init_data){
1890 .name = "mali_1",
1891 .ops = &clk_regmap_gate_ops,
1892 .parent_names = (const char *[]){ "mali_1_div" },
1893 .num_parents = 1,
1894 .flags = CLK_SET_RATE_PARENT,
1895 },
1896};
1897
1898static const char * const g12a_mali_parent_names[] = {
1899 "mali_0", "mali_1"
1900};
1901
1902static struct clk_regmap g12a_mali = {
1903 .data = &(struct clk_regmap_mux_data){
1904 .offset = HHI_MALI_CLK_CNTL,
1905 .mask = 1,
1906 .shift = 31,
1907 },
1908 .hw.init = &(struct clk_init_data){
1909 .name = "mali",
1910 .ops = &clk_regmap_mux_ops,
1911 .parent_names = g12a_mali_parent_names,
1912 .num_parents = 2,
1913 .flags = CLK_SET_RATE_NO_REPARENT,
1914 },
1915};
1916
1917/* Everything Else (EE) domain gates */
1918static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
1919static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
1920static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
1921static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1922static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
1923static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
1924static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
1925static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
1926static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
1927static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
1928static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
1929static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
1930static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
1931static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
1932static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
1933static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
1934static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
1935static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
1936static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
1937static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
1938static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
1939static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
1940
1941static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
1942static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
1943static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
1944static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
1945static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
1946static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
1947static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
1948static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
1949static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
1950static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
1951static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
1952static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
1953static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
1954
1955static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1956static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1957static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
1958static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
1959static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
1960static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1961static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
1962static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
1963static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
1964static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
1965
1966static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
1967static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
1968static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1969static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1970static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
1971static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
1972static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
1973static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
1974static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
1975static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
1976static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
1977static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
1978static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
1979static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
1980static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
1981static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
1982static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
1983static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
1984static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
1985
1986static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
1987static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
1988static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
1989static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
1990static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
1991
1992/* Array of all clocks provided by this provider */
1993static struct clk_hw_onecell_data g12a_hw_onecell_data = {
1994 .hws = {
1995 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
1996 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
1997 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
1998 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
1999 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
2000 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
2001 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
2002 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
2003 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
2004 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
2005 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
2006 [CLKID_CLK81] = &g12a_clk81.hw,
2007 [CLKID_MPLL0] = &g12a_mpll0.hw,
2008 [CLKID_MPLL1] = &g12a_mpll1.hw,
2009 [CLKID_MPLL2] = &g12a_mpll2.hw,
2010 [CLKID_MPLL3] = &g12a_mpll3.hw,
2011 [CLKID_DDR] = &g12a_ddr.hw,
2012 [CLKID_DOS] = &g12a_dos.hw,
2013 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
2014 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
2015 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
2016 [CLKID_ISA] = &g12a_isa.hw,
2017 [CLKID_PL301] = &g12a_pl301.hw,
2018 [CLKID_PERIPHS] = &g12a_periphs.hw,
2019 [CLKID_SPICC0] = &g12a_spicc_0.hw,
2020 [CLKID_I2C] = &g12a_i2c.hw,
2021 [CLKID_SANA] = &g12a_sana.hw,
2022 [CLKID_SD] = &g12a_sd.hw,
2023 [CLKID_RNG0] = &g12a_rng0.hw,
2024 [CLKID_UART0] = &g12a_uart0.hw,
2025 [CLKID_SPICC1] = &g12a_spicc_1.hw,
2026 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
2027 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
2028 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
2029 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
2030 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
2031 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
2032 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
2033 [CLKID_AUDIO] = &g12a_audio.hw,
2034 [CLKID_ETH] = &g12a_eth_core.hw,
2035 [CLKID_DEMUX] = &g12a_demux.hw,
2036 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
2037 [CLKID_ADC] = &g12a_adc.hw,
2038 [CLKID_UART1] = &g12a_uart1.hw,
2039 [CLKID_G2D] = &g12a_g2d.hw,
2040 [CLKID_RESET] = &g12a_reset.hw,
2041 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
2042 [CLKID_PARSER] = &g12a_parser.hw,
2043 [CLKID_USB] = &g12a_usb_general.hw,
2044 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
2045 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
2046 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
2047 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
2048 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
2049 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
2050 [CLKID_BT656] = &g12a_bt656.hw,
2051 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
2052 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
2053 [CLKID_UART2] = &g12a_uart2.hw,
2054 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
2055 [CLKID_GIC] = &g12a_gic.hw,
2056 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
2057 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
2058 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
2059 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
2060 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
2061 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
2062 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
2063 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
2064 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
2065 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
2066 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
2067 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
2068 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
2069 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
2070 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
2071 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
2072 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
2073 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
2074 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
2075 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
2076 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
2077 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
2078 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
2079 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
2080 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
2081 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
2082 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
2083 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
2084 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
2085 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
2086 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
2087 [CLKID_IEC958] = &g12a_iec958_gate.hw,
2088 [CLKID_ENC480P] = &g12a_enc480p.hw,
2089 [CLKID_RNG1] = &g12a_rng1.hw,
2090 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
2091 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
2092 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
2093 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
2094 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
2095 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
2096 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
2097 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
2098 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
2099 [CLKID_DMA] = &g12a_dma.hw,
2100 [CLKID_EFUSE] = &g12a_efuse.hw,
2101 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
2102 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
2103 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
2104 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
2105 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
2106 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
2107 [CLKID_VPU_0] = &g12a_vpu_0.hw,
2108 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
2109 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
2110 [CLKID_VPU_1] = &g12a_vpu_1.hw,
2111 [CLKID_VPU] = &g12a_vpu.hw,
2112 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
2113 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
2114 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
2115 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
2116 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
2117 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
2118 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
2119 [CLKID_VAPB] = &g12a_vapb.hw,
2120 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
2121 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
2122 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
2123 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
2124 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
2125 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
2126 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
2127 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
2128 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
2129 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
2130 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
2131 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
2132 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
2133 [CLKID_VCLK] = &g12a_vclk.hw,
2134 [CLKID_VCLK2] = &g12a_vclk2.hw,
2135 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
2136 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
2137 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
2138 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
2139 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
2140 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
2141 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
2142 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
2143 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
2144 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
2145 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
2146 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
2147 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
2148 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
2149 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
2150 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
2151 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
2152 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
2153 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
2154 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
2155 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
2156 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
2157 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
2158 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
2159 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
2160 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
2161 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
2162 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
2163 [CLKID_HDMI] = &g12a_hdmi.hw,
2164 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
2165 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
2166 [CLKID_MALI_0] = &g12a_mali_0.hw,
2167 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
2168 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
2169 [CLKID_MALI_1] = &g12a_mali_1.hw,
2170 [CLKID_MALI] = &g12a_mali.hw,
2171 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
2172 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
2173 [NR_CLKS] = NULL,
2174 },
2175 .num = NR_CLKS,
2176};
2177
2178/* Convenience table to populate regmap in .probe */
2179static struct clk_regmap *const g12a_clk_regmaps[] = {
2180 &g12a_clk81,
2181 &g12a_dos,
2182 &g12a_ddr,
2183 &g12a_audio_locker,
2184 &g12a_mipi_dsi_host,
2185 &g12a_eth_phy,
2186 &g12a_isa,
2187 &g12a_pl301,
2188 &g12a_periphs,
2189 &g12a_spicc_0,
2190 &g12a_i2c,
2191 &g12a_sana,
2192 &g12a_sd,
2193 &g12a_rng0,
2194 &g12a_uart0,
2195 &g12a_spicc_1,
2196 &g12a_hiu_reg,
2197 &g12a_mipi_dsi_phy,
2198 &g12a_assist_misc,
2199 &g12a_emmc_a,
2200 &g12a_emmc_b,
2201 &g12a_emmc_c,
2202 &g12a_audio_codec,
2203 &g12a_audio,
2204 &g12a_eth_core,
2205 &g12a_demux,
2206 &g12a_audio_ififo,
2207 &g12a_adc,
2208 &g12a_uart1,
2209 &g12a_g2d,
2210 &g12a_reset,
2211 &g12a_pcie_comb,
2212 &g12a_parser,
2213 &g12a_usb_general,
2214 &g12a_pcie_phy,
2215 &g12a_ahb_arb0,
2216 &g12a_ahb_data_bus,
2217 &g12a_ahb_ctrl_bus,
2218 &g12a_htx_hdcp22,
2219 &g12a_htx_pclk,
2220 &g12a_bt656,
2221 &g12a_usb1_to_ddr,
2222 &g12a_mmc_pclk,
2223 &g12a_vpu_intr,
2224 &g12a_gic,
2225 &g12a_sd_emmc_a_clk0,
2226 &g12a_sd_emmc_b_clk0,
2227 &g12a_sd_emmc_c_clk0,
2228 &g12a_mpeg_clk_div,
2229 &g12a_sd_emmc_a_clk0_div,
2230 &g12a_sd_emmc_b_clk0_div,
2231 &g12a_sd_emmc_c_clk0_div,
2232 &g12a_mpeg_clk_sel,
2233 &g12a_sd_emmc_a_clk0_sel,
2234 &g12a_sd_emmc_b_clk0_sel,
2235 &g12a_sd_emmc_c_clk0_sel,
2236 &g12a_mpll0,
2237 &g12a_mpll1,
2238 &g12a_mpll2,
2239 &g12a_mpll3,
2240 &g12a_mpll0_div,
2241 &g12a_mpll1_div,
2242 &g12a_mpll2_div,
2243 &g12a_mpll3_div,
2244 &g12a_fixed_pll,
2245 &g12a_sys_pll,
2246 &g12a_gp0_pll,
2247 &g12a_hifi_pll,
2248 &g12a_vclk2_venci0,
2249 &g12a_vclk2_venci1,
2250 &g12a_vclk2_vencp0,
2251 &g12a_vclk2_vencp1,
2252 &g12a_vclk2_venct0,
2253 &g12a_vclk2_venct1,
2254 &g12a_vclk2_other,
2255 &g12a_vclk2_enci,
2256 &g12a_vclk2_encp,
2257 &g12a_dac_clk,
2258 &g12a_aoclk_gate,
2259 &g12a_iec958_gate,
2260 &g12a_enc480p,
2261 &g12a_rng1,
2262 &g12a_vclk2_enct,
2263 &g12a_vclk2_encl,
2264 &g12a_vclk2_venclmmc,
2265 &g12a_vclk2_vencl,
2266 &g12a_vclk2_other1,
2267 &g12a_fixed_pll_dco,
2268 &g12a_sys_pll_dco,
2269 &g12a_gp0_pll_dco,
2270 &g12a_hifi_pll_dco,
2271 &g12a_fclk_div2,
2272 &g12a_fclk_div3,
2273 &g12a_fclk_div4,
2274 &g12a_fclk_div5,
2275 &g12a_fclk_div7,
2276 &g12a_fclk_div2p5,
2277 &g12a_dma,
2278 &g12a_efuse,
2279 &g12a_rom_boot,
2280 &g12a_reset_sec,
2281 &g12a_sec_ahb_apb3,
2282 &g12a_vpu_0_sel,
2283 &g12a_vpu_0_div,
2284 &g12a_vpu_0,
2285 &g12a_vpu_1_sel,
2286 &g12a_vpu_1_div,
2287 &g12a_vpu_1,
2288 &g12a_vpu,
2289 &g12a_vapb_0_sel,
2290 &g12a_vapb_0_div,
2291 &g12a_vapb_0,
2292 &g12a_vapb_1_sel,
2293 &g12a_vapb_1_div,
2294 &g12a_vapb_1,
2295 &g12a_vapb_sel,
2296 &g12a_vapb,
2297 &g12a_hdmi_pll_dco,
2298 &g12a_hdmi_pll_od,
2299 &g12a_hdmi_pll_od2,
2300 &g12a_hdmi_pll,
2301 &g12a_vid_pll_div,
2302 &g12a_vid_pll_sel,
2303 &g12a_vid_pll,
2304 &g12a_vclk_sel,
2305 &g12a_vclk2_sel,
2306 &g12a_vclk_input,
2307 &g12a_vclk2_input,
2308 &g12a_vclk_div,
2309 &g12a_vclk2_div,
2310 &g12a_vclk,
2311 &g12a_vclk2,
2312 &g12a_vclk_div1,
2313 &g12a_vclk_div2_en,
2314 &g12a_vclk_div4_en,
2315 &g12a_vclk_div6_en,
2316 &g12a_vclk_div12_en,
2317 &g12a_vclk2_div1,
2318 &g12a_vclk2_div2_en,
2319 &g12a_vclk2_div4_en,
2320 &g12a_vclk2_div6_en,
2321 &g12a_vclk2_div12_en,
2322 &g12a_cts_enci_sel,
2323 &g12a_cts_encp_sel,
2324 &g12a_cts_vdac_sel,
2325 &g12a_hdmi_tx_sel,
2326 &g12a_cts_enci,
2327 &g12a_cts_encp,
2328 &g12a_cts_vdac,
2329 &g12a_hdmi_tx,
2330 &g12a_hdmi_sel,
2331 &g12a_hdmi_div,
2332 &g12a_hdmi,
2333 &g12a_mali_0_sel,
2334 &g12a_mali_0_div,
2335 &g12a_mali_0,
2336 &g12a_mali_1_sel,
2337 &g12a_mali_1_div,
2338 &g12a_mali_1,
2339 &g12a_mali,
2340 &g12a_mpll_50m,
2341};
2342
2343static const struct of_device_id clkc_match_table[] = {
2344 { .compatible = "amlogic,g12a-clkc" },
2345 {}
2346};
2347
2348static int g12a_clkc_probe(struct platform_device *pdev)
2349{
2350 struct device *dev = &pdev->dev;
2351 struct clk_hw *input;
2352 struct regmap *map;
2353 int ret, i;
2354
2355 /* Get the hhi system controller node */
2356 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2357 if (IS_ERR(map)) {
2358 dev_err(dev,
2359 "failed to get HHI regmap\n");
2360 return PTR_ERR(map);
2361 }
2362
2363 input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
2364 if (IS_ERR(input)) {
2365 ret = PTR_ERR(input);
2366 if (ret != -EPROBE_DEFER)
2367 dev_err(dev, "failed to get input clock");
2368 return ret;
2369 }
2370
2371 /* Populate regmap for the regmap backed clocks */
2372 for (i = 0; i < ARRAY_SIZE(g12a_clk_regmaps); i++)
2373 g12a_clk_regmaps[i]->map = map;
2374
2375 for (i = 0; i < g12a_hw_onecell_data.num; i++) {
2376 /* array might be sparse */
2377 if (!g12a_hw_onecell_data.hws[i])
2378 continue;
2379
2380 ret = devm_clk_hw_register(dev, g12a_hw_onecell_data.hws[i]);
2381 if (ret) {
2382 dev_err(dev, "Clock registration failed\n");
2383 return ret;
2384 }
2385 }
2386
2387 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2388 &g12a_hw_onecell_data);
2389}
2390
2391static struct platform_driver g12a_driver = {
2392 .probe = g12a_clkc_probe,
2393 .driver = {
2394 .name = "g12a-clkc",
2395 .of_match_table = clkc_match_table,
2396 },
2397};
2398
2399builtin_platform_driver(g12a_driver);
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
new file mode 100644
index 000000000000..f399dfe1401c
--- /dev/null
+++ b/drivers/clk/meson/g12a.h
@@ -0,0 +1,175 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2016 Amlogic, Inc.
4 * Author: Michael Turquette <mturquette@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 * Author: Jian Hu <jian.hu@amlogic.com>
9 *
10 */
11#ifndef __G12A_H
12#define __G12A_H
13
14/*
15 * Clock controller register offsets
16 *
17 * Register offsets from the data sheet must be multiplied by 4 before
18 * adding them to the base address to get the right value.
19 */
20#define HHI_MIPI_CNTL0 0x000
21#define HHI_MIPI_CNTL1 0x004
22#define HHI_MIPI_CNTL2 0x008
23#define HHI_MIPI_STS 0x00C
24#define HHI_GP0_PLL_CNTL0 0x040
25#define HHI_GP0_PLL_CNTL1 0x044
26#define HHI_GP0_PLL_CNTL2 0x048
27#define HHI_GP0_PLL_CNTL3 0x04C
28#define HHI_GP0_PLL_CNTL4 0x050
29#define HHI_GP0_PLL_CNTL5 0x054
30#define HHI_GP0_PLL_CNTL6 0x058
31#define HHI_GP0_PLL_STS 0x05C
32#define HHI_PCIE_PLL_CNTL0 0x098
33#define HHI_PCIE_PLL_CNTL1 0x09C
34#define HHI_PCIE_PLL_CNTL2 0x0A0
35#define HHI_PCIE_PLL_CNTL3 0x0A4
36#define HHI_PCIE_PLL_CNTL4 0x0A8
37#define HHI_PCIE_PLL_CNTL5 0x0AC
38#define HHI_PCIE_PLL_STS 0x0B8
39#define HHI_HIFI_PLL_CNTL0 0x0D8
40#define HHI_HIFI_PLL_CNTL1 0x0DC
41#define HHI_HIFI_PLL_CNTL2 0x0E0
42#define HHI_HIFI_PLL_CNTL3 0x0E4
43#define HHI_HIFI_PLL_CNTL4 0x0E8
44#define HHI_HIFI_PLL_CNTL5 0x0EC
45#define HHI_HIFI_PLL_CNTL6 0x0F0
46#define HHI_VIID_CLK_DIV 0x128
47#define HHI_VIID_CLK_CNTL 0x12C
48#define HHI_GCLK_MPEG0 0x140
49#define HHI_GCLK_MPEG1 0x144
50#define HHI_GCLK_MPEG2 0x148
51#define HHI_GCLK_OTHER 0x150
52#define HHI_GCLK_OTHER2 0x154
53#define HHI_VID_CLK_DIV 0x164
54#define HHI_MPEG_CLK_CNTL 0x174
55#define HHI_AUD_CLK_CNTL 0x178
56#define HHI_VID_CLK_CNTL 0x17c
57#define HHI_TS_CLK_CNTL 0x190
58#define HHI_VID_CLK_CNTL2 0x194
59#define HHI_SYS_CPU_CLK_CNTL0 0x19c
60#define HHI_VID_PLL_CLK_DIV 0x1A0
61#define HHI_MALI_CLK_CNTL 0x1b0
62#define HHI_VPU_CLKC_CNTL 0x1b4
63#define HHI_VPU_CLK_CNTL 0x1bC
64#define HHI_HDMI_CLK_CNTL 0x1CC
65#define HHI_VDEC_CLK_CNTL 0x1E0
66#define HHI_VDEC2_CLK_CNTL 0x1E4
67#define HHI_VDEC3_CLK_CNTL 0x1E8
68#define HHI_VDEC4_CLK_CNTL 0x1EC
69#define HHI_HDCP22_CLK_CNTL 0x1F0
70#define HHI_VAPBCLK_CNTL 0x1F4
71#define HHI_VPU_CLKB_CNTL 0x20C
72#define HHI_GEN_CLK_CNTL 0x228
73#define HHI_VDIN_MEAS_CLK_CNTL 0x250
74#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
75#define HHI_NAND_CLK_CNTL 0x25C
76#define HHI_SD_EMMC_CLK_CNTL 0x264
77#define HHI_MPLL_CNTL0 0x278
78#define HHI_MPLL_CNTL1 0x27C
79#define HHI_MPLL_CNTL2 0x280
80#define HHI_MPLL_CNTL3 0x284
81#define HHI_MPLL_CNTL4 0x288
82#define HHI_MPLL_CNTL5 0x28c
83#define HHI_MPLL_CNTL6 0x290
84#define HHI_MPLL_CNTL7 0x294
85#define HHI_MPLL_CNTL8 0x298
86#define HHI_FIX_PLL_CNTL0 0x2A0
87#define HHI_FIX_PLL_CNTL1 0x2A4
88#define HHI_FIX_PLL_CNTL3 0x2AC
89#define HHI_SYS_PLL_CNTL0 0x2f4
90#define HHI_SYS_PLL_CNTL1 0x2f8
91#define HHI_SYS_PLL_CNTL2 0x2fc
92#define HHI_SYS_PLL_CNTL3 0x300
93#define HHI_SYS_PLL_CNTL4 0x304
94#define HHI_SYS_PLL_CNTL5 0x308
95#define HHI_SYS_PLL_CNTL6 0x30c
96#define HHI_HDMI_PLL_CNTL0 0x320
97#define HHI_HDMI_PLL_CNTL1 0x324
98#define HHI_HDMI_PLL_CNTL2 0x328
99#define HHI_HDMI_PLL_CNTL3 0x32c
100#define HHI_HDMI_PLL_CNTL4 0x330
101#define HHI_HDMI_PLL_CNTL5 0x334
102#define HHI_HDMI_PLL_CNTL6 0x338
103#define HHI_SPICC_CLK_CNTL 0x3dc
104
105/*
106 * CLKID index values
107 *
108 * These indices are entirely contrived and do not map onto the hardware.
109 * It has now been decided to expose everything by default in the DT header:
110 * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
111 * to expose, such as the internal muxes and dividers of composite clocks,
112 * will remain defined here.
113 */
114#define CLKID_MPEG_SEL 8
115#define CLKID_MPEG_DIV 9
116#define CLKID_SD_EMMC_A_CLK0_SEL 63
117#define CLKID_SD_EMMC_A_CLK0_DIV 64
118#define CLKID_SD_EMMC_B_CLK0_SEL 65
119#define CLKID_SD_EMMC_B_CLK0_DIV 66
120#define CLKID_SD_EMMC_C_CLK0_SEL 67
121#define CLKID_SD_EMMC_C_CLK0_DIV 68
122#define CLKID_MPLL0_DIV 69
123#define CLKID_MPLL1_DIV 70
124#define CLKID_MPLL2_DIV 71
125#define CLKID_MPLL3_DIV 72
126#define CLKID_MPLL_PREDIV 73
127#define CLKID_FCLK_DIV2_DIV 75
128#define CLKID_FCLK_DIV3_DIV 76
129#define CLKID_FCLK_DIV4_DIV 77
130#define CLKID_FCLK_DIV5_DIV 78
131#define CLKID_FCLK_DIV7_DIV 79
132#define CLKID_FCLK_DIV2P5_DIV 100
133#define CLKID_FIXED_PLL_DCO 101
134#define CLKID_SYS_PLL_DCO 102
135#define CLKID_GP0_PLL_DCO 103
136#define CLKID_HIFI_PLL_DCO 104
137#define CLKID_VPU_0_DIV 111
138#define CLKID_VPU_1_DIV 114
139#define CLKID_VAPB_0_DIV 118
140#define CLKID_VAPB_1_DIV 121
141#define CLKID_HDMI_PLL_DCO 125
142#define CLKID_HDMI_PLL_OD 126
143#define CLKID_HDMI_PLL_OD2 127
144#define CLKID_VID_PLL_SEL 130
145#define CLKID_VID_PLL_DIV 131
146#define CLKID_VCLK_SEL 132
147#define CLKID_VCLK2_SEL 133
148#define CLKID_VCLK_INPUT 134
149#define CLKID_VCLK2_INPUT 135
150#define CLKID_VCLK_DIV 136
151#define CLKID_VCLK2_DIV 137
152#define CLKID_VCLK_DIV2_EN 140
153#define CLKID_VCLK_DIV4_EN 141
154#define CLKID_VCLK_DIV6_EN 142
155#define CLKID_VCLK_DIV12_EN 143
156#define CLKID_VCLK2_DIV2_EN 144
157#define CLKID_VCLK2_DIV4_EN 145
158#define CLKID_VCLK2_DIV6_EN 146
159#define CLKID_VCLK2_DIV12_EN 147
160#define CLKID_CTS_ENCI_SEL 158
161#define CLKID_CTS_ENCP_SEL 159
162#define CLKID_CTS_VDAC_SEL 160
163#define CLKID_HDMI_TX_SEL 161
164#define CLKID_HDMI_SEL 166
165#define CLKID_HDMI_DIV 167
166#define CLKID_MALI_0_DIV 170
167#define CLKID_MALI_1_DIV 173
168#define CLKID_MPLL_5OM_DIV 176
169
170#define NR_CLKS 178
171
172/* include the CLKIDs that have been made part of the DT binding */
173#include <dt-bindings/clock/g12a-clkc.h>
174
175#endif /* __G12A_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 18:54:01 -0500