diff options
| -rw-r--r-- | drivers/irqchip/spear-shirq.c | 52 | ||||
| -rw-r--r-- | include/linux/irqchip/spear-shirq.h | 64 |
2 files changed, 45 insertions, 71 deletions
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c index 93f2196e8a08..441e39f08135 100644 --- a/drivers/irqchip/spear-shirq.c +++ b/drivers/irqchip/spear-shirq.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
| 21 | #include <linux/irqdomain.h> | 21 | #include <linux/irqdomain.h> |
| 22 | #include <linux/irqchip/spear-shirq.h> | ||
| 23 | #include <linux/of.h> | 22 | #include <linux/of.h> |
| 24 | #include <linux/of_address.h> | 23 | #include <linux/of_address.h> |
| 25 | #include <linux/of_irq.h> | 24 | #include <linux/of_irq.h> |
| @@ -27,6 +26,45 @@ | |||
| 27 | 26 | ||
| 28 | #include "irqchip.h" | 27 | #include "irqchip.h" |
| 29 | 28 | ||
| 29 | /* | ||
| 30 | * struct shirq_regs: shared irq register configuration | ||
| 31 | * | ||
| 32 | * enb_reg: enable register offset | ||
| 33 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt | ||
| 34 | * status_reg: status register offset | ||
| 35 | * status_reg_mask: status register valid mask | ||
| 36 | * clear_reg: clear register offset | ||
| 37 | * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt | ||
| 38 | */ | ||
| 39 | struct shirq_regs { | ||
| 40 | u32 enb_reg; | ||
| 41 | u32 reset_to_enb; | ||
| 42 | u32 status_reg; | ||
| 43 | u32 clear_reg; | ||
| 44 | u32 reset_to_clear; | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* | ||
| 48 | * struct spear_shirq: shared irq structure | ||
| 49 | * | ||
| 50 | * irq: hardware irq number | ||
| 51 | * irq_base: base irq in linux domain | ||
| 52 | * irq_nr: no. of shared interrupts in a particular block | ||
| 53 | * irq_bit_off: starting bit offset in the status register | ||
| 54 | * invalid_irq: irq group is currently disabled | ||
| 55 | * base: base address of shared irq register | ||
| 56 | * regs: register configuration for shared irq block | ||
| 57 | */ | ||
| 58 | struct spear_shirq { | ||
| 59 | u32 irq; | ||
| 60 | u32 irq_base; | ||
| 61 | u32 irq_nr; | ||
| 62 | u32 irq_bit_off; | ||
| 63 | int invalid_irq; | ||
| 64 | void __iomem *base; | ||
| 65 | struct shirq_regs regs; | ||
| 66 | }; | ||
| 67 | |||
| 30 | static DEFINE_SPINLOCK(lock); | 68 | static DEFINE_SPINLOCK(lock); |
| 31 | 69 | ||
| 32 | /* spear300 shared irq registers offsets and masks */ | 70 | /* spear300 shared irq registers offsets and masks */ |
| @@ -296,24 +334,24 @@ err_unmap: | |||
| 296 | return -ENXIO; | 334 | return -ENXIO; |
| 297 | } | 335 | } |
| 298 | 336 | ||
| 299 | int __init spear300_shirq_of_init(struct device_node *np, | 337 | static int __init spear300_shirq_of_init(struct device_node *np, |
| 300 | struct device_node *parent) | 338 | struct device_node *parent) |
| 301 | { | 339 | { |
| 302 | return shirq_init(spear300_shirq_blocks, | 340 | return shirq_init(spear300_shirq_blocks, |
| 303 | ARRAY_SIZE(spear300_shirq_blocks), np); | 341 | ARRAY_SIZE(spear300_shirq_blocks), np); |
| 304 | } | 342 | } |
| 305 | IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); | 343 | IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); |
| 306 | 344 | ||
| 307 | int __init spear310_shirq_of_init(struct device_node *np, | 345 | static int __init spear310_shirq_of_init(struct device_node *np, |
| 308 | struct device_node *parent) | 346 | struct device_node *parent) |
| 309 | { | 347 | { |
| 310 | return shirq_init(spear310_shirq_blocks, | 348 | return shirq_init(spear310_shirq_blocks, |
| 311 | ARRAY_SIZE(spear310_shirq_blocks), np); | 349 | ARRAY_SIZE(spear310_shirq_blocks), np); |
| 312 | } | 350 | } |
| 313 | IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); | 351 | IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); |
| 314 | 352 | ||
| 315 | int __init spear320_shirq_of_init(struct device_node *np, | 353 | static int __init spear320_shirq_of_init(struct device_node *np, |
| 316 | struct device_node *parent) | 354 | struct device_node *parent) |
| 317 | { | 355 | { |
| 318 | return shirq_init(spear320_shirq_blocks, | 356 | return shirq_init(spear320_shirq_blocks, |
| 319 | ARRAY_SIZE(spear320_shirq_blocks), np); | 357 | ARRAY_SIZE(spear320_shirq_blocks), np); |
diff --git a/include/linux/irqchip/spear-shirq.h b/include/linux/irqchip/spear-shirq.h deleted file mode 100644 index c8be16d213a3..000000000000 --- a/include/linux/irqchip/spear-shirq.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * SPEAr platform shared irq layer header file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2012 ST Microelectronics | ||
| 5 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __SPEAR_SHIRQ_H | ||
| 13 | #define __SPEAR_SHIRQ_H | ||
| 14 | |||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * struct shirq_regs: shared irq register configuration | ||
| 20 | * | ||
| 21 | * enb_reg: enable register offset | ||
| 22 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt | ||
| 23 | * status_reg: status register offset | ||
| 24 | * status_reg_mask: status register valid mask | ||
| 25 | * clear_reg: clear register offset | ||
| 26 | * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt | ||
| 27 | */ | ||
| 28 | struct shirq_regs { | ||
| 29 | u32 enb_reg; | ||
| 30 | u32 reset_to_enb; | ||
| 31 | u32 status_reg; | ||
| 32 | u32 clear_reg; | ||
| 33 | u32 reset_to_clear; | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* | ||
| 37 | * struct spear_shirq: shared irq structure | ||
| 38 | * | ||
| 39 | * irq: hardware irq number | ||
| 40 | * irq_base: base irq in linux domain | ||
| 41 | * irq_nr: no. of shared interrupts in a particular block | ||
| 42 | * irq_bit_off: starting bit offset in the status register | ||
| 43 | * invalid_irq: irq group is currently disabled | ||
| 44 | * base: base address of shared irq register | ||
| 45 | * regs: register configuration for shared irq block | ||
| 46 | */ | ||
| 47 | struct spear_shirq { | ||
| 48 | u32 irq; | ||
| 49 | u32 irq_base; | ||
| 50 | u32 irq_nr; | ||
| 51 | u32 irq_bit_off; | ||
| 52 | int invalid_irq; | ||
| 53 | void __iomem *base; | ||
| 54 | struct shirq_regs regs; | ||
| 55 | }; | ||
| 56 | |||
| 57 | int __init spear300_shirq_of_init(struct device_node *np, | ||
| 58 | struct device_node *parent); | ||
| 59 | int __init spear310_shirq_of_init(struct device_node *np, | ||
| 60 | struct device_node *parent); | ||
| 61 | int __init spear320_shirq_of_init(struct device_node *np, | ||
| 62 | struct device_node *parent); | ||
| 63 | |||
| 64 | #endif /* __SPEAR_SHIRQ_H */ | ||
