diff options
-rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 999955c2b23e..891b353e8105 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c | |||
@@ -70,6 +70,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { | |||
70 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), | 70 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), |
71 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), | 71 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), |
72 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), | 72 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), |
73 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), | ||
73 | 74 | ||
74 | /* Core Clock Outputs */ | 75 | /* Core Clock Outputs */ |
75 | DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), | 76 | DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
@@ -93,6 +94,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { | |||
93 | DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), | 94 | DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), |
94 | DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), | 95 | DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), |
95 | 96 | ||
97 | DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x0074), | ||
98 | DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x0078), | ||
99 | DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x0268), | ||
100 | DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x026c), | ||
101 | |||
96 | DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), | 102 | DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
97 | DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), | 103 | DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
98 | 104 | ||
@@ -104,6 +110,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { | |||
104 | 110 | ||
105 | static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { | 111 | static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { |
106 | DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), | 112 | DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), |
113 | DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), | ||
114 | DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), | ||
115 | DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), | ||
116 | DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), | ||
107 | DEF_MOD("rwdt0", 402, R8A7796_CLK_R), | 117 | DEF_MOD("rwdt0", 402, R8A7796_CLK_R), |
108 | DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), | 118 | DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), |
109 | DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), | 119 | DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), |