diff options
| -rw-r--r-- | arch/sparc/include/asm/cmt.h | 59 | ||||
| -rw-r--r-- | arch/sparc/include/asm/mpmbox.h | 67 |
2 files changed, 0 insertions, 126 deletions
diff --git a/arch/sparc/include/asm/cmt.h b/arch/sparc/include/asm/cmt.h deleted file mode 100644 index 870db5928577..000000000000 --- a/arch/sparc/include/asm/cmt.h +++ /dev/null | |||
| @@ -1,59 +0,0 @@ | |||
| 1 | #ifndef _SPARC64_CMT_H | ||
| 2 | #define _SPARC64_CMT_H | ||
| 3 | |||
| 4 | /* cmt.h: Chip Multi-Threading register definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 David S. Miller (davem@redhat.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* ASI_CORE_ID - private */ | ||
| 10 | #define LP_ID 0x0000000000000010UL | ||
| 11 | #define LP_ID_MAX 0x00000000003f0000UL | ||
| 12 | #define LP_ID_ID 0x000000000000003fUL | ||
| 13 | |||
| 14 | /* ASI_INTR_ID - private */ | ||
| 15 | #define LP_INTR_ID 0x0000000000000000UL | ||
| 16 | #define LP_INTR_ID_ID 0x00000000000003ffUL | ||
| 17 | |||
| 18 | /* ASI_CESR_ID - private */ | ||
| 19 | #define CESR_ID 0x0000000000000040UL | ||
| 20 | #define CESR_ID_ID 0x00000000000000ffUL | ||
| 21 | |||
| 22 | /* ASI_CORE_AVAILABLE - shared */ | ||
| 23 | #define LP_AVAIL 0x0000000000000000UL | ||
| 24 | #define LP_AVAIL_1 0x0000000000000002UL | ||
| 25 | #define LP_AVAIL_0 0x0000000000000001UL | ||
| 26 | |||
| 27 | /* ASI_CORE_ENABLE_STATUS - shared */ | ||
| 28 | #define LP_ENAB_STAT 0x0000000000000010UL | ||
| 29 | #define LP_ENAB_STAT_1 0x0000000000000002UL | ||
| 30 | #define LP_ENAB_STAT_0 0x0000000000000001UL | ||
| 31 | |||
| 32 | /* ASI_CORE_ENABLE - shared */ | ||
| 33 | #define LP_ENAB 0x0000000000000020UL | ||
| 34 | #define LP_ENAB_1 0x0000000000000002UL | ||
| 35 | #define LP_ENAB_0 0x0000000000000001UL | ||
| 36 | |||
| 37 | /* ASI_CORE_RUNNING - shared */ | ||
| 38 | #define LP_RUNNING_RW 0x0000000000000050UL | ||
| 39 | #define LP_RUNNING_W1S 0x0000000000000060UL | ||
| 40 | #define LP_RUNNING_W1C 0x0000000000000068UL | ||
| 41 | #define LP_RUNNING_1 0x0000000000000002UL | ||
| 42 | #define LP_RUNNING_0 0x0000000000000001UL | ||
| 43 | |||
| 44 | /* ASI_CORE_RUNNING_STAT - shared */ | ||
| 45 | #define LP_RUN_STAT 0x0000000000000058UL | ||
| 46 | #define LP_RUN_STAT_1 0x0000000000000002UL | ||
| 47 | #define LP_RUN_STAT_0 0x0000000000000001UL | ||
| 48 | |||
| 49 | /* ASI_XIR_STEERING - shared */ | ||
| 50 | #define LP_XIR_STEER 0x0000000000000030UL | ||
| 51 | #define LP_XIR_STEER_1 0x0000000000000002UL | ||
| 52 | #define LP_XIR_STEER_0 0x0000000000000001UL | ||
| 53 | |||
| 54 | /* ASI_CMT_ERROR_STEERING - shared */ | ||
| 55 | #define CMT_ER_STEER 0x0000000000000040UL | ||
| 56 | #define CMT_ER_STEER_1 0x0000000000000002UL | ||
| 57 | #define CMT_ER_STEER_0 0x0000000000000001UL | ||
| 58 | |||
| 59 | #endif /* _SPARC64_CMT_H */ | ||
diff --git a/arch/sparc/include/asm/mpmbox.h b/arch/sparc/include/asm/mpmbox.h deleted file mode 100644 index f8423039b242..000000000000 --- a/arch/sparc/include/asm/mpmbox.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * mpmbox.h: Interface and defines for the OpenProm mailbox | ||
| 3 | * facilities for MP machines under Linux. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _SPARC_MPMBOX_H | ||
| 9 | #define _SPARC_MPMBOX_H | ||
| 10 | |||
| 11 | /* The prom allocates, for each CPU on the machine an unsigned | ||
| 12 | * byte in physical ram. You probe the device tree prom nodes | ||
| 13 | * for these values. The purpose of this byte is to be able to | ||
| 14 | * pass messages from one cpu to another. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* These are the main message types we have to look for in our | ||
| 18 | * Cpu mailboxes, based upon these values we decide what course | ||
| 19 | * of action to take. | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* The CPU is executing code in the kernel. */ | ||
| 23 | #define MAILBOX_ISRUNNING 0xf0 | ||
| 24 | |||
| 25 | /* Another CPU called romvec->pv_exit(), you should call | ||
| 26 | * prom_stopcpu() when you see this in your mailbox. | ||
| 27 | */ | ||
| 28 | #define MAILBOX_EXIT 0xfb | ||
| 29 | |||
| 30 | /* Another CPU called romvec->pv_enter(), you should call | ||
| 31 | * prom_cpuidle() when this is seen. | ||
| 32 | */ | ||
| 33 | #define MAILBOX_GOSPIN 0xfc | ||
| 34 | |||
| 35 | /* Another CPU has hit a breakpoint either into kadb or the prom | ||
| 36 | * itself. Just like MAILBOX_GOSPIN, you should call prom_cpuidle() | ||
| 37 | * at this point. | ||
| 38 | */ | ||
| 39 | #define MAILBOX_BPT_SPIN 0xfd | ||
| 40 | |||
| 41 | /* Oh geese, some other nitwit got a damn watchdog reset. The party's | ||
| 42 | * over so go call prom_stopcpu(). | ||
| 43 | */ | ||
| 44 | #define MAILBOX_WDOG_STOP 0xfe | ||
| 45 | |||
| 46 | #ifndef __ASSEMBLY__ | ||
| 47 | |||
| 48 | /* Handy macro's to determine a cpu's state. */ | ||
| 49 | |||
| 50 | /* Is the cpu still in Power On Self Test? */ | ||
| 51 | #define MBOX_POST_P(letter) ((letter) >= 0x00 && (letter) <= 0x7f) | ||
| 52 | |||
| 53 | /* Is the cpu at the 'ok' prompt of the PROM? */ | ||
| 54 | #define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f) | ||
| 55 | |||
| 56 | /* Is the cpu spinning in the PROM? */ | ||
| 57 | #define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef) | ||
| 58 | |||
| 59 | /* Sanity check... This is junk mail, throw it out. */ | ||
| 60 | #define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa) | ||
| 61 | |||
| 62 | /* Is the cpu actively running an application/kernel-code? */ | ||
| 63 | #define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING) | ||
| 64 | |||
| 65 | #endif /* !(__ASSEMBLY__) */ | ||
| 66 | |||
| 67 | #endif /* !(_SPARC_MPMBOX_H) */ | ||