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-rw-r--r--drivers/gpu/drm/i915/intel_display.c11
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c7
2 files changed, 11 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 85f3eb74d2b7..c59335ce84f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4913,22 +4913,19 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4913 uint32_t tmp; 4913 uint32_t tmp;
4914 4914
4915 tmp = I915_READ(PFIT_CONTROL); 4915 tmp = I915_READ(PFIT_CONTROL);
4916 if (!(tmp & PFIT_ENABLE))
4917 return;
4916 4918
4919 /* Check whether the pfit is attached to our pipe. */
4917 if (INTEL_INFO(dev)->gen < 4) { 4920 if (INTEL_INFO(dev)->gen < 4) {
4918 if (crtc->pipe != PIPE_B) 4921 if (crtc->pipe != PIPE_B)
4919 return; 4922 return;
4920
4921 /* gen2/3 store dither state in pfit control, needs to match */
4922 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4923 } else { 4923 } else {
4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4925 return; 4925 return;
4926 } 4926 }
4927 4927
4928 if (!(tmp & PFIT_ENABLE)) 4928 pipe_config->gmch_pfit.control = tmp;
4929 return;
4930
4931 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4932 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); 4929 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4933 if (INTEL_INFO(dev)->gen < 5) 4930 if (INTEL_INFO(dev)->gen < 5)
4934 pipe_config->gmch_pfit.lvds_border_bits = 4931 pipe_config->gmch_pfit.lvds_border_bits =
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2abb2d3c727b..12079983c8ab 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -109,6 +109,13 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
109 flags |= DRM_MODE_FLAG_PVSYNC; 109 flags |= DRM_MODE_FLAG_PVSYNC;
110 110
111 pipe_config->adjusted_mode.flags |= flags; 111 pipe_config->adjusted_mode.flags |= flags;
112
113 /* gen2/3 store dither state in pfit control, needs to match */
114 if (INTEL_INFO(dev)->gen < 4) {
115 tmp = I915_READ(PFIT_CONTROL);
116
117 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
118 }
112} 119}
113 120
114/* The LVDS pin pair needs to be on before the DPLLs are enabled. 121/* The LVDS pin pair needs to be on before the DPLLs are enabled.