diff options
| -rw-r--r-- | drivers/gpu/drm/etnaviv/common.xml.h | 281 | ||||
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state.xml.h | 256 | ||||
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state_3d.xml.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state_blt.xml.h | 52 | ||||
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state_hi.xml.h | 150 |
5 files changed, 617 insertions, 127 deletions
diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h index 207f45c999c3..001faea80fef 100644 --- a/drivers/gpu/drm/etnaviv/common.xml.h +++ b/drivers/gpu/drm/etnaviv/common.xml.h | |||
| @@ -8,15 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng | |||
| 8 | git clone git://0x04.net/rules-ng-ng | 8 | git clone git://0x04.net/rules-ng-ng |
| 9 | 9 | ||
| 10 | The rules-ng-ng source files this header was generated from are: | 10 | The rules-ng-ng source files this header was generated from are: |
| 11 | - state.xml ( 19930 bytes, from 2017-03-09 15:43:43) | 11 | - texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59) |
| 12 | - common.xml ( 23473 bytes, from 2017-03-09 15:43:43) | 12 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) |
| 13 | - state_hi.xml ( 26403 bytes, from 2017-03-09 15:43:43) | 13 | - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) |
| 14 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) | 14 | - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) |
| 15 | - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) | ||
| 16 | - state_3d.xml ( 66957 bytes, from 2017-03-09 15:43:43) | ||
| 17 | - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) | ||
| 18 | 15 | ||
| 19 | Copyright (C) 2012-2017 by the following authors: | 16 | Copyright (C) 2012-2018 by the following authors: |
| 20 | - Wladimir J. van der Laan <laanwj@gmail.com> | 17 | - Wladimir J. van der Laan <laanwj@gmail.com> |
| 21 | - Christian Gmeiner <christian.gmeiner@gmail.com> | 18 | - Christian Gmeiner <christian.gmeiner@gmail.com> |
| 22 | - Lucas Stach <l.stach@pengutronix.de> | 19 | - Lucas Stach <l.stach@pengutronix.de> |
| @@ -49,12 +46,7 @@ DEALINGS IN THE SOFTWARE. | |||
| 49 | #define SYNC_RECIPIENT_RA 0x00000005 | 46 | #define SYNC_RECIPIENT_RA 0x00000005 |
| 50 | #define SYNC_RECIPIENT_PE 0x00000007 | 47 | #define SYNC_RECIPIENT_PE 0x00000007 |
| 51 | #define SYNC_RECIPIENT_DE 0x0000000b | 48 | #define SYNC_RECIPIENT_DE 0x0000000b |
| 52 | #define SYNC_RECIPIENT_VG 0x0000000f | 49 | #define SYNC_RECIPIENT_BLT 0x00000010 |
| 53 | #define SYNC_RECIPIENT_TESSELATOR 0x00000010 | ||
| 54 | #define SYNC_RECIPIENT_VG2 0x00000011 | ||
| 55 | #define SYNC_RECIPIENT_TESSELATOR2 0x00000012 | ||
| 56 | #define SYNC_RECIPIENT_VG3 0x00000013 | ||
| 57 | #define SYNC_RECIPIENT_TESSELATOR3 0x00000014 | ||
| 58 | #define ENDIAN_MODE_NO_SWAP 0x00000000 | 50 | #define ENDIAN_MODE_NO_SWAP 0x00000000 |
| 59 | #define ENDIAN_MODE_SWAP_16 0x00000001 | 51 | #define ENDIAN_MODE_SWAP_16 0x00000001 |
| 60 | #define ENDIAN_MODE_SWAP_32 0x00000002 | 52 | #define ENDIAN_MODE_SWAP_32 0x00000002 |
| @@ -77,6 +69,7 @@ DEALINGS IN THE SOFTWARE. | |||
| 77 | #define chipModel_GC800 0x00000800 | 69 | #define chipModel_GC800 0x00000800 |
| 78 | #define chipModel_GC860 0x00000860 | 70 | #define chipModel_GC860 0x00000860 |
| 79 | #define chipModel_GC880 0x00000880 | 71 | #define chipModel_GC880 0x00000880 |
| 72 | #define chipModel_GC900 0x00000900 | ||
| 80 | #define chipModel_GC1000 0x00001000 | 73 | #define chipModel_GC1000 0x00001000 |
| 81 | #define chipModel_GC1500 0x00001500 | 74 | #define chipModel_GC1500 0x00001500 |
| 82 | #define chipModel_GC2000 0x00002000 | 75 | #define chipModel_GC2000 0x00002000 |
| @@ -88,6 +81,12 @@ DEALINGS IN THE SOFTWARE. | |||
| 88 | #define chipModel_GC5000 0x00005000 | 81 | #define chipModel_GC5000 0x00005000 |
| 89 | #define chipModel_GC5200 0x00005200 | 82 | #define chipModel_GC5200 0x00005200 |
| 90 | #define chipModel_GC6400 0x00006400 | 83 | #define chipModel_GC6400 0x00006400 |
| 84 | #define chipModel_GC7000 0x00007000 | ||
| 85 | #define chipModel_GC7400 0x00007400 | ||
| 86 | #define chipModel_GC8000 0x00008000 | ||
| 87 | #define chipModel_GC8100 0x00008100 | ||
| 88 | #define chipModel_GC8200 0x00008200 | ||
| 89 | #define chipModel_GC8400 0x00008400 | ||
| 91 | #define RGBA_BITS_R 0x00000001 | 90 | #define RGBA_BITS_R 0x00000001 |
| 92 | #define RGBA_BITS_G 0x00000002 | 91 | #define RGBA_BITS_G 0x00000002 |
| 93 | #define RGBA_BITS_B 0x00000004 | 92 | #define RGBA_BITS_B 0x00000004 |
| @@ -203,7 +202,7 @@ DEALINGS IN THE SOFTWARE. | |||
| 203 | #define chipMinorFeatures2_RGB888 0x00001000 | 202 | #define chipMinorFeatures2_RGB888 0x00001000 |
| 204 | #define chipMinorFeatures2_TX__YUV_ASSEMBLER 0x00002000 | 203 | #define chipMinorFeatures2_TX__YUV_ASSEMBLER 0x00002000 |
| 205 | #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING 0x00004000 | 204 | #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING 0x00004000 |
| 206 | #define chipMinorFeatures2_EXTRA_TEXTURE_STATE 0x00008000 | 205 | #define chipMinorFeatures2_TX_FILTER 0x00008000 |
| 207 | #define chipMinorFeatures2_FULL_DIRECTFB 0x00010000 | 206 | #define chipMinorFeatures2_FULL_DIRECTFB 0x00010000 |
| 208 | #define chipMinorFeatures2_2D_TILING 0x00020000 | 207 | #define chipMinorFeatures2_2D_TILING 0x00020000 |
| 209 | #define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000 | 208 | #define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000 |
| @@ -242,36 +241,36 @@ DEALINGS IN THE SOFTWARE. | |||
| 242 | #define chipMinorFeatures3_TX_ENHANCEMENTS1 0x00080000 | 241 | #define chipMinorFeatures3_TX_ENHANCEMENTS1 0x00080000 |
| 243 | #define chipMinorFeatures3_SH_ENHANCEMENTS1 0x00100000 | 242 | #define chipMinorFeatures3_SH_ENHANCEMENTS1 0x00100000 |
| 244 | #define chipMinorFeatures3_SH_ENHANCEMENTS2 0x00200000 | 243 | #define chipMinorFeatures3_SH_ENHANCEMENTS2 0x00200000 |
| 245 | #define chipMinorFeatures3_UNK22 0x00400000 | 244 | #define chipMinorFeatures3_PE_ENHANCEMENTS1 0x00400000 |
| 246 | #define chipMinorFeatures3_2D_FC_SOURCE 0x00800000 | 245 | #define chipMinorFeatures3_2D_FC_SOURCE 0x00800000 |
| 247 | #define chipMinorFeatures3_UNK24 0x01000000 | 246 | #define chipMinorFeatures3_BUG_FIXES_14 0x01000000 |
| 248 | #define chipMinorFeatures3_UNK25 0x02000000 | 247 | #define chipMinorFeatures3_POWER_OPTIMIZATIONS_0 0x02000000 |
| 249 | #define chipMinorFeatures3_NEW_HZ 0x04000000 | 248 | #define chipMinorFeatures3_NEW_HZ 0x04000000 |
| 250 | #define chipMinorFeatures3_UNK27 0x08000000 | 249 | #define chipMinorFeatures3_PE_DITHER_FIX 0x08000000 |
| 251 | #define chipMinorFeatures3_UNK28 0x10000000 | 250 | #define chipMinorFeatures3_DE_ENHANCEMENTS3 0x10000000 |
| 252 | #define chipMinorFeatures3_SH_ENHANCEMENTS3 0x20000000 | 251 | #define chipMinorFeatures3_SH_ENHANCEMENTS3 0x20000000 |
| 253 | #define chipMinorFeatures3_UNK30 0x40000000 | 252 | #define chipMinorFeatures3_SH_ENHANCEMENTS4 0x40000000 |
| 254 | #define chipMinorFeatures3_UNK31 0x80000000 | 253 | #define chipMinorFeatures3_TX_ENHANCEMENTS2 0x80000000 |
| 255 | #define chipMinorFeatures4_UNK0 0x00000001 | 254 | #define chipMinorFeatures4_FE_ENHANCEMENTS1 0x00000001 |
| 256 | #define chipMinorFeatures4_PE_ENHANCEMENTS2 0x00000002 | 255 | #define chipMinorFeatures4_PE_ENHANCEMENTS2 0x00000002 |
| 257 | #define chipMinorFeatures4_FRUSTUM_CLIP_FIX 0x00000004 | 256 | #define chipMinorFeatures4_FRUSTUM_CLIP_FIX 0x00000004 |
| 258 | #define chipMinorFeatures4_UNK3 0x00000008 | 257 | #define chipMinorFeatures4_DE_NO_GAMMA 0x00000008 |
| 259 | #define chipMinorFeatures4_UNK4 0x00000010 | 258 | #define chipMinorFeatures4_PA_ENHANCEMENTS_2 0x00000010 |
| 260 | #define chipMinorFeatures4_2D_GAMMA 0x00000020 | 259 | #define chipMinorFeatures4_2D_GAMMA 0x00000020 |
| 261 | #define chipMinorFeatures4_SINGLE_BUFFER 0x00000040 | 260 | #define chipMinorFeatures4_SINGLE_BUFFER 0x00000040 |
| 262 | #define chipMinorFeatures4_UNK7 0x00000080 | 261 | #define chipMinorFeatures4_HI_ENHANCEMENTS_1 0x00000080 |
| 263 | #define chipMinorFeatures4_UNK8 0x00000100 | 262 | #define chipMinorFeatures4_TX_ENHANCEMENTS_3 0x00000100 |
| 264 | #define chipMinorFeatures4_UNK9 0x00000200 | 263 | #define chipMinorFeatures4_SH_ENHANCEMENTS_5 0x00000200 |
| 265 | #define chipMinorFeatures4_UNK10 0x00000400 | 264 | #define chipMinorFeatures4_FE_ENHANCEMENTS_2 0x00000400 |
| 266 | #define chipMinorFeatures4_TX_LERP_PRECISION_FIX 0x00000800 | 265 | #define chipMinorFeatures4_TX_LERP_PRECISION_FIX 0x00000800 |
| 267 | #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION 0x00001000 | 266 | #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION 0x00001000 |
| 268 | #define chipMinorFeatures4_TEXTURE_ASTC 0x00002000 | 267 | #define chipMinorFeatures4_TEXTURE_ASTC 0x00002000 |
| 269 | #define chipMinorFeatures4_UNK14 0x00004000 | 268 | #define chipMinorFeatures4_PE_ENHANCEMENTS_4 0x00004000 |
| 270 | #define chipMinorFeatures4_UNK15 0x00008000 | 269 | #define chipMinorFeatures4_MC_ENHANCEMENTS_1 0x00008000 |
| 271 | #define chipMinorFeatures4_HALTI2 0x00010000 | 270 | #define chipMinorFeatures4_HALTI2 0x00010000 |
| 272 | #define chipMinorFeatures4_UNK17 0x00020000 | 271 | #define chipMinorFeatures4_2D_MIRROR_EXTENSION 0x00020000 |
| 273 | #define chipMinorFeatures4_SMALL_MSAA 0x00040000 | 272 | #define chipMinorFeatures4_SMALL_MSAA 0x00040000 |
| 274 | #define chipMinorFeatures4_UNK19 0x00080000 | 273 | #define chipMinorFeatures4_BUG_FIXES_17 0x00080000 |
| 275 | #define chipMinorFeatures4_NEW_RA 0x00100000 | 274 | #define chipMinorFeatures4_NEW_RA 0x00100000 |
| 276 | #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT 0x00200000 | 275 | #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT 0x00200000 |
| 277 | #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2 0x00400000 | 276 | #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2 0x00400000 |
| @@ -280,41 +279,207 @@ DEALINGS IN THE SOFTWARE. | |||
| 280 | #define chipMinorFeatures4_BUG_FIXES18 0x02000000 | 279 | #define chipMinorFeatures4_BUG_FIXES18 0x02000000 |
| 281 | #define chipMinorFeatures4_2D_COMPRESSION 0x04000000 | 280 | #define chipMinorFeatures4_2D_COMPRESSION 0x04000000 |
| 282 | #define chipMinorFeatures4_PROBE 0x08000000 | 281 | #define chipMinorFeatures4_PROBE 0x08000000 |
| 283 | #define chipMinorFeatures4_UNK28 0x10000000 | 282 | #define chipMinorFeatures4_MEDIUM_PRECISION 0x10000000 |
| 284 | #define chipMinorFeatures4_2D_SUPER_TILE_VERSION 0x20000000 | 283 | #define chipMinorFeatures4_2D_SUPER_TILE_VERSION 0x20000000 |
| 285 | #define chipMinorFeatures4_UNK30 0x40000000 | 284 | #define chipMinorFeatures4_BUG_FIXES19 0x40000000 |
| 286 | #define chipMinorFeatures4_UNK31 0x80000000 | 285 | #define chipMinorFeatures4_SH_ENHANCEMENTS6 0x80000000 |
| 287 | #define chipMinorFeatures5_UNK0 0x00000001 | 286 | #define chipMinorFeatures5_SH_ENHANCEMENTS7 0x00000001 |
| 288 | #define chipMinorFeatures5_UNK1 0x00000002 | 287 | #define chipMinorFeatures5_BUG_FIXES20 0x00000002 |
| 289 | #define chipMinorFeatures5_UNK2 0x00000004 | 288 | #define chipMinorFeatures5_DE_ADDRESS_40 0x00000004 |
| 290 | #define chipMinorFeatures5_UNK3 0x00000008 | 289 | #define chipMinorFeatures5_MINI_MMU_FIX 0x00000008 |
| 291 | #define chipMinorFeatures5_EEZ 0x00000010 | 290 | #define chipMinorFeatures5_EEZ 0x00000010 |
| 292 | #define chipMinorFeatures5_UNK5 0x00000020 | 291 | #define chipMinorFeatures5_BUG_FIXES21 0x00000020 |
| 293 | #define chipMinorFeatures5_UNK6 0x00000040 | 292 | #define chipMinorFeatures5_EXTRA_VG_CAPS 0x00000040 |
| 294 | #define chipMinorFeatures5_UNK7 0x00000080 | 293 | #define chipMinorFeatures5_MULTI_SRC_V15 0x00000080 |
| 295 | #define chipMinorFeatures5_UNK8 0x00000100 | 294 | #define chipMinorFeatures5_BUG_FIXES22 0x00000100 |
| 296 | #define chipMinorFeatures5_HALTI3 0x00000200 | 295 | #define chipMinorFeatures5_HALTI3 0x00000200 |
| 297 | #define chipMinorFeatures5_UNK10 0x00000400 | 296 | #define chipMinorFeatures5_TESSELATION_SHADERS 0x00000400 |
| 298 | #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP 0x00000800 | 297 | #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP 0x00000800 |
| 299 | #define chipMinorFeatures5_UNK12 0x00001000 | 298 | #define chipMinorFeatures5_MULTI_SRC_V2_STR_QUAD 0x00001000 |
| 300 | #define chipMinorFeatures5_SEPARATE_SRC_DST 0x00002000 | 299 | #define chipMinorFeatures5_SEPARATE_SRC_DST 0x00002000 |
| 301 | #define chipMinorFeatures5_HALTI4 0x00004000 | 300 | #define chipMinorFeatures5_HALTI4 0x00004000 |
| 302 | #define chipMinorFeatures5_UNK15 0x00008000 | 301 | #define chipMinorFeatures5_RA_WRITE_DEPTH 0x00008000 |
| 303 | #define chipMinorFeatures5_ANDROID_ONLY 0x00010000 | 302 | #define chipMinorFeatures5_ANDROID_ONLY 0x00010000 |
| 304 | #define chipMinorFeatures5_HAS_PRODUCTID 0x00020000 | 303 | #define chipMinorFeatures5_HAS_PRODUCTID 0x00020000 |
| 305 | #define chipMinorFeatures5_UNK18 0x00040000 | 304 | #define chipMinorFeatures5_TX_SUPPORT_DEC 0x00040000 |
| 306 | #define chipMinorFeatures5_UNK19 0x00080000 | 305 | #define chipMinorFeatures5_S8_MSAA_COMPRESSION 0x00080000 |
| 307 | #define chipMinorFeatures5_PE_DITHER_FIX2 0x00100000 | 306 | #define chipMinorFeatures5_PE_DITHER_FIX2 0x00100000 |
| 308 | #define chipMinorFeatures5_UNK21 0x00200000 | 307 | #define chipMinorFeatures5_L2_CACHE_REMOVE 0x00200000 |
| 309 | #define chipMinorFeatures5_UNK22 0x00400000 | 308 | #define chipMinorFeatures5_FE_ALLOW_RND_VTX_CNT 0x00400000 |
| 310 | #define chipMinorFeatures5_UNK23 0x00800000 | 309 | #define chipMinorFeatures5_CUBE_MAP_FL28 0x00800000 |
| 311 | #define chipMinorFeatures5_UNK24 0x01000000 | 310 | #define chipMinorFeatures5_TX_6BIT_FRAC 0x01000000 |
| 312 | #define chipMinorFeatures5_UNK25 0x02000000 | 311 | #define chipMinorFeatures5_FE_ALLOW_STALL_PREFETCH_ENG 0x02000000 |
| 313 | #define chipMinorFeatures5_UNK26 0x04000000 | 312 | #define chipMinorFeatures5_THIRD_PARTY_COMPRESSION 0x04000000 |
| 314 | #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT 0x08000000 | 313 | #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT 0x08000000 |
| 315 | #define chipMinorFeatures5_V2_MSAA_COMP_FIX 0x10000000 | 314 | #define chipMinorFeatures5_V2_MSAA_COMP_FIX 0x10000000 |
| 316 | #define chipMinorFeatures5_UNK29 0x20000000 | 315 | #define chipMinorFeatures5_HALTI5 0x20000000 |
| 317 | #define chipMinorFeatures5_UNK30 0x40000000 | 316 | #define chipMinorFeatures5_EVIS 0x40000000 |
| 318 | #define chipMinorFeatures5_UNK31 0x80000000 | 317 | #define chipMinorFeatures5_BLT_ENGINE 0x80000000 |
| 318 | #define chipMinorFeatures6_BUG_FIXES_23 0x00000001 | ||
| 319 | #define chipMinorFeatures6_BUG_FIXES_24 0x00000002 | ||
| 320 | #define chipMinorFeatures6_DEC 0x00000004 | ||
| 321 | #define chipMinorFeatures6_VS_TILE_NV12 0x00000008 | ||
| 322 | #define chipMinorFeatures6_VS_TILE_NV12_10BIT 0x00000010 | ||
| 323 | #define chipMinorFeatures6_RENDER_TARGET_8 0x00000020 | ||
| 324 | #define chipMinorFeatures6_TEX_LOD_FLOW_CORR 0x00000040 | ||
| 325 | #define chipMinorFeatures6_FACE_LOD 0x00000080 | ||
| 326 | #define chipMinorFeatures6_MULTI_CORE_SEMAPHORE_STALL_V2 0x00000100 | ||
| 327 | #define chipMinorFeatures6_VMSAA 0x00000200 | ||
| 328 | #define chipMinorFeatures6_CHIP_ENABLE_LINK 0x00000400 | ||
| 329 | #define chipMinorFeatures6_MULTI_SRC_BLT_1_5_ENHANCEMENT 0x00000800 | ||
| 330 | #define chipMinorFeatures6_MULTI_SRC_BLT_BILINEAR_FILTER 0x00001000 | ||
| 331 | #define chipMinorFeatures6_RA_HZEZ_CLOCK_CONTROL 0x00002000 | ||
| 332 | #define chipMinorFeatures6_CACHE128B256BPERLINE 0x00004000 | ||
| 333 | #define chipMinorFeatures6_V4_COMPRESSION 0x00008000 | ||
| 334 | #define chipMinorFeatures6_PE2D_MAJOR_SUPER_TILE 0x00010000 | ||
| 335 | #define chipMinorFeatures6_PE_32BPC_COLORMASK_FIX 0x00020000 | ||
| 336 | #define chipMinorFeatures6_ALPHA_BLENDING_OPT 0x00040000 | ||
| 337 | #define chipMinorFeatures6_NEW_GPIPE 0x00080000 | ||
| 338 | #define chipMinorFeatures6_PIPELINE_32_ATTRIBUTES 0x00100000 | ||
| 339 | #define chipMinorFeatures6_MSAA_SHADING 0x00200000 | ||
| 340 | #define chipMinorFeatures6_NO_ANISTRO_FILTER 0x00400000 | ||
| 341 | #define chipMinorFeatures6_NO_ASTC 0x00800000 | ||
| 342 | #define chipMinorFeatures6_NO_DXT 0x01000000 | ||
| 343 | #define chipMinorFeatures6_HWTFB 0x02000000 | ||
| 344 | #define chipMinorFeatures6_RA_DEPTH_WRITE_MSAA1X_FIX 0x04000000 | ||
| 345 | #define chipMinorFeatures6_EZHZ_CLOCKGATE_FIX 0x08000000 | ||
| 346 | #define chipMinorFeatures6_SH_SNAP2PAGE_FIX 0x10000000 | ||
| 347 | #define chipMinorFeatures6_SH_HALFDEPENDENCY_FIX 0x20000000 | ||
| 348 | #define chipMinorFeatures6_USC_MCFILL_FIX 0x40000000 | ||
| 349 | #define chipMinorFeatures6_TPG_TCPERF_FIX 0x80000000 | ||
| 350 | #define chipMinorFeatures7_USC_MDFIFO_OVERFLOW_FIX 0x00000001 | ||
| 351 | #define chipMinorFeatures7_SH_TEXLD_BARRIER_IN_CS_FIX 0x00000002 | ||
| 352 | #define chipMinorFeatures7_RS_NEW_BASEADDR 0x00000004 | ||
| 353 | #define chipMinorFeatures7_PE_8BPP_DUALPIPE_FIX 0x00000008 | ||
| 354 | #define chipMinorFeatures7_SH_ADVANCED_INSTR 0x00000010 | ||
| 355 | #define chipMinorFeatures7_SH_FLAT_INTERPOLATION_DUAL16_FIX 0x00000020 | ||
| 356 | #define chipMinorFeatures7_USC_CONTINUOUS_FLUS_FIX 0x00000040 | ||
| 357 | #define chipMinorFeatures7_SH_SUPPORT_V4 0x00000080 | ||
| 358 | #define chipMinorFeatures7_SH_SUPPORT_ALPHA_KILL 0x00000100 | ||
| 359 | #define chipMinorFeatures7_PE_NO_ALPHA_TEST 0x00000200 | ||
| 360 | #define chipMinorFeatures7_TX_LOD_NEAREST_SELECT 0x00000400 | ||
| 361 | #define chipMinorFeatures7_SH_FIX_LDEXP 0x00000800 | ||
| 362 | #define chipMinorFeatures7_SUPPORT_MOVAI 0x00001000 | ||
| 363 | #define chipMinorFeatures7_SH_SNAP2PAGE_MAXPAGES_FIX 0x00002000 | ||
| 364 | #define chipMinorFeatures7_PE_RGBA16I_FIX 0x00004000 | ||
| 365 | #define chipMinorFeatures7_BLT_8bpp_256TILE_FC_FIX 0x00008000 | ||
| 366 | #define chipMinorFeatures7_PE_64BIT_FENCE_FIX 0x00010000 | ||
| 367 | #define chipMinorFeatures7_USC_FULL_CACHE_FIX 0x00020000 | ||
| 368 | #define chipMinorFeatures7_TX_YUV_ASSEMBLER_10BIT 0x00040000 | ||
| 369 | #define chipMinorFeatures7_FE_32BIT_INDEX_FIX 0x00080000 | ||
| 370 | #define chipMinorFeatures7_BLT_64BPP_MASKED_CLEAR_FIX 0x00100000 | ||
| 371 | #define chipMinorFeatures7_BIT_SECURITY 0x00200000 | ||
| 372 | #define chipMinorFeatures7_BIT_ROBUSTNESS 0x00400000 | ||
| 373 | #define chipMinorFeatures7_USC_ATOMIC_FIX 0x00800000 | ||
| 374 | #define chipMinorFeatures7_SH_PSO_MSAA1x_FIX 0x01000000 | ||
| 375 | #define chipMinorFeatures7_BIT_USC_VX_PERF_FIX 0x02000000 | ||
| 376 | #define chipMinorFeatures7_EVIS_NO_ABSDIFF 0x04000000 | ||
| 377 | #define chipMinorFeatures7_EVIS_NO_BITREPLACE 0x08000000 | ||
| 378 | #define chipMinorFeatures7_EVIS_NO_BOXFILTER 0x10000000 | ||
| 379 | #define chipMinorFeatures7_EVIS_NO_CORDIAC 0x20000000 | ||
| 380 | #define chipMinorFeatures7_EVIS_NO_DP32 0x40000000 | ||
| 381 | #define chipMinorFeatures7_EVIS_NO_FILTER 0x80000000 | ||
| 382 | #define chipMinorFeatures8_EVIS_NO_IADD 0x00000001 | ||
| 383 | #define chipMinorFeatures8_EVIS_NO_SELECTADD 0x00000002 | ||
| 384 | #define chipMinorFeatures8_EVIS_LERP_7OUTPUT 0x00000004 | ||
| 385 | #define chipMinorFeatures8_EVIS_ACCSQ_8OUTPUT 0x00000008 | ||
| 386 | #define chipMinorFeatures8_USC_GOS_ADDR_FIX 0x00000010 | ||
| 387 | #define chipMinorFeatures8_TX_8BIT_UVFRAC 0x00000020 | ||
| 388 | #define chipMinorFeatures8_TX_DESC_CACHE_CLOCKGATE_FIX 0x00000040 | ||
| 389 | #define chipMinorFeatures8_RSBLT_MSAA_DECOMPRESSION 0x00000080 | ||
| 390 | #define chipMinorFeatures8_TX_INTEGER_COORDINATE 0x00000100 | ||
| 391 | #define chipMinorFeatures8_DRAWID 0x00000200 | ||
| 392 | #define chipMinorFeatures8_PSIO_SAMPLEMASK_IN_R0ZW_FIX 0x00000400 | ||
| 393 | #define chipMinorFeatures8_TX_INTEGER_COORDINATE_V2 0x00000800 | ||
| 394 | #define chipMinorFeatures8_MULTI_CORE_BLOCK_SET_CONFIG 0x00001000 | ||
| 395 | #define chipMinorFeatures8_VG_RESOLVE_ENGINE 0x00002000 | ||
| 396 | #define chipMinorFeatures8_VG_PE_COLOR_KEY 0x00004000 | ||
| 397 | #define chipMinorFeatures8_VG_IM_INDEX_FORMAT 0x00008000 | ||
| 398 | #define chipMinorFeatures8_SNAPPAGE_CMD 0x00010000 | ||
| 399 | #define chipMinorFeatures8_SH_NO_INDEX_CONST_ON_A0 0x00020000 | ||
| 400 | #define chipMinorFeatures8_SH_NO_ONECONST_LIMIT 0x00040000 | ||
| 401 | #define chipMinorFeatures8_SH_IMG_LDST_ON_TEMP 0x00080000 | ||
| 402 | #define chipMinorFeatures8_COMPUTE_ONLY 0x00100000 | ||
| 403 | #define chipMinorFeatures8_SH_IMG_LDST_CLAMP 0x00200000 | ||
| 404 | #define chipMinorFeatures8_SH_ICACHE_ALLOC_COUNT_FIX 0x00400000 | ||
| 405 | #define chipMinorFeatures8_SH_ICACHE_PREFETCH 0x00800000 | ||
| 406 | #define chipMinorFeatures8_PE2D_SEPARATE_CACHE 0x01000000 | ||
| 407 | #define chipMinorFeatures8_VG_AYUV_INPUT_OUTPUT 0x02000000 | ||
| 408 | #define chipMinorFeatures8_VG_DOUBLE_IMAGE 0x04000000 | ||
| 409 | #define chipMinorFeatures8_VG_RECTANGLE_STRIPE_MODE 0x08000000 | ||
| 410 | #define chipMinorFeatures8_VG_MMU 0x10000000 | ||
| 411 | #define chipMinorFeatures8_VG_IM_FILTER 0x20000000 | ||
| 412 | #define chipMinorFeatures8_VG_IM_YUV_PACKET 0x40000000 | ||
| 413 | #define chipMinorFeatures8_VG_IM_YUV_PLANAR 0x80000000 | ||
| 414 | #define chipMinorFeatures9_VG_PE_YUV_PACKET 0x00000001 | ||
| 415 | #define chipMinorFeatures9_VG_COLOR_PRECISION_8_BIT 0x00000002 | ||
| 416 | #define chipMinorFeatures9_PE_MSAA_OQ_FIX 0x00000004 | ||
| 417 | #define chipMinorFeatures9_PSIO_MSAA_CL_FIX 0x00000008 | ||
| 418 | #define chipMinorFeatures9_USC_DEFER_FILL_FIX 0x00000010 | ||
| 419 | #define chipMinorFeatures9_SH_CLOCK_GATE_FIX 0x00000020 | ||
| 420 | #define chipMinorFeatures9_FE_NEED_DUMMYDRAW 0x00000040 | ||
| 421 | #define chipMinorFeatures9_PE2D_LINEAR_YUV420_OUTPUT 0x00000080 | ||
| 422 | #define chipMinorFeatures9_PE2D_LINEAR_YUV420_10BIT 0x00000100 | ||
| 423 | #define chipMinorFeatures9_MULTI_CLUSTER 0x00000200 | ||
| 424 | #define chipMinorFeatures9_VG_TS_CULLING 0x00000400 | ||
| 425 | #define chipMinorFeatures9_VG_FP25 0x00000800 | ||
| 426 | #define chipMinorFeatures9_SH_MULTI_WG_PACK 0x00001000 | ||
| 427 | #define chipMinorFeatures9_SH_DUAL16_SAMPLEMASK_ZW 0x00002000 | ||
| 428 | #define chipMinorFeatures9_TPG_TRIVIAL_MODE_FIX 0x00004000 | ||
| 429 | #define chipMinorFeatures9_TX_ASTC_MULTISLICE_FIX 0x00008000 | ||
| 430 | #define chipMinorFeatures9_FE_ROBUST_FIX 0x00010000 | ||
| 431 | #define chipMinorFeatures9_SH_GPIPE_ACCESS_FULLTEMPS 0x00020000 | ||
| 432 | #define chipMinorFeatures9_PSIO_INTERLOCK 0x00040000 | ||
| 433 | #define chipMinorFeatures9_PA_WIDELINE_FIX 0x00080000 | ||
| 434 | #define chipMinorFeatures9_WIDELINE_HELPER_FIX 0x00100000 | ||
| 435 | #define chipMinorFeatures9_G2D_3RD_PARTY_COMPRESSION_1_1 0x00200000 | ||
| 436 | #define chipMinorFeatures9_TX_FLUSH_L1CACHE 0x00400000 | ||
| 437 | #define chipMinorFeatures9_PE_DITHER_FIX2 0x00800000 | ||
| 438 | #define chipMinorFeatures9_G2D_DEC400 0x01000000 | ||
| 439 | #define chipMinorFeatures9_SH_TEXLD_U_FIX 0x02000000 | ||
| 440 | #define chipMinorFeatures9_MC_FCCACHE_BYTEMASK 0x04000000 | ||
| 441 | #define chipMinorFeatures9_SH_MULTI_WG_PACK_FIX 0x08000000 | ||
| 442 | #define chipMinorFeatures9_DC_OVERLAY_SCALING 0x10000000 | ||
| 443 | #define chipMinorFeatures9_DC_SOURCE_ROTATION 0x20000000 | ||
| 444 | #define chipMinorFeatures9_DC_TILED 0x40000000 | ||
| 445 | #define chipMinorFeatures9_DC_YUV_L1 0x80000000 | ||
| 446 | #define chipMinorFeatures10_DC_D30_OUTPUT 0x00000001 | ||
| 447 | #define chipMinorFeatures10_DC_MMU 0x00000002 | ||
| 448 | #define chipMinorFeatures10_DC_COMPRESSION 0x00000004 | ||
| 449 | #define chipMinorFeatures10_DC_QOS 0x00000008 | ||
| 450 | #define chipMinorFeatures10_PE_ADVANCE_BLEND_PART0 0x00000010 | ||
| 451 | #define chipMinorFeatures10_FE_PATCHLIST_FETCH_FIX 0x00000020 | ||
| 452 | #define chipMinorFeatures10_RA_CG_FIX 0x00000040 | ||
| 453 | #define chipMinorFeatures10_EVIS_VX2 0x00000080 | ||
| 454 | #define chipMinorFeatures10_NN_FLOAT 0x00000100 | ||
| 455 | #define chipMinorFeatures10_DEC400 0x00000200 | ||
| 456 | #define chipMinorFeatures10_LS_SUPPORT_PERCOMP_DEPENDENCY 0x00000400 | ||
| 457 | #define chipMinorFeatures10_TP_ENGINE 0x00000800 | ||
| 458 | #define chipMinorFeatures10_MULTI_CORE_BLOCK_SET_CONFIG2 0x00001000 | ||
| 459 | #define chipMinorFeatures10_PE_VMSAA_COVERAGE_CACHE_FIX 0x00002000 | ||
| 460 | #define chipMinorFeatures10_SECURITY_AHB 0x00004000 | ||
| 461 | #define chipMinorFeatures10_MULTICORE_SEMAPHORESTALL_V3 0x00008000 | ||
| 462 | #define chipMinorFeatures10_SMALLBATCH 0x00010000 | ||
| 463 | #define chipMinorFeatures10_SH_CMPLX 0x00020000 | ||
| 464 | #define chipMinorFeatures10_SH_IDIV0_SWZL_EHS 0x00040000 | ||
| 465 | #define chipMinorFeatures10_TX_LERP_LESS_BIT 0x00080000 | ||
| 466 | #define chipMinorFeatures10_SH_GM_ENDIAN 0x00100000 | ||
| 467 | #define chipMinorFeatures10_SH_GM_USC_UNALLOC 0x00200000 | ||
| 468 | #define chipMinorFeatures10_SH_END_OF_BB 0x00400000 | ||
| 469 | #define chipMinorFeatures10_VIP_V7 0x00800000 | ||
| 470 | #define chipMinorFeatures10_TX_BORDER_CLAMP_FIX 0x01000000 | ||
| 471 | #define chipMinorFeatures10_SH_IMG_LD_LASTPIXEL_FIX 0x02000000 | ||
| 472 | #define chipMinorFeatures10_ASYNC_BLT 0x04000000 | ||
| 473 | #define chipMinorFeatures10_ASYNC_FE_FENCE_FIX 0x08000000 | ||
| 474 | #define chipMinorFeatures10_PSCS_THROTTLE 0x10000000 | ||
| 475 | #define chipMinorFeatures10_SEPARATE_LS 0x20000000 | ||
| 476 | #define chipMinorFeatures10_MCFE 0x40000000 | ||
| 477 | #define chipMinorFeatures10_WIDELINE_TRIANGLE_EMU 0x80000000 | ||
| 478 | #define chipMinorFeatures11_VG_RESOLUTION_8K 0x00000001 | ||
| 479 | #define chipMinorFeatures11_FENCE_32BIT 0x00000002 | ||
| 480 | #define chipMinorFeatures11_FENCE_64BIT 0x00000004 | ||
| 481 | #define chipMinorFeatures11_NN_INTERLEVE8 0x00000008 | ||
| 482 | #define chipMinorFeatures11_TP_REORDER 0x00000010 | ||
| 483 | #define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020 | ||
| 319 | 484 | ||
| 320 | #endif /* COMMON_XML */ | 485 | #endif /* COMMON_XML */ |
diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h index c27c1484cfa9..421cb7cc0053 100644 --- a/drivers/gpu/drm/etnaviv/state.xml.h +++ b/drivers/gpu/drm/etnaviv/state.xml.h | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
| 2 | #ifndef STATE_XML | 1 | #ifndef STATE_XML |
| 3 | #define STATE_XML | 2 | #define STATE_XML |
| 4 | 3 | ||
| @@ -9,14 +8,40 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng | |||
| 9 | git clone git://0x04.net/rules-ng-ng | 8 | git clone git://0x04.net/rules-ng-ng |
| 10 | 9 | ||
| 11 | The rules-ng-ng source files this header was generated from are: | 10 | The rules-ng-ng source files this header was generated from are: |
| 12 | - state.xml ( 18882 bytes, from 2015-03-25 11:42:32) | 11 | - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) |
| 13 | - common.xml ( 18437 bytes, from 2015-03-25 11:27:41) | 12 | - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) |
| 14 | - state_hi.xml ( 23420 bytes, from 2015-03-25 11:47:21) | 13 | - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) |
| 15 | - state_2d.xml ( 51549 bytes, from 2015-03-25 11:25:06) | 14 | - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) |
| 16 | - state_3d.xml ( 54600 bytes, from 2015-03-25 11:25:19) | 15 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) |
| 17 | - state_vg.xml ( 5973 bytes, from 2015-03-25 11:26:01) | 16 | - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) |
| 18 | 17 | - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) | |
| 19 | Copyright (C) 2015 | 18 | - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) |
| 19 | - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) | ||
| 20 | |||
| 21 | Copyright (C) 2012-2017 by the following authors: | ||
| 22 | - Wladimir J. van der Laan <laanwj@gmail.com> | ||
| 23 | - Christian Gmeiner <christian.gmeiner@gmail.com> | ||
| 24 | - Lucas Stach <l.stach@pengutronix.de> | ||
| 25 | - Russell King <rmk@arm.linux.org.uk> | ||
| 26 | |||
| 27 | Permission is hereby granted, free of charge, to any person obtaining a | ||
| 28 | copy of this software and associated documentation files (the "Software"), | ||
| 29 | to deal in the Software without restriction, including without limitation | ||
| 30 | the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
| 31 | and/or sell copies of the Software, and to permit persons to whom the | ||
| 32 | Software is furnished to do so, subject to the following conditions: | ||
| 33 | |||
| 34 | The above copyright notice and this permission notice (including the | ||
| 35 | next paragraph) shall be included in all copies or substantial portions | ||
| 36 | of the Software. | ||
| 37 | |||
| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 39 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 40 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
| 41 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 42 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 43 | FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 44 | DEALINGS IN THE SOFTWARE. | ||
| 20 | */ | 45 | */ |
| 21 | 46 | ||
| 22 | 47 | ||
| @@ -24,9 +49,25 @@ Copyright (C) 2015 | |||
| 24 | #define VARYING_COMPONENT_USE_USED 0x00000001 | 49 | #define VARYING_COMPONENT_USE_USED 0x00000001 |
| 25 | #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 | 50 | #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 |
| 26 | #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 | 51 | #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 |
| 52 | #define FE_DATA_TYPE_BYTE 0x00000000 | ||
| 53 | #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001 | ||
| 54 | #define FE_DATA_TYPE_SHORT 0x00000002 | ||
| 55 | #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 | ||
| 56 | #define FE_DATA_TYPE_INT 0x00000004 | ||
| 57 | #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 | ||
| 58 | #define FE_DATA_TYPE_FLOAT 0x00000008 | ||
| 59 | #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 | ||
| 60 | #define FE_DATA_TYPE_FIXED 0x0000000b | ||
| 61 | #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c | ||
| 62 | #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d | ||
| 63 | #define FE_DATA_TYPE_BYTE_I 0x0000000e | ||
| 64 | #define FE_DATA_TYPE_SHORT_I 0x0000000f | ||
| 27 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff | 65 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff |
| 28 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 | 66 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 |
| 29 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) | 67 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) |
| 68 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000 | ||
| 69 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16 | ||
| 70 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK) | ||
| 30 | #define VIVS_FE 0x00000000 | 71 | #define VIVS_FE 0x00000000 |
| 31 | 72 | ||
| 32 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) | 73 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) |
| @@ -34,17 +75,7 @@ Copyright (C) 2015 | |||
| 34 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 | 75 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 |
| 35 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f | 76 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f |
| 36 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 | 77 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 |
| 37 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_BYTE 0x00000000 | 78 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK) |
| 38 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_BYTE 0x00000001 | ||
| 39 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_SHORT 0x00000002 | ||
| 40 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_SHORT 0x00000003 | ||
| 41 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT 0x00000004 | ||
| 42 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT 0x00000005 | ||
| 43 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT 0x00000008 | ||
| 44 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_HALF_FLOAT 0x00000009 | ||
| 45 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FIXED 0x0000000b | ||
| 46 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT_10_10_10_2 0x0000000c | ||
| 47 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d | ||
| 48 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 | 79 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 |
| 49 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 | 80 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 |
| 50 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) | 81 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) |
| @@ -76,6 +107,7 @@ Copyright (C) 2015 | |||
| 76 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 | 107 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 |
| 77 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 | 108 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 |
| 78 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 | 109 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 |
| 110 | #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100 | ||
| 79 | 111 | ||
| 80 | #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c | 112 | #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c |
| 81 | 113 | ||
| @@ -151,6 +183,8 @@ Copyright (C) 2015 | |||
| 151 | 183 | ||
| 152 | #define VIVS_FE_AUTO_FLUSH 0x00000670 | 184 | #define VIVS_FE_AUTO_FLUSH 0x00000670 |
| 153 | 185 | ||
| 186 | #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674 | ||
| 187 | |||
| 154 | #define VIVS_FE_UNK00678 0x00000678 | 188 | #define VIVS_FE_UNK00678 0x00000678 |
| 155 | 189 | ||
| 156 | #define VIVS_FE_UNK0067C 0x0000067c | 190 | #define VIVS_FE_UNK0067C 0x0000067c |
| @@ -163,17 +197,40 @@ Copyright (C) 2015 | |||
| 163 | 197 | ||
| 164 | #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) | 198 | #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) |
| 165 | 199 | ||
| 166 | #define VIVS_FE_UNK00700(i0) (0x00000700 + 0x4*(i0)) | 200 | #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) |
| 167 | #define VIVS_FE_UNK00700__ESIZE 0x00000004 | 201 | #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004 |
| 168 | #define VIVS_FE_UNK00700__LEN 0x00000010 | 202 | #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010 |
| 203 | |||
| 204 | #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) | ||
| 205 | |||
| 206 | #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) | ||
| 207 | |||
| 208 | #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) | ||
| 209 | |||
| 210 | #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) | ||
| 211 | |||
| 212 | #define VIVS_FE_HALTI5_UNK007C4 0x000007c4 | ||
| 213 | |||
| 214 | #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) | ||
| 215 | #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 | ||
| 216 | #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002 | ||
| 217 | |||
| 218 | #define VIVS_FE_HALTI5_UNK007D8 0x000007d8 | ||
| 219 | |||
| 220 | #define VIVS_FE_DESC_START 0x000007dc | ||
| 221 | |||
| 222 | #define VIVS_FE_DESC_END 0x000007e0 | ||
| 223 | |||
| 224 | #define VIVS_FE_DESC_AVAIL 0x000007e4 | ||
| 225 | #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f | ||
| 226 | #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0 | ||
| 227 | #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK) | ||
| 228 | |||
| 229 | #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8 | ||
| 169 | 230 | ||
| 170 | #define VIVS_FE_UNK00740(i0) (0x00000740 + 0x4*(i0)) | 231 | #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4 |
| 171 | #define VIVS_FE_UNK00740__ESIZE 0x00000004 | ||
| 172 | #define VIVS_FE_UNK00740__LEN 0x00000010 | ||
| 173 | 232 | ||
| 174 | #define VIVS_FE_UNK00780(i0) (0x00000780 + 0x4*(i0)) | 233 | #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 |
| 175 | #define VIVS_FE_UNK00780__ESIZE 0x00000004 | ||
| 176 | #define VIVS_FE_UNK00780__LEN 0x00000010 | ||
| 177 | 234 | ||
| 178 | #define VIVS_GL 0x00000000 | 235 | #define VIVS_GL 0x00000000 |
| 179 | 236 | ||
| @@ -188,6 +245,7 @@ Copyright (C) 2015 | |||
| 188 | #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) | 245 | #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) |
| 189 | #define VIVS_GL_EVENT_FROM_FE 0x00000020 | 246 | #define VIVS_GL_EVENT_FROM_FE 0x00000020 |
| 190 | #define VIVS_GL_EVENT_FROM_PE 0x00000040 | 247 | #define VIVS_GL_EVENT_FROM_PE 0x00000040 |
| 248 | #define VIVS_GL_EVENT_FROM_BLT 0x00000080 | ||
| 191 | #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 | 249 | #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 |
| 192 | #define VIVS_GL_EVENT_SOURCE__SHIFT 8 | 250 | #define VIVS_GL_EVENT_SOURCE__SHIFT 8 |
| 193 | #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) | 251 | #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) |
| @@ -199,6 +257,9 @@ Copyright (C) 2015 | |||
| 199 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 | 257 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 |
| 200 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 | 258 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 |
| 201 | #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) | 259 | #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) |
| 260 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000 | ||
| 261 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28 | ||
| 262 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK) | ||
| 202 | 263 | ||
| 203 | #define VIVS_GL_FLUSH_CACHE 0x0000380c | 264 | #define VIVS_GL_FLUSH_CACHE 0x0000380c |
| 204 | #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 | 265 | #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 |
| @@ -208,6 +269,10 @@ Copyright (C) 2015 | |||
| 208 | #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 | 269 | #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 |
| 209 | #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 | 270 | #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 |
| 210 | #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 | 271 | #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 |
| 272 | #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400 | ||
| 273 | #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 | ||
| 274 | #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 | ||
| 275 | #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 | ||
| 211 | 276 | ||
| 212 | #define VIVS_GL_FLUSH_MMU 0x00003810 | 277 | #define VIVS_GL_FLUSH_MMU 0x00003810 |
| 213 | #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 | 278 | #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 |
| @@ -244,30 +309,8 @@ Copyright (C) 2015 | |||
| 244 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) | 309 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) |
| 245 | 310 | ||
| 246 | #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 | 311 | #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 |
| 247 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 | 312 | |
| 248 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 | 313 | #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824 |
| 249 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK) | ||
| 250 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK 0x00000070 | ||
| 251 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT 4 | ||
| 252 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK) | ||
| 253 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK 0x00000700 | ||
| 254 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT 8 | ||
| 255 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK) | ||
| 256 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK 0x00007000 | ||
| 257 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT 12 | ||
| 258 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK) | ||
| 259 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK 0x00070000 | ||
| 260 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT 16 | ||
| 261 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK) | ||
| 262 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK 0x00700000 | ||
| 263 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT 20 | ||
| 264 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK) | ||
| 265 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK 0x07000000 | ||
| 266 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT 24 | ||
| 267 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK) | ||
| 268 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK 0x70000000 | ||
| 269 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT 28 | ||
| 270 | #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK) | ||
| 271 | 314 | ||
| 272 | #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) | 315 | #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) |
| 273 | #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 | 316 | #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 |
| @@ -321,6 +364,10 @@ Copyright (C) 2015 | |||
| 321 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 | 364 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 |
| 322 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) | 365 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) |
| 323 | 366 | ||
| 367 | #define VIVS_GL_UNK0382C 0x0000382c | ||
| 368 | |||
| 369 | #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 | ||
| 370 | |||
| 324 | #define VIVS_GL_UNK03834 0x00003834 | 371 | #define VIVS_GL_UNK03834 0x00003834 |
| 325 | 372 | ||
| 326 | #define VIVS_GL_UNK03838 0x00003838 | 373 | #define VIVS_GL_UNK03838 0x00003838 |
| @@ -332,8 +379,58 @@ Copyright (C) 2015 | |||
| 332 | 379 | ||
| 333 | #define VIVS_GL_CONTEXT_POINTER 0x00003850 | 380 | #define VIVS_GL_CONTEXT_POINTER 0x00003850 |
| 334 | 381 | ||
| 382 | #define VIVS_GL_UNK03854 0x00003854 | ||
| 383 | |||
| 384 | #define VIVS_GL_BUG_FIXES 0x00003860 | ||
| 385 | |||
| 386 | #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868 | ||
| 387 | |||
| 388 | #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c | ||
| 389 | |||
| 390 | #define VIVS_GL_HALTI5_UNK03884 0x00003884 | ||
| 391 | |||
| 392 | #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 | ||
| 393 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f | ||
| 394 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0 | ||
| 395 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK) | ||
| 396 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00 | ||
| 397 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8 | ||
| 398 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK) | ||
| 399 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000 | ||
| 400 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16 | ||
| 401 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK) | ||
| 402 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000 | ||
| 403 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24 | ||
| 404 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK) | ||
| 405 | |||
| 406 | #define VIVS_GL_GS_UNK0388C 0x0000388c | ||
| 407 | |||
| 408 | #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898 | ||
| 409 | |||
| 410 | #define VIVS_GL_SHADER_INDEX 0x0000389c | ||
| 411 | |||
| 412 | #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) | ||
| 413 | #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004 | ||
| 414 | #define VIVS_GL_GS_UNK038A0__LEN 0x00000008 | ||
| 415 | |||
| 416 | #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) | ||
| 417 | #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004 | ||
| 418 | #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010 | ||
| 419 | |||
| 420 | #define VIVS_GL_SECURITY_UNK3900 0x00003900 | ||
| 421 | |||
| 422 | #define VIVS_GL_SECURITY_UNK3904 0x00003904 | ||
| 423 | |||
| 335 | #define VIVS_GL_UNK03A00 0x00003a00 | 424 | #define VIVS_GL_UNK03A00 0x00003a00 |
| 336 | 425 | ||
| 426 | #define VIVS_GL_UNK03A04 0x00003a04 | ||
| 427 | |||
| 428 | #define VIVS_GL_UNK03A08 0x00003a08 | ||
| 429 | |||
| 430 | #define VIVS_GL_UNK03A0C 0x00003a0c | ||
| 431 | |||
| 432 | #define VIVS_GL_UNK03A10 0x00003a10 | ||
| 433 | |||
| 337 | #define VIVS_GL_STALL_TOKEN 0x00003c00 | 434 | #define VIVS_GL_STALL_TOKEN 0x00003c00 |
| 338 | #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f | 435 | #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f |
| 339 | #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0 | 436 | #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0 |
| @@ -344,6 +441,59 @@ Copyright (C) 2015 | |||
| 344 | #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 | 441 | #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 |
| 345 | #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 | 442 | #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 |
| 346 | 443 | ||
| 444 | #define VIVS_NFE 0x00000000 | ||
| 445 | |||
| 446 | #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) | ||
| 447 | #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004 | ||
| 448 | #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010 | ||
| 449 | |||
| 450 | #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) | ||
| 451 | |||
| 452 | #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) | ||
| 453 | |||
| 454 | #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) | ||
| 455 | |||
| 456 | #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) | ||
| 457 | |||
| 458 | #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) | ||
| 459 | #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004 | ||
| 460 | #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020 | ||
| 461 | |||
| 462 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) | ||
| 463 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f | ||
| 464 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0 | ||
| 465 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK) | ||
| 466 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030 | ||
| 467 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4 | ||
| 468 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK) | ||
| 469 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700 | ||
| 470 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8 | ||
| 471 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK) | ||
| 472 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000 | ||
| 473 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12 | ||
| 474 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK) | ||
| 475 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000 | ||
| 476 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14 | ||
| 477 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000 | ||
| 478 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000 | ||
| 479 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000 | ||
| 480 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16 | ||
| 481 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK) | ||
| 482 | |||
| 483 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) | ||
| 484 | |||
| 485 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) | ||
| 486 | |||
| 487 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) | ||
| 488 | |||
| 489 | #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) | ||
| 490 | |||
| 491 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) | ||
| 492 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff | ||
| 493 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0 | ||
| 494 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK) | ||
| 495 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800 | ||
| 496 | |||
| 347 | #define VIVS_DUMMY 0x00000000 | 497 | #define VIVS_DUMMY 0x00000000 |
| 348 | 498 | ||
| 349 | #define VIVS_DUMMY_DUMMY 0x0003fffc | 499 | #define VIVS_DUMMY_DUMMY 0x0003fffc |
diff --git a/drivers/gpu/drm/etnaviv/state_3d.xml.h b/drivers/gpu/drm/etnaviv/state_3d.xml.h index 73a97d35c51b..ebbd4fcf3096 100644 --- a/drivers/gpu/drm/etnaviv/state_3d.xml.h +++ b/drivers/gpu/drm/etnaviv/state_3d.xml.h | |||
| @@ -7,4 +7,9 @@ | |||
| 7 | #define VIVS_TS_FLUSH_CACHE 0x00001650 | 7 | #define VIVS_TS_FLUSH_CACHE 0x00001650 |
| 8 | #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 | 8 | #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 |
| 9 | 9 | ||
| 10 | #define VIVS_NTE_DESCRIPTOR_FLUSH 0x00014c44 | ||
| 11 | #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK 0xf0000000 | ||
| 12 | #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT 28 | ||
| 13 | #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x) (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK) | ||
| 14 | |||
| 10 | #endif /* STATE_3D_XML */ | 15 | #endif /* STATE_3D_XML */ |
diff --git a/drivers/gpu/drm/etnaviv/state_blt.xml.h b/drivers/gpu/drm/etnaviv/state_blt.xml.h new file mode 100644 index 000000000000..daae55995def --- /dev/null +++ b/drivers/gpu/drm/etnaviv/state_blt.xml.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | #ifndef STATE_BLT_XML | ||
| 2 | #define STATE_BLT_XML | ||
| 3 | |||
| 4 | /* Autogenerated file, DO NOT EDIT manually! | ||
| 5 | |||
| 6 | This file was generated by the rules-ng-ng headergen tool in this git repository: | ||
| 7 | http://0x04.net/cgit/index.cgi/rules-ng-ng | ||
| 8 | git clone git://0x04.net/rules-ng-ng | ||
| 9 | |||
| 10 | The rules-ng-ng source files this header was generated from are: | ||
| 11 | - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) | ||
| 12 | - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) | ||
| 13 | - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) | ||
| 14 | - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) | ||
| 15 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) | ||
| 16 | - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) | ||
| 17 | - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) | ||
| 18 | - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) | ||
| 19 | - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) | ||
| 20 | |||
| 21 | Copyright (C) 2012-2017 by the following authors: | ||
| 22 | - Wladimir J. van der Laan <laanwj@gmail.com> | ||
| 23 | - Christian Gmeiner <christian.gmeiner@gmail.com> | ||
| 24 | - Lucas Stach <l.stach@pengutronix.de> | ||
| 25 | - Russell King <rmk@arm.linux.org.uk> | ||
| 26 | |||
| 27 | Permission is hereby granted, free of charge, to any person obtaining a | ||
| 28 | copy of this software and associated documentation files (the "Software"), | ||
| 29 | to deal in the Software without restriction, including without limitation | ||
| 30 | the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
| 31 | and/or sell copies of the Software, and to permit persons to whom the | ||
| 32 | Software is furnished to do so, subject to the following conditions: | ||
| 33 | |||
| 34 | The above copyright notice and this permission notice (including the | ||
| 35 | next paragraph) shall be included in all copies or substantial portions | ||
| 36 | of the Software. | ||
| 37 | |||
| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 39 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 40 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
| 41 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 42 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 43 | FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 44 | DEALINGS IN THE SOFTWARE. | ||
| 45 | */ | ||
| 46 | |||
| 47 | /* This is a cut-down version of the state_blt.xml.h file */ | ||
| 48 | |||
| 49 | #define VIVS_BLT_ENABLE 0x000140b8 | ||
| 50 | #define VIVS_BLT_ENABLE_ENABLE 0x00000001 | ||
| 51 | |||
| 52 | #endif /* STATE_BLT_XML */ | ||
diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h index 60808daf7e8d..41d8da2b6f4f 100644 --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
| 2 | #ifndef STATE_HI_XML | 1 | #ifndef STATE_HI_XML |
| 3 | #define STATE_HI_XML | 2 | #define STATE_HI_XML |
| 4 | 3 | ||
| @@ -9,10 +8,40 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng | |||
| 9 | git clone git://0x04.net/rules-ng-ng | 8 | git clone git://0x04.net/rules-ng-ng |
| 10 | 9 | ||
| 11 | The rules-ng-ng source files this header was generated from are: | 10 | The rules-ng-ng source files this header was generated from are: |
| 12 | - state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) | 11 | - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) |
| 13 | - common.xml ( 20583 bytes, from 2016-06-07 05:22:38) | 12 | - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) |
| 14 | 13 | - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) | |
| 15 | Copyright (C) 2016 | 14 | - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) |
| 15 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) | ||
| 16 | - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) | ||
| 17 | - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) | ||
| 18 | - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) | ||
| 19 | - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) | ||
| 20 | |||
| 21 | Copyright (C) 2012-2018 by the following authors: | ||
| 22 | - Wladimir J. van der Laan <laanwj@gmail.com> | ||
| 23 | - Christian Gmeiner <christian.gmeiner@gmail.com> | ||
| 24 | - Lucas Stach <l.stach@pengutronix.de> | ||
| 25 | - Russell King <rmk@arm.linux.org.uk> | ||
| 26 | |||
| 27 | Permission is hereby granted, free of charge, to any person obtaining a | ||
| 28 | copy of this software and associated documentation files (the "Software"), | ||
| 29 | to deal in the Software without restriction, including without limitation | ||
| 30 | the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
| 31 | and/or sell copies of the Software, and to permit persons to whom the | ||
| 32 | Software is furnished to do so, subject to the following conditions: | ||
| 33 | |||
| 34 | The above copyright notice and this permission notice (including the | ||
| 35 | next paragraph) shall be included in all copies or substantial portions | ||
| 36 | of the Software. | ||
| 37 | |||
| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 39 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 40 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
| 41 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 42 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 43 | FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 44 | DEALINGS IN THE SOFTWARE. | ||
| 16 | */ | 45 | */ |
| 17 | 46 | ||
| 18 | 47 | ||
| @@ -192,6 +221,9 @@ Copyright (C) 2016 | |||
| 192 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 | 221 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 |
| 193 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) | 222 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) |
| 194 | 223 | ||
| 224 | #define VIVS_HI_COMPRESSION_FLAGS 0x00000090 | ||
| 225 | #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040 | ||
| 226 | |||
| 195 | #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 | 227 | #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 |
| 196 | 228 | ||
| 197 | #define VIVS_HI_CHIP_SPECS_4 0x0000009c | 229 | #define VIVS_HI_CHIP_SPECS_4 0x0000009c |
| @@ -203,6 +235,10 @@ Copyright (C) 2016 | |||
| 203 | 235 | ||
| 204 | #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 | 236 | #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 |
| 205 | 237 | ||
| 238 | #define VIVS_HI_BLT_INTR 0x000000d4 | ||
| 239 | |||
| 240 | #define VIVS_HI_AUXBIT 0x000000ec | ||
| 241 | |||
| 206 | #define VIVS_PM 0x00000000 | 242 | #define VIVS_PM 0x00000000 |
| 207 | 243 | ||
| 208 | #define VIVS_PM_POWER_CONTROLS 0x00000100 | 244 | #define VIVS_PM_POWER_CONTROLS 0x00000100 |
| @@ -239,6 +275,17 @@ Copyright (C) 2016 | |||
| 239 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 | 275 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 |
| 240 | 276 | ||
| 241 | #define VIVS_PM_PULSE_EATER 0x0000010c | 277 | #define VIVS_PM_PULSE_EATER 0x0000010c |
| 278 | #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001 | ||
| 279 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00 | ||
| 280 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8 | ||
| 281 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK) | ||
| 282 | #define VIVS_PM_PULSE_EATER_UNK16 0x00010000 | ||
| 283 | #define VIVS_PM_PULSE_EATER_UNK17 0x00020000 | ||
| 284 | #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000 | ||
| 285 | #define VIVS_PM_PULSE_EATER_UNK19 0x00080000 | ||
| 286 | #define VIVS_PM_PULSE_EATER_UNK20 0x00100000 | ||
| 287 | #define VIVS_PM_PULSE_EATER_UNK22 0x00400000 | ||
| 288 | #define VIVS_PM_PULSE_EATER_UNK23 0x00800000 | ||
| 242 | 289 | ||
| 243 | #define VIVS_MMUv2 0x00000000 | 290 | #define VIVS_MMUv2 0x00000000 |
| 244 | 291 | ||
| @@ -280,6 +327,68 @@ Copyright (C) 2016 | |||
| 280 | #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 | 327 | #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 |
| 281 | #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 | 328 | #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 |
| 282 | 329 | ||
| 330 | #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4 | ||
| 331 | |||
| 332 | #define VIVS_MMUv2_PTA_CONFIG 0x000001ac | ||
| 333 | #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff | ||
| 334 | #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0 | ||
| 335 | #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK) | ||
| 336 | #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000 | ||
| 337 | |||
| 338 | #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) | ||
| 339 | #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004 | ||
| 340 | #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008 | ||
| 341 | |||
| 342 | #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380 | ||
| 343 | |||
| 344 | #define VIVS_MMUv2_SEC_STATUS 0x00000384 | ||
| 345 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003 | ||
| 346 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0 | ||
| 347 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK) | ||
| 348 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030 | ||
| 349 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4 | ||
| 350 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK) | ||
| 351 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300 | ||
| 352 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8 | ||
| 353 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK) | ||
| 354 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000 | ||
| 355 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12 | ||
| 356 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK) | ||
| 357 | |||
| 358 | #define VIVS_MMUv2_SEC_CONTROL 0x00000388 | ||
| 359 | #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001 | ||
| 360 | |||
| 361 | #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c | ||
| 362 | |||
| 363 | #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390 | ||
| 364 | |||
| 365 | #define VIVS_MMUv2_PTA_CONTROL 0x00000394 | ||
| 366 | #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001 | ||
| 367 | |||
| 368 | #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398 | ||
| 369 | |||
| 370 | #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c | ||
| 371 | |||
| 372 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0 | ||
| 373 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff | ||
| 374 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0 | ||
| 375 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK) | ||
| 376 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000 | ||
| 377 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000 | ||
| 378 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16 | ||
| 379 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK) | ||
| 380 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000 | ||
| 381 | |||
| 382 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4 | ||
| 383 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff | ||
| 384 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0 | ||
| 385 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK) | ||
| 386 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000 | ||
| 387 | |||
| 388 | #define VIVS_MMUv2_AHB_CONTROL 0x000003a8 | ||
| 389 | #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001 | ||
| 390 | #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002 | ||
| 391 | |||
| 283 | #define VIVS_MC 0x00000000 | 392 | #define VIVS_MC 0x00000000 |
| 284 | 393 | ||
| 285 | #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 | 394 | #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 |
| @@ -340,13 +449,13 @@ Copyright (C) 2016 | |||
| 340 | #define VIVS_MC_PROFILE_HI_READ 0x0000046c | 449 | #define VIVS_MC_PROFILE_HI_READ 0x0000046c |
| 341 | 450 | ||
| 342 | #define VIVS_MC_PROFILE_CONFIG0 0x00000470 | 451 | #define VIVS_MC_PROFILE_CONFIG0 0x00000470 |
| 343 | #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x0000000f | 452 | #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff |
| 344 | #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 | 453 | #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 |
| 345 | #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f | 454 | #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f |
| 346 | #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x00000f00 | 455 | #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00 |
| 347 | #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 | 456 | #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 |
| 348 | #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 | 457 | #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 |
| 349 | #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x000f0000 | 458 | #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000 |
| 350 | #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 | 459 | #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 |
| 351 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 | 460 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 |
| 352 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 | 461 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 |
| @@ -354,7 +463,7 @@ Copyright (C) 2016 | |||
| 354 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 | 463 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 |
| 355 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 | 464 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 |
| 356 | #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 | 465 | #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 |
| 357 | #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0x0f000000 | 466 | #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000 |
| 358 | #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 | 467 | #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 |
| 359 | #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 | 468 | #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 |
| 360 | #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 | 469 | #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 |
| @@ -368,7 +477,7 @@ Copyright (C) 2016 | |||
| 368 | #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 | 477 | #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 |
| 369 | 478 | ||
| 370 | #define VIVS_MC_PROFILE_CONFIG1 0x00000474 | 479 | #define VIVS_MC_PROFILE_CONFIG1 0x00000474 |
| 371 | #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x0000000f | 480 | #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff |
| 372 | #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 | 481 | #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 |
| 373 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 | 482 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 |
| 374 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 | 483 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 |
| @@ -377,12 +486,12 @@ Copyright (C) 2016 | |||
| 377 | #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 | 486 | #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 |
| 378 | #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 | 487 | #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 |
| 379 | #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f | 488 | #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f |
| 380 | #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x00000f00 | 489 | #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00 |
| 381 | #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 | 490 | #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 |
| 382 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 | 491 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 |
| 383 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 | 492 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 |
| 384 | #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 | 493 | #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 |
| 385 | #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x000f0000 | 494 | #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000 |
| 386 | #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 | 495 | #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 |
| 387 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 | 496 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 |
| 388 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 | 497 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 |
| @@ -392,7 +501,7 @@ Copyright (C) 2016 | |||
| 392 | #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 | 501 | #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 |
| 393 | #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 | 502 | #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 |
| 394 | #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 | 503 | #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 |
| 395 | #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0x0f000000 | 504 | #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000 |
| 396 | #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 | 505 | #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 |
| 397 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 | 506 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 |
| 398 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 | 507 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 |
| @@ -407,18 +516,21 @@ Copyright (C) 2016 | |||
| 407 | #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 | 516 | #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 |
| 408 | 517 | ||
| 409 | #define VIVS_MC_PROFILE_CONFIG2 0x00000478 | 518 | #define VIVS_MC_PROFILE_CONFIG2 0x00000478 |
| 410 | #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x0000000f | 519 | #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff |
| 411 | #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 | 520 | #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 |
| 412 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 | 521 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 |
| 413 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 | 522 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 |
| 414 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 | 523 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 |
| 415 | #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f | 524 | #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f |
| 416 | #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x00000f00 | 525 | #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00 |
| 417 | #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 | 526 | #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 |
| 418 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 | 527 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 |
| 419 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 | 528 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 |
| 420 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 | 529 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 |
| 421 | #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 | 530 | #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 |
| 531 | #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000 | ||
| 532 | #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24 | ||
| 533 | #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000 | ||
| 422 | 534 | ||
| 423 | #define VIVS_MC_PROFILE_CONFIG3 0x0000047c | 535 | #define VIVS_MC_PROFILE_CONFIG3 0x0000047c |
| 424 | 536 | ||
| @@ -432,7 +544,13 @@ Copyright (C) 2016 | |||
| 432 | 544 | ||
| 433 | #define VIVS_MC_START_COMPOSITION 0x00000554 | 545 | #define VIVS_MC_START_COMPOSITION 0x00000554 |
| 434 | 546 | ||
| 435 | #define VIVS_MC_128B_MERGE 0x00000558 | 547 | #define VIVS_MC_FLAGS 0x00000558 |
| 548 | #define VIVS_MC_FLAGS_128B_MERGE 0x00000001 | ||
| 549 | #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000 | ||
| 550 | |||
| 551 | #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c | ||
| 552 | |||
| 553 | #define VIVS_MC_PROFILE_L2_READ 0x00000564 | ||
| 436 | 554 | ||
| 437 | 555 | ||
| 438 | #endif /* STATE_HI_XML */ | 556 | #endif /* STATE_HI_XML */ |