diff options
41 files changed, 252 insertions, 136 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 2bfc987a8c30..98f8a5c92314 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -1159,6 +1159,7 @@ F: arch/arm/mach-footbridge/ | |||
| 1159 | ARM/FREESCALE IMX / MXC ARM ARCHITECTURE | 1159 | ARM/FREESCALE IMX / MXC ARM ARCHITECTURE |
| 1160 | M: Shawn Guo <shawnguo@kernel.org> | 1160 | M: Shawn Guo <shawnguo@kernel.org> |
| 1161 | M: Sascha Hauer <kernel@pengutronix.de> | 1161 | M: Sascha Hauer <kernel@pengutronix.de> |
| 1162 | R: Fabio Estevam <fabio.estevam@nxp.com> | ||
| 1162 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 1163 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1163 | S: Maintained | 1164 | S: Maintained |
| 1164 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git | 1165 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d695bf..414b42710a36 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -741,6 +741,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ | |||
| 741 | sun7i-a20-olimex-som-evb.dtb \ | 741 | sun7i-a20-olimex-som-evb.dtb \ |
| 742 | sun7i-a20-olinuxino-lime.dtb \ | 742 | sun7i-a20-olinuxino-lime.dtb \ |
| 743 | sun7i-a20-olinuxino-lime2.dtb \ | 743 | sun7i-a20-olinuxino-lime2.dtb \ |
| 744 | sun7i-a20-olinuxino-lime2-emmc.dtb \ | ||
| 744 | sun7i-a20-olinuxino-micro.dtb \ | 745 | sun7i-a20-olinuxino-micro.dtb \ |
| 745 | sun7i-a20-orangepi.dtb \ | 746 | sun7i-a20-orangepi.dtb \ |
| 746 | sun7i-a20-orangepi-mini.dtb \ | 747 | sun7i-a20-orangepi-mini.dtb \ |
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index d82dd6e3f9b1..5687d6b4da60 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts | |||
| @@ -418,7 +418,7 @@ | |||
| 418 | status = "okay"; | 418 | status = "okay"; |
| 419 | pinctrl-names = "default"; | 419 | pinctrl-names = "default"; |
| 420 | pinctrl-0 = <&i2c0_pins>; | 420 | pinctrl-0 = <&i2c0_pins>; |
| 421 | clock-frequency = <400000>; | 421 | clock-frequency = <100000>; |
| 422 | 422 | ||
| 423 | tps@24 { | 423 | tps@24 { |
| 424 | compatible = "ti,tps65218"; | 424 | compatible = "ti,tps65218"; |
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index b01a5948cdd0..0e63b9dff6e7 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi | |||
| @@ -60,10 +60,26 @@ | |||
| 60 | 60 | ||
| 61 | tps659038_pmic { | 61 | tps659038_pmic { |
| 62 | compatible = "ti,tps659038-pmic"; | 62 | compatible = "ti,tps659038-pmic"; |
| 63 | |||
| 64 | smps12-in-supply = <&vmain>; | ||
| 65 | smps3-in-supply = <&vmain>; | ||
| 66 | smps45-in-supply = <&vmain>; | ||
| 67 | smps6-in-supply = <&vmain>; | ||
| 68 | smps7-in-supply = <&vmain>; | ||
| 69 | smps8-in-supply = <&vmain>; | ||
| 70 | smps9-in-supply = <&vmain>; | ||
| 71 | ldo1-in-supply = <&vmain>; | ||
| 72 | ldo2-in-supply = <&vmain>; | ||
| 73 | ldo3-in-supply = <&vmain>; | ||
| 74 | ldo4-in-supply = <&vmain>; | ||
| 75 | ldo9-in-supply = <&vmain>; | ||
| 76 | ldoln-in-supply = <&vmain>; | ||
| 77 | ldousb-in-supply = <&vmain>; | ||
| 78 | ldortc-in-supply = <&vmain>; | ||
| 79 | |||
| 63 | regulators { | 80 | regulators { |
| 64 | smps12_reg: smps12 { | 81 | smps12_reg: smps12 { |
| 65 | /* VDD_MPU */ | 82 | /* VDD_MPU */ |
| 66 | vin-supply = <&vmain>; | ||
| 67 | regulator-name = "smps12"; | 83 | regulator-name = "smps12"; |
| 68 | regulator-min-microvolt = <850000>; | 84 | regulator-min-microvolt = <850000>; |
| 69 | regulator-max-microvolt = <1250000>; | 85 | regulator-max-microvolt = <1250000>; |
| @@ -73,7 +89,6 @@ | |||
| 73 | 89 | ||
| 74 | smps3_reg: smps3 { | 90 | smps3_reg: smps3 { |
| 75 | /* VDD_DDR EMIF1 EMIF2 */ | 91 | /* VDD_DDR EMIF1 EMIF2 */ |
| 76 | vin-supply = <&vmain>; | ||
| 77 | regulator-name = "smps3"; | 92 | regulator-name = "smps3"; |
| 78 | regulator-min-microvolt = <1350000>; | 93 | regulator-min-microvolt = <1350000>; |
| 79 | regulator-max-microvolt = <1350000>; | 94 | regulator-max-microvolt = <1350000>; |
| @@ -84,7 +99,6 @@ | |||
| 84 | smps45_reg: smps45 { | 99 | smps45_reg: smps45 { |
| 85 | /* VDD_DSPEVE on AM572 */ | 100 | /* VDD_DSPEVE on AM572 */ |
| 86 | /* VDD_IVA + VDD_DSP on AM571 */ | 101 | /* VDD_IVA + VDD_DSP on AM571 */ |
| 87 | vin-supply = <&vmain>; | ||
| 88 | regulator-name = "smps45"; | 102 | regulator-name = "smps45"; |
| 89 | regulator-min-microvolt = <850000>; | 103 | regulator-min-microvolt = <850000>; |
| 90 | regulator-max-microvolt = <1250000>; | 104 | regulator-max-microvolt = <1250000>; |
| @@ -94,7 +108,6 @@ | |||
| 94 | 108 | ||
| 95 | smps6_reg: smps6 { | 109 | smps6_reg: smps6 { |
| 96 | /* VDD_GPU */ | 110 | /* VDD_GPU */ |
| 97 | vin-supply = <&vmain>; | ||
| 98 | regulator-name = "smps6"; | 111 | regulator-name = "smps6"; |
| 99 | regulator-min-microvolt = <850000>; | 112 | regulator-min-microvolt = <850000>; |
| 100 | regulator-max-microvolt = <1250000>; | 113 | regulator-max-microvolt = <1250000>; |
| @@ -104,7 +117,6 @@ | |||
| 104 | 117 | ||
| 105 | smps7_reg: smps7 { | 118 | smps7_reg: smps7 { |
| 106 | /* VDD_CORE */ | 119 | /* VDD_CORE */ |
| 107 | vin-supply = <&vmain>; | ||
| 108 | regulator-name = "smps7"; | 120 | regulator-name = "smps7"; |
| 109 | regulator-min-microvolt = <850000>; | 121 | regulator-min-microvolt = <850000>; |
| 110 | regulator-max-microvolt = <1150000>; | 122 | regulator-max-microvolt = <1150000>; |
| @@ -115,13 +127,11 @@ | |||
| 115 | smps8_reg: smps8 { | 127 | smps8_reg: smps8 { |
| 116 | /* 5728 - VDD_IVAHD */ | 128 | /* 5728 - VDD_IVAHD */ |
| 117 | /* 5718 - N.C. test point */ | 129 | /* 5718 - N.C. test point */ |
| 118 | vin-supply = <&vmain>; | ||
| 119 | regulator-name = "smps8"; | 130 | regulator-name = "smps8"; |
| 120 | }; | 131 | }; |
| 121 | 132 | ||
| 122 | smps9_reg: smps9 { | 133 | smps9_reg: smps9 { |
| 123 | /* VDD_3_3D */ | 134 | /* VDD_3_3D */ |
| 124 | vin-supply = <&vmain>; | ||
| 125 | regulator-name = "smps9"; | 135 | regulator-name = "smps9"; |
| 126 | regulator-min-microvolt = <3300000>; | 136 | regulator-min-microvolt = <3300000>; |
| 127 | regulator-max-microvolt = <3300000>; | 137 | regulator-max-microvolt = <3300000>; |
| @@ -132,7 +142,6 @@ | |||
| 132 | ldo1_reg: ldo1 { | 142 | ldo1_reg: ldo1 { |
| 133 | /* VDDSHV8 - VSDMMC */ | 143 | /* VDDSHV8 - VSDMMC */ |
| 134 | /* NOTE: on rev 1.3a, data supply */ | 144 | /* NOTE: on rev 1.3a, data supply */ |
| 135 | vin-supply = <&vmain>; | ||
| 136 | regulator-name = "ldo1"; | 145 | regulator-name = "ldo1"; |
| 137 | regulator-min-microvolt = <1800000>; | 146 | regulator-min-microvolt = <1800000>; |
| 138 | regulator-max-microvolt = <3300000>; | 147 | regulator-max-microvolt = <3300000>; |
| @@ -142,7 +151,6 @@ | |||
| 142 | 151 | ||
| 143 | ldo2_reg: ldo2 { | 152 | ldo2_reg: ldo2 { |
| 144 | /* VDDSH18V */ | 153 | /* VDDSH18V */ |
| 145 | vin-supply = <&vmain>; | ||
| 146 | regulator-name = "ldo2"; | 154 | regulator-name = "ldo2"; |
| 147 | regulator-min-microvolt = <1800000>; | 155 | regulator-min-microvolt = <1800000>; |
| 148 | regulator-max-microvolt = <1800000>; | 156 | regulator-max-microvolt = <1800000>; |
| @@ -152,7 +160,6 @@ | |||
| 152 | 160 | ||
| 153 | ldo3_reg: ldo3 { | 161 | ldo3_reg: ldo3 { |
| 154 | /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ | 162 | /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ |
| 155 | vin-supply = <&vmain>; | ||
| 156 | regulator-name = "ldo3"; | 163 | regulator-name = "ldo3"; |
| 157 | regulator-min-microvolt = <1800000>; | 164 | regulator-min-microvolt = <1800000>; |
| 158 | regulator-max-microvolt = <1800000>; | 165 | regulator-max-microvolt = <1800000>; |
| @@ -162,7 +169,6 @@ | |||
| 162 | 169 | ||
| 163 | ldo4_reg: ldo4 { | 170 | ldo4_reg: ldo4 { |
| 164 | /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ | 171 | /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ |
| 165 | vin-supply = <&vmain>; | ||
| 166 | regulator-name = "ldo4"; | 172 | regulator-name = "ldo4"; |
| 167 | regulator-min-microvolt = <1800000>; | 173 | regulator-min-microvolt = <1800000>; |
| 168 | regulator-max-microvolt = <1800000>; | 174 | regulator-max-microvolt = <1800000>; |
| @@ -174,7 +180,6 @@ | |||
| 174 | 180 | ||
| 175 | ldo9_reg: ldo9 { | 181 | ldo9_reg: ldo9 { |
| 176 | /* VDD_RTC */ | 182 | /* VDD_RTC */ |
| 177 | vin-supply = <&vmain>; | ||
| 178 | regulator-name = "ldo9"; | 183 | regulator-name = "ldo9"; |
| 179 | regulator-min-microvolt = <840000>; | 184 | regulator-min-microvolt = <840000>; |
| 180 | regulator-max-microvolt = <1160000>; | 185 | regulator-max-microvolt = <1160000>; |
| @@ -184,7 +189,6 @@ | |||
| 184 | 189 | ||
| 185 | ldoln_reg: ldoln { | 190 | ldoln_reg: ldoln { |
| 186 | /* VDDA_1V8_PLL */ | 191 | /* VDDA_1V8_PLL */ |
| 187 | vin-supply = <&vmain>; | ||
| 188 | regulator-name = "ldoln"; | 192 | regulator-name = "ldoln"; |
| 189 | regulator-min-microvolt = <1800000>; | 193 | regulator-min-microvolt = <1800000>; |
| 190 | regulator-max-microvolt = <1800000>; | 194 | regulator-max-microvolt = <1800000>; |
| @@ -194,7 +198,6 @@ | |||
| 194 | 198 | ||
| 195 | ldousb_reg: ldousb { | 199 | ldousb_reg: ldousb { |
| 196 | /* VDDA_3V_USB: VDDA_USBHS33 */ | 200 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
| 197 | vin-supply = <&vmain>; | ||
| 198 | regulator-name = "ldousb"; | 201 | regulator-name = "ldousb"; |
| 199 | regulator-min-microvolt = <3300000>; | 202 | regulator-min-microvolt = <3300000>; |
| 200 | regulator-max-microvolt = <3300000>; | 203 | regulator-max-microvolt = <3300000>; |
| @@ -204,7 +207,6 @@ | |||
| 204 | 207 | ||
| 205 | ldortc_reg: ldortc { | 208 | ldortc_reg: ldortc { |
| 206 | /* VDDA_RTC */ | 209 | /* VDDA_RTC */ |
| 207 | vin-supply = <&vmain>; | ||
| 208 | regulator-name = "ldortc"; | 210 | regulator-name = "ldortc"; |
| 209 | regulator-min-microvolt = <1800000>; | 211 | regulator-min-microvolt = <1800000>; |
| 210 | regulator-max-microvolt = <1800000>; | 212 | regulator-max-microvolt = <1800000>; |
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index cbc17b0794b1..4128fa91823c 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts | |||
| @@ -93,6 +93,10 @@ | |||
| 93 | }; | 93 | }; |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | &mmc1 { | ||
| 97 | status = "disabled"; | ||
| 98 | }; | ||
| 99 | |||
| 96 | &mmc2 { | 100 | &mmc2 { |
| 97 | pinctrl-names = "default"; | 101 | pinctrl-names = "default"; |
| 98 | pinctrl-0 = <&sd1_pins>; | 102 | pinctrl-0 = <&sd1_pins>; |
| @@ -101,6 +105,10 @@ | |||
| 101 | cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; | 105 | cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; |
| 102 | }; | 106 | }; |
| 103 | 107 | ||
| 108 | &mmc3 { | ||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 104 | &pincntl { | 112 | &pincntl { |
| 105 | sd1_pins: pinmux_sd1_pins { | 113 | sd1_pins: pinmux_sd1_pins { |
| 106 | pinctrl-single,pins = < | 114 | pinctrl-single,pins = < |
diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts index 5d4313fd5a46..3f184863e0c5 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/dm8148-t410.dts | |||
| @@ -45,6 +45,14 @@ | |||
| 45 | phy-mode = "rgmii"; | 45 | phy-mode = "rgmii"; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | &mmc1 { | ||
| 49 | status = "disabled"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | &mmc2 { | ||
| 53 | status = "disabled"; | ||
| 54 | }; | ||
| 55 | |||
| 48 | &mmc3 { | 56 | &mmc3 { |
| 49 | pinctrl-names = "default"; | 57 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&sd2_pins>; | 58 | pinctrl-0 = <&sd2_pins>; |
| @@ -53,6 +61,7 @@ | |||
| 53 | dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ | 61 | dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ |
| 54 | &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ | 62 | &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ |
| 55 | dma-names = "tx", "rx"; | 63 | dma-names = "tx", "rx"; |
| 64 | non-removable; | ||
| 56 | }; | 65 | }; |
| 57 | 66 | ||
| 58 | &pincntl { | 67 | &pincntl { |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e0074014385a..3a8f3976f6f9 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
| @@ -1451,6 +1451,8 @@ | |||
| 1451 | ti,hwmods = "gpmc"; | 1451 | ti,hwmods = "gpmc"; |
| 1452 | reg = <0x50000000 0x37c>; /* device IO registers */ | 1452 | reg = <0x50000000 0x37c>; /* device IO registers */ |
| 1453 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | 1453 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 1454 | dmas = <&edma_xbar 4 0>; | ||
| 1455 | dma-names = "rxtx"; | ||
| 1454 | gpmc,num-cs = <8>; | 1456 | gpmc,num-cs = <8>; |
| 1455 | gpmc,num-waitpins = <2>; | 1457 | gpmc,num-waitpins = <2>; |
| 1456 | #address-cells = <2>; | 1458 | #address-cells = <2>; |
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 4220eeffc65a..5e06020f450b 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi | |||
| @@ -107,8 +107,8 @@ | |||
| 107 | reg = <0x58000000 0x80>, | 107 | reg = <0x58000000 0x80>, |
| 108 | <0x58004054 0x4>, | 108 | <0x58004054 0x4>, |
| 109 | <0x58004300 0x20>, | 109 | <0x58004300 0x20>, |
| 110 | <0x58005054 0x4>, | 110 | <0x58009054 0x4>, |
| 111 | <0x58005300 0x20>; | 111 | <0x58009300 0x20>; |
| 112 | reg-names = "dss", "pll1_clkctrl", "pll1", | 112 | reg-names = "dss", "pll1_clkctrl", "pll1", |
| 113 | "pll2_clkctrl", "pll2"; | 113 | "pll2_clkctrl", "pll2"; |
| 114 | 114 | ||
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index ddfe1f558c10..fa14f77df563 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi | |||
| @@ -242,7 +242,7 @@ | |||
| 242 | hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; | 242 | hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; |
| 243 | 243 | ||
| 244 | ports { | 244 | ports { |
| 245 | port0 { | 245 | port { |
| 246 | dp_out: endpoint { | 246 | dp_out: endpoint { |
| 247 | remote-endpoint = <&bridge_in>; | 247 | remote-endpoint = <&bridge_in>; |
| 248 | }; | 248 | }; |
| @@ -485,13 +485,20 @@ | |||
| 485 | edid-emulation = <5>; | 485 | edid-emulation = <5>; |
| 486 | 486 | ||
| 487 | ports { | 487 | ports { |
| 488 | port0 { | 488 | #address-cells = <1>; |
| 489 | #size-cells = <0>; | ||
| 490 | |||
| 491 | port@0 { | ||
| 492 | reg = <0>; | ||
| 493 | |||
| 489 | bridge_out: endpoint { | 494 | bridge_out: endpoint { |
| 490 | remote-endpoint = <&panel_in>; | 495 | remote-endpoint = <&panel_in>; |
| 491 | }; | 496 | }; |
| 492 | }; | 497 | }; |
| 493 | 498 | ||
| 494 | port1 { | 499 | port@1 { |
| 500 | reg = <1>; | ||
| 501 | |||
| 495 | bridge_in: endpoint { | 502 | bridge_in: endpoint { |
| 496 | remote-endpoint = <&dp_out>; | 503 | remote-endpoint = <&dp_out>; |
| 497 | }; | 504 | }; |
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f9d2e4f1a0e0..1de972d46a87 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts | |||
| @@ -163,7 +163,7 @@ | |||
| 163 | hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; | 163 | hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; |
| 164 | 164 | ||
| 165 | ports { | 165 | ports { |
| 166 | port0 { | 166 | port { |
| 167 | dp_out: endpoint { | 167 | dp_out: endpoint { |
| 168 | remote-endpoint = <&bridge_in>; | 168 | remote-endpoint = <&bridge_in>; |
| 169 | }; | 169 | }; |
| @@ -631,13 +631,20 @@ | |||
| 631 | use-external-pwm; | 631 | use-external-pwm; |
| 632 | 632 | ||
| 633 | ports { | 633 | ports { |
| 634 | port0 { | 634 | #address-cells = <1>; |
| 635 | #size-cells = <0>; | ||
| 636 | |||
| 637 | port@0 { | ||
| 638 | reg = <0>; | ||
| 639 | |||
| 635 | bridge_out: endpoint { | 640 | bridge_out: endpoint { |
| 636 | remote-endpoint = <&panel_in>; | 641 | remote-endpoint = <&panel_in>; |
| 637 | }; | 642 | }; |
| 638 | }; | 643 | }; |
| 639 | 644 | ||
| 640 | port1 { | 645 | port@1 { |
| 646 | reg = <1>; | ||
| 647 | |||
| 641 | bridge_in: endpoint { | 648 | bridge_in: endpoint { |
| 642 | remote-endpoint = <&dp_out>; | 649 | remote-endpoint = <&dp_out>; |
| 643 | }; | 650 | }; |
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index 76056ba92ced..ed449827c3d3 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts | |||
| @@ -85,7 +85,7 @@ | |||
| 85 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | 85 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ |
| 86 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | 86 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ |
| 87 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | 87 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ |
| 88 | OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | 88 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ |
| 89 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | 89 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ |
| 90 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | 90 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ |
| 91 | >; | 91 | >; |
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 41f5d386f21f..f4f2ce46d681 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi | |||
| @@ -188,6 +188,7 @@ | |||
| 188 | vmmc-supply = <&vmmc1>; | 188 | vmmc-supply = <&vmmc1>; |
| 189 | vmmc_aux-supply = <&vsim>; | 189 | vmmc_aux-supply = <&vsim>; |
| 190 | bus-width = <4>; | 190 | bus-width = <4>; |
| 191 | cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; | ||
| 191 | }; | 192 | }; |
| 192 | 193 | ||
| 193 | &mmc3 { | 194 | &mmc3 { |
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index d6f839cab649..b6971060648a 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi | |||
| @@ -194,6 +194,12 @@ | |||
| 194 | OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ | 194 | OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ |
| 195 | >; | 195 | >; |
| 196 | }; | 196 | }; |
| 197 | |||
| 198 | mmc1_wp_pins: pinmux_mmc1_cd_pins { | ||
| 199 | pinctrl-single,pins = < | ||
| 200 | OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ | ||
| 201 | >; | ||
| 202 | }; | ||
| 197 | }; | 203 | }; |
| 198 | 204 | ||
| 199 | &i2c3 { | 205 | &i2c3 { |
| @@ -250,3 +256,8 @@ | |||
| 250 | }; | 256 | }; |
| 251 | }; | 257 | }; |
| 252 | }; | 258 | }; |
| 259 | |||
| 260 | &mmc1 { | ||
| 261 | pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; | ||
| 262 | wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ | ||
| 263 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index d9e2d9c6e999..2b74a81d1de2 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts | |||
| @@ -288,7 +288,7 @@ | |||
| 288 | pinctrl-single,pins = < | 288 | pinctrl-single,pins = < |
| 289 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ | 289 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ |
| 290 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ | 290 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ |
| 291 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ | 291 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ |
| 292 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ | 292 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ |
| 293 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ | 293 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ |
| 294 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ | 294 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ |
| @@ -300,7 +300,7 @@ | |||
| 300 | modem_pins: pinmux_modem { | 300 | modem_pins: pinmux_modem { |
| 301 | pinctrl-single,pins = < | 301 | pinctrl-single,pins = < |
| 302 | OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ | 302 | OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ |
| 303 | OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */ | 303 | OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ |
| 304 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ | 304 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ |
| 305 | OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ | 305 | OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ |
| 306 | OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ | 306 | OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ |
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index a00ca761675d..927b17fc4ed8 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi | |||
| @@ -97,7 +97,7 @@ | |||
| 97 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ | 97 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ |
| 98 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ | 98 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ |
| 99 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ | 99 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ |
| 100 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ | 100 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ |
| 101 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ | 101 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ |
| 102 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ | 102 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ |
| 103 | OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ | 103 | OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ |
| @@ -110,7 +110,7 @@ | |||
| 110 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ | 110 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ |
| 111 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ | 111 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ |
| 112 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ | 112 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ |
| 113 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ | 113 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ |
| 114 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ | 114 | OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ |
| 115 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ | 115 | OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ |
| 116 | OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ | 116 | OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ |
| @@ -120,7 +120,7 @@ | |||
| 120 | 120 | ||
| 121 | modem_pins1: pinmux_modem_core1_pins { | 121 | modem_pins1: pinmux_modem_core1_pins { |
| 122 | pinctrl-single,pins = < | 122 | pinctrl-single,pins = < |
| 123 | OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ | 123 | OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ |
| 124 | OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ | 124 | OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ |
| 125 | OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ | 125 | OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ |
| 126 | >; | 126 | >; |
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index f19170bdcc1f..c29b41dc7b95 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts | |||
| @@ -98,7 +98,7 @@ | |||
| 98 | pinctrl-single,pins = < | 98 | pinctrl-single,pins = < |
| 99 | OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ | 99 | OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ |
| 100 | OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ | 100 | OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ |
| 101 | OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ | 101 | OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ |
| 102 | OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ | 102 | OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ |
| 103 | >; | 103 | >; |
| 104 | }; | 104 | }; |
| @@ -107,7 +107,7 @@ | |||
| 107 | pinctrl-single,pins = < | 107 | pinctrl-single,pins = < |
| 108 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ | 108 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ |
| 109 | OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ | 109 | OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ |
| 110 | OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | 110 | OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ |
| 111 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | 111 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ |
| 112 | >; | 112 | >; |
| 113 | }; | 113 | }; |
| @@ -125,7 +125,7 @@ | |||
| 125 | pinctrl-single,pins = < | 125 | pinctrl-single,pins = < |
| 126 | OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ | 126 | OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ |
| 127 | OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ | 127 | OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ |
| 128 | OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ | 128 | OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ |
| 129 | OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ | 129 | OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ |
| 130 | OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ | 130 | OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ |
| 131 | >; | 131 | >; |
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index dc759a3028b7..5d5b620b7d9b 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi | |||
| @@ -14,6 +14,29 @@ | |||
| 14 | display0 = &hdmi0; | 14 | display0 = &hdmi0; |
| 15 | }; | 15 | }; |
| 16 | 16 | ||
| 17 | vmain: fixedregulator-vmain { | ||
| 18 | compatible = "regulator-fixed"; | ||
| 19 | regulator-name = "vmain"; | ||
| 20 | regulator-min-microvolt = <5000000>; | ||
| 21 | regulator-max-microvolt = <5000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | vsys_cobra: fixedregulator-vsys_cobra { | ||
| 25 | compatible = "regulator-fixed"; | ||
| 26 | regulator-name = "vsys_cobra"; | ||
| 27 | vin-supply = <&vmain>; | ||
| 28 | regulator-min-microvolt = <5000000>; | ||
| 29 | regulator-max-microvolt = <5000000>; | ||
| 30 | }; | ||
| 31 | |||
| 32 | vdds_1v8_main: fixedregulator-vdds_1v8_main { | ||
| 33 | compatible = "regulator-fixed"; | ||
| 34 | regulator-name = "vdds_1v8_main"; | ||
| 35 | vin-supply = <&smps7_reg>; | ||
| 36 | regulator-min-microvolt = <1800000>; | ||
| 37 | regulator-max-microvolt = <1800000>; | ||
| 38 | }; | ||
| 39 | |||
| 17 | vmmcsd_fixed: fixedregulator-mmcsd { | 40 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 18 | compatible = "regulator-fixed"; | 41 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "vmmcsd_fixed"; | 42 | regulator-name = "vmmcsd_fixed"; |
| @@ -309,7 +332,7 @@ | |||
| 309 | 332 | ||
| 310 | wlcore_irq_pin: pinmux_wlcore_irq_pin { | 333 | wlcore_irq_pin: pinmux_wlcore_irq_pin { |
| 311 | pinctrl-single,pins = < | 334 | pinctrl-single,pins = < |
| 312 | OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ | 335 | OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ |
| 313 | >; | 336 | >; |
| 314 | }; | 337 | }; |
| 315 | }; | 338 | }; |
| @@ -409,6 +432,26 @@ | |||
| 409 | 432 | ||
| 410 | ti,ldo6-vibrator; | 433 | ti,ldo6-vibrator; |
| 411 | 434 | ||
| 435 | smps123-in-supply = <&vsys_cobra>; | ||
| 436 | smps45-in-supply = <&vsys_cobra>; | ||
| 437 | smps6-in-supply = <&vsys_cobra>; | ||
| 438 | smps7-in-supply = <&vsys_cobra>; | ||
| 439 | smps8-in-supply = <&vsys_cobra>; | ||
| 440 | smps9-in-supply = <&vsys_cobra>; | ||
| 441 | smps10_out2-in-supply = <&vsys_cobra>; | ||
| 442 | smps10_out1-in-supply = <&vsys_cobra>; | ||
| 443 | ldo1-in-supply = <&vsys_cobra>; | ||
| 444 | ldo2-in-supply = <&vsys_cobra>; | ||
| 445 | ldo3-in-supply = <&vdds_1v8_main>; | ||
| 446 | ldo4-in-supply = <&vdds_1v8_main>; | ||
| 447 | ldo5-in-supply = <&vsys_cobra>; | ||
| 448 | ldo6-in-supply = <&vdds_1v8_main>; | ||
| 449 | ldo7-in-supply = <&vsys_cobra>; | ||
| 450 | ldo8-in-supply = <&vsys_cobra>; | ||
| 451 | ldo9-in-supply = <&vmmcsd_fixed>; | ||
| 452 | ldoln-in-supply = <&vsys_cobra>; | ||
| 453 | ldousb-in-supply = <&vsys_cobra>; | ||
| 454 | |||
| 412 | regulators { | 455 | regulators { |
| 413 | smps123_reg: smps123 { | 456 | smps123_reg: smps123 { |
| 414 | /* VDD_OPP_MPU */ | 457 | /* VDD_OPP_MPU */ |
| @@ -600,7 +643,8 @@ | |||
| 600 | pinctrl-0 = <&twl6040_pins>; | 643 | pinctrl-0 = <&twl6040_pins>; |
| 601 | 644 | ||
| 602 | interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ | 645 | interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ |
| 603 | ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ | 646 | |
| 647 | /* audpwron gpio defined in the board specific dts */ | ||
| 604 | 648 | ||
| 605 | vio-supply = <&smps7_reg>; | 649 | vio-supply = <&smps7_reg>; |
| 606 | v2v1-supply = <&smps9_reg>; | 650 | v2v1-supply = <&smps9_reg>; |
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 46ecb1dd3b5c..f75ce02fb398 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts | |||
| @@ -35,6 +35,22 @@ | |||
| 35 | }; | 35 | }; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | /* LDO4 is VPP1 - ball AD9 */ | ||
| 39 | &ldo4_reg { | ||
| 40 | regulator-min-microvolt = <2000000>; | ||
| 41 | regulator-max-microvolt = <2000000>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* | ||
| 45 | * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, | ||
| 46 | * VDDA_HDMI - ball AN25 | ||
| 47 | */ | ||
| 48 | &ldo7_reg { | ||
| 49 | status = "okay"; | ||
| 50 | regulator-min-microvolt = <1800000>; | ||
| 51 | regulator-max-microvolt = <1800000>; | ||
| 52 | }; | ||
| 53 | |||
| 38 | &omap5_pmx_core { | 54 | &omap5_pmx_core { |
| 39 | i2c4_pins: pinmux_i2c4_pins { | 55 | i2c4_pins: pinmux_i2c4_pins { |
| 40 | pinctrl-single,pins = < | 56 | pinctrl-single,pins = < |
| @@ -52,3 +68,13 @@ | |||
| 52 | <&gpio7 3 0>; /* 195, SDA */ | 68 | <&gpio7 3 0>; /* 195, SDA */ |
| 53 | }; | 69 | }; |
| 54 | 70 | ||
| 71 | &twl6040 { | ||
| 72 | ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ | ||
| 73 | }; | ||
| 74 | |||
| 75 | &twl6040_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ | ||
| 78 | OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ | ||
| 79 | >; | ||
| 80 | }; | ||
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 60b3fbb3bf07..a51e60518eb6 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts | |||
| @@ -51,3 +51,13 @@ | |||
| 51 | <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ | 51 | <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ |
| 52 | <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ | 52 | <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ |
| 53 | }; | 53 | }; |
| 54 | |||
| 55 | &twl6040 { | ||
| 56 | ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ | ||
| 57 | }; | ||
| 58 | |||
| 59 | &twl6040_pins { | ||
| 60 | pinctrl-single,pins = < | ||
| 61 | OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ | ||
| 62 | >; | ||
| 63 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index a3601e4c0a2e..b844473601d2 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | |||
| @@ -136,6 +136,7 @@ | |||
| 136 | &gmac1 { | 136 | &gmac1 { |
| 137 | status = "okay"; | 137 | status = "okay"; |
| 138 | phy-mode = "rgmii"; | 138 | phy-mode = "rgmii"; |
| 139 | phy-handle = <&phy1>; | ||
| 139 | 140 | ||
| 140 | snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; | 141 | snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; |
| 141 | snps,reset-active-low; | 142 | snps,reset-active-low; |
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index ad8ba10764a3..d294e82447a2 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi | |||
| @@ -24,18 +24,21 @@ | |||
| 24 | compatible = "shared-dma-pool"; | 24 | compatible = "shared-dma-pool"; |
| 25 | reg = <0x40000000 0x01000000>; | 25 | reg = <0x40000000 0x01000000>; |
| 26 | no-map; | 26 | no-map; |
| 27 | status = "disabled"; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gp1_reserved: rproc@41000000 { | 30 | gp1_reserved: rproc@41000000 { |
| 30 | compatible = "shared-dma-pool"; | 31 | compatible = "shared-dma-pool"; |
| 31 | reg = <0x41000000 0x01000000>; | 32 | reg = <0x41000000 0x01000000>; |
| 32 | no-map; | 33 | no-map; |
| 34 | status = "disabled"; | ||
| 33 | }; | 35 | }; |
| 34 | 36 | ||
| 35 | audio_reserved: rproc@42000000 { | 37 | audio_reserved: rproc@42000000 { |
| 36 | compatible = "shared-dma-pool"; | 38 | compatible = "shared-dma-pool"; |
| 37 | reg = <0x42000000 0x01000000>; | 39 | reg = <0x42000000 0x01000000>; |
| 38 | no-map; | 40 | no-map; |
| 41 | status = "disabled"; | ||
| 39 | }; | 42 | }; |
| 40 | 43 | ||
| 41 | dmu_reserved: rproc@43000000 { | 44 | dmu_reserved: rproc@43000000 { |
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 68b479b8772c..73c133f5e79c 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts | |||
| @@ -176,8 +176,6 @@ | |||
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | ®_dc1sw { | 178 | ®_dc1sw { |
| 179 | regulator-min-microvolt = <3000000>; | ||
| 180 | regulator-max-microvolt = <3000000>; | ||
| 181 | regulator-name = "vcc-lcd"; | 179 | regulator-name = "vcc-lcd"; |
| 182 | }; | 180 | }; |
| 183 | 181 | ||
diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 360adfb1e9ca..d6ad6196a768 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | |||
| @@ -135,8 +135,6 @@ | |||
| 135 | 135 | ||
| 136 | ®_dc1sw { | 136 | ®_dc1sw { |
| 137 | regulator-name = "vcc-lcd-usb2"; | 137 | regulator-name = "vcc-lcd-usb2"; |
| 138 | regulator-min-microvolt = <3000000>; | ||
| 139 | regulator-max-microvolt = <3000000>; | ||
| 140 | }; | 138 | }; |
| 141 | 139 | ||
| 142 | ®_dc5ldo { | 140 | ®_dc5ldo { |
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 10f49ab5328e..47195e8690b4 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig | |||
| @@ -82,6 +82,7 @@ CONFIG_TOUCHSCREEN_MMS114=y | |||
| 82 | CONFIG_INPUT_MISC=y | 82 | CONFIG_INPUT_MISC=y |
| 83 | CONFIG_INPUT_MAX77693_HAPTIC=y | 83 | CONFIG_INPUT_MAX77693_HAPTIC=y |
| 84 | CONFIG_INPUT_MAX8997_HAPTIC=y | 84 | CONFIG_INPUT_MAX8997_HAPTIC=y |
| 85 | CONFIG_KEYBOARD_SAMSUNG=y | ||
| 85 | CONFIG_SERIAL_8250=y | 86 | CONFIG_SERIAL_8250=y |
| 86 | CONFIG_SERIAL_SAMSUNG=y | 87 | CONFIG_SERIAL_SAMSUNG=y |
| 87 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | 88 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 8f857564657f..8a5fff1b7f6f 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig | |||
| @@ -264,6 +264,7 @@ CONFIG_KEYBOARD_TEGRA=y | |||
| 264 | CONFIG_KEYBOARD_SPEAR=y | 264 | CONFIG_KEYBOARD_SPEAR=y |
| 265 | CONFIG_KEYBOARD_ST_KEYSCAN=y | 265 | CONFIG_KEYBOARD_ST_KEYSCAN=y |
| 266 | CONFIG_KEYBOARD_CROS_EC=m | 266 | CONFIG_KEYBOARD_CROS_EC=m |
| 267 | CONFIG_KEYBOARD_SAMSUNG=m | ||
| 267 | CONFIG_MOUSE_PS2_ELANTECH=y | 268 | CONFIG_MOUSE_PS2_ELANTECH=y |
| 268 | CONFIG_MOUSE_CYAPA=m | 269 | CONFIG_MOUSE_CYAPA=m |
| 269 | CONFIG_MOUSE_ELAN_I2C=y | 270 | CONFIG_MOUSE_ELAN_I2C=y |
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index df90bc59bfce..861521606c6d 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -486,7 +486,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { | |||
| 486 | 486 | ||
| 487 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) | 487 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
| 488 | { | 488 | { |
| 489 | trace_ipi_raise(target, ipi_types[ipinr]); | 489 | trace_ipi_raise_rcuidle(target, ipi_types[ipinr]); |
| 490 | __smp_cross_call(target, ipinr); | 490 | __smp_cross_call(target, ipinr); |
| 491 | } | 491 | } |
| 492 | 492 | ||
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e65aa7d11b20..20dcf6e904b2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig | |||
| @@ -61,7 +61,6 @@ config ARCH_EXYNOS4 | |||
| 61 | select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 | 61 | select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 |
| 62 | select CPU_EXYNOS4210 | 62 | select CPU_EXYNOS4210 |
| 63 | select GIC_NON_BANKED | 63 | select GIC_NON_BANKED |
| 64 | select KEYBOARD_SAMSUNG if INPUT_KEYBOARD | ||
| 65 | select MIGHT_HAVE_CACHE_L2X0 | 64 | select MIGHT_HAVE_CACHE_L2X0 |
| 66 | help | 65 | help |
| 67 | Samsung EXYNOS4 (Cortex-A9) SoC based systems | 66 | Samsung EXYNOS4 (Cortex-A9) SoC based systems |
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index a38b16b69923..b56de4b8cdf2 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c | |||
| @@ -46,7 +46,7 @@ static int ksz8081_phy_fixup(struct phy_device *dev) | |||
| 46 | static void __init imx6ul_enet_phy_init(void) | 46 | static void __init imx6ul_enet_phy_init(void) |
| 47 | { | 47 | { |
| 48 | if (IS_BUILTIN(CONFIG_PHYLIB)) | 48 | if (IS_BUILTIN(CONFIG_PHYLIB)) |
| 49 | phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, | 49 | phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, |
| 50 | ksz8081_phy_fixup); | 50 | ksz8081_phy_fixup); |
| 51 | } | 51 | } |
| 52 | 52 | ||
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index 5d7fb596bf4a..bf608441b357 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S | |||
| @@ -43,8 +43,8 @@ | |||
| 43 | #define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) | 43 | #define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) |
| 44 | 44 | ||
| 45 | /* IRQ handler register bitmasks */ | 45 | /* IRQ handler register bitmasks */ |
| 46 | #define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) | 46 | #define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ) |
| 47 | #define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) | 47 | #define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1) |
| 48 | 48 | ||
| 49 | /* Driver buffer byte offsets */ | 49 | /* Driver buffer byte offsets */ |
| 50 | #define BUF_MASK (FIQ_MASK * 4) | 50 | #define BUF_MASK (FIQ_MASK * 4) |
| @@ -110,7 +110,7 @@ ENTRY(qwerty_fiqin_start) | |||
| 110 | mov r8, #2 @ reset FIQ agreement | 110 | mov r8, #2 @ reset FIQ agreement |
| 111 | str r8, [r12, #IRQ_CONTROL_REG_OFFSET] | 111 | str r8, [r12, #IRQ_CONTROL_REG_OFFSET] |
| 112 | 112 | ||
| 113 | cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? | 113 | cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt? |
| 114 | beq gpio @ yes - process it | 114 | beq gpio @ yes - process it |
| 115 | 115 | ||
| 116 | mov r8, #1 | 116 | mov r8, #1 |
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index d1f12095f315..ec760ae2f917 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c | |||
| @@ -109,7 +109,8 @@ void __init ams_delta_init_fiq(void) | |||
| 109 | * Since no set_type() method is provided by OMAP irq chip, | 109 | * Since no set_type() method is provided by OMAP irq chip, |
| 110 | * switch to edge triggered interrupt type manually. | 110 | * switch to edge triggered interrupt type manually. |
| 111 | */ | 111 | */ |
| 112 | offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; | 112 | offset = IRQ_ILR0_REG_OFFSET + |
| 113 | ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; | ||
| 113 | val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); | 114 | val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); |
| 114 | omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); | 115 | omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); |
| 115 | 116 | ||
| @@ -149,7 +150,7 @@ void __init ams_delta_init_fiq(void) | |||
| 149 | /* | 150 | /* |
| 150 | * Redirect GPIO interrupts to FIQ | 151 | * Redirect GPIO interrupts to FIQ |
| 151 | */ | 152 | */ |
| 152 | offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; | 153 | offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; |
| 153 | val = omap_readl(OMAP_IH1_BASE + offset) | 1; | 154 | val = omap_readl(OMAP_IH1_BASE + offset) | 1; |
| 154 | omap_writel(val, OMAP_IH1_BASE + offset); | 155 | omap_writel(val, OMAP_IH1_BASE + offset); |
| 155 | } | 156 | } |
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index adb5e7649659..6dfc3e1210a3 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | #ifndef __AMS_DELTA_FIQ_H | 14 | #ifndef __AMS_DELTA_FIQ_H |
| 15 | #define __AMS_DELTA_FIQ_H | 15 | #define __AMS_DELTA_FIQ_H |
| 16 | 16 | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | |||
| 17 | /* | 19 | /* |
| 18 | * Interrupt number used for passing control from FIQ to IRQ. | 20 | * Interrupt number used for passing control from FIQ to IRQ. |
| 19 | * IRQ12, described as reserved, has been selected. | 21 | * IRQ12, described as reserved, has been selected. |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 0517f0c1581a..1a648e9dfaa0 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -17,6 +17,7 @@ config ARCH_OMAP3 | |||
| 17 | select PM_OPP if PM | 17 | select PM_OPP if PM |
| 18 | select PM if CPU_IDLE | 18 | select PM if CPU_IDLE |
| 19 | select SOC_HAS_OMAP2_SDRC | 19 | select SOC_HAS_OMAP2_SDRC |
| 20 | select ARM_ERRATA_430973 | ||
| 20 | 21 | ||
| 21 | config ARCH_OMAP4 | 22 | config ARCH_OMAP4 |
| 22 | bool "TI OMAP4" | 23 | bool "TI OMAP4" |
| @@ -36,6 +37,7 @@ config ARCH_OMAP4 | |||
| 36 | select PM if CPU_IDLE | 37 | select PM if CPU_IDLE |
| 37 | select ARM_ERRATA_754322 | 38 | select ARM_ERRATA_754322 |
| 38 | select ARM_ERRATA_775420 | 39 | select ARM_ERRATA_775420 |
| 40 | select OMAP_INTERCONNECT | ||
| 39 | 41 | ||
| 40 | config SOC_OMAP5 | 42 | config SOC_OMAP5 |
| 41 | bool "TI OMAP5" | 43 | bool "TI OMAP5" |
| @@ -67,6 +69,8 @@ config SOC_AM43XX | |||
| 67 | select HAVE_ARM_SCU | 69 | select HAVE_ARM_SCU |
| 68 | select GENERIC_CLOCKEVENTS_BROADCAST | 70 | select GENERIC_CLOCKEVENTS_BROADCAST |
| 69 | select HAVE_ARM_TWD | 71 | select HAVE_ARM_TWD |
| 72 | select ARM_ERRATA_754322 | ||
| 73 | select ARM_ERRATA_775420 | ||
| 70 | 74 | ||
| 71 | config SOC_DRA7XX | 75 | config SOC_DRA7XX |
| 72 | bool "TI DRA7XX" | 76 | bool "TI DRA7XX" |
| @@ -240,4 +244,12 @@ endmenu | |||
| 240 | 244 | ||
| 241 | endif | 245 | endif |
| 242 | 246 | ||
| 247 | config OMAP5_ERRATA_801819 | ||
| 248 | bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" | ||
| 249 | depends on SOC_OMAP5 || SOC_DRA7XX | ||
| 250 | help | ||
| 251 | A livelock can occur in the L2 cache arbitration that might prevent | ||
| 252 | a snoop from completing. Under certain conditions this can cause the | ||
| 253 | system to deadlock. | ||
| 254 | |||
| 243 | endmenu | 255 | endmenu |
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index af2851fbcdf0..bae263fba640 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | 46 | ||
| 47 | #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 | 47 | #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 |
| 48 | #define OMAP5_MON_AMBA_IF_INDEX 0x108 | 48 | #define OMAP5_MON_AMBA_IF_INDEX 0x108 |
| 49 | #define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107 | ||
| 49 | 50 | ||
| 50 | /* Secure PPA(Primary Protected Application) APIs */ | 51 | /* Secure PPA(Primary Protected Application) APIs */ |
| 51 | #define OMAP4_PPA_L2_POR_INDEX 0x23 | 52 | #define OMAP4_PPA_L2_POR_INDEX 0x23 |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index c625cc10d9f9..8cd1de914ee4 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
| @@ -50,6 +50,39 @@ void __iomem *omap4_get_scu_base(void) | |||
| 50 | return scu_base; | 50 | return scu_base; |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | #ifdef CONFIG_OMAP5_ERRATA_801819 | ||
| 54 | void omap5_erratum_workaround_801819(void) | ||
| 55 | { | ||
| 56 | u32 acr, revidr; | ||
| 57 | u32 acr_mask; | ||
| 58 | |||
| 59 | /* REVIDR[3] indicates erratum fix available on silicon */ | ||
| 60 | asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr)); | ||
| 61 | if (revidr & (0x1 << 3)) | ||
| 62 | return; | ||
| 63 | |||
| 64 | asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); | ||
| 65 | /* | ||
| 66 | * BIT(27) - Disables streaming. All write-allocate lines allocate in | ||
| 67 | * the L1 or L2 cache. | ||
| 68 | * BIT(25) - Disables streaming. All write-allocate lines allocate in | ||
| 69 | * the L1 cache. | ||
| 70 | */ | ||
| 71 | acr_mask = (0x3 << 25) | (0x3 << 27); | ||
| 72 | /* do we already have it done.. if yes, skip expensive smc */ | ||
| 73 | if ((acr & acr_mask) == acr_mask) | ||
| 74 | return; | ||
| 75 | |||
| 76 | acr |= acr_mask; | ||
| 77 | omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); | ||
| 78 | |||
| 79 | pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", | ||
| 80 | __func__, smp_processor_id()); | ||
| 81 | } | ||
| 82 | #else | ||
| 83 | static inline void omap5_erratum_workaround_801819(void) { } | ||
| 84 | #endif | ||
| 85 | |||
| 53 | static void omap4_secondary_init(unsigned int cpu) | 86 | static void omap4_secondary_init(unsigned int cpu) |
| 54 | { | 87 | { |
| 55 | /* | 88 | /* |
| @@ -64,12 +97,15 @@ static void omap4_secondary_init(unsigned int cpu) | |||
| 64 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, | 97 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, |
| 65 | 4, 0, 0, 0, 0, 0); | 98 | 4, 0, 0, 0, 0, 0); |
| 66 | 99 | ||
| 67 | /* | 100 | if (soc_is_omap54xx() || soc_is_dra7xx()) { |
| 68 | * Configure the CNTFRQ register for the secondary cpu's which | 101 | /* |
| 69 | * indicates the frequency of the cpu local timers. | 102 | * Configure the CNTFRQ register for the secondary cpu's which |
| 70 | */ | 103 | * indicates the frequency of the cpu local timers. |
| 71 | if (soc_is_omap54xx() || soc_is_dra7xx()) | 104 | */ |
| 72 | set_cntfreq(); | 105 | set_cntfreq(); |
| 106 | /* Configure ACR to disable streaming WA for 801819 */ | ||
| 107 | omap5_erratum_workaround_801819(); | ||
| 108 | } | ||
| 73 | 109 | ||
| 74 | /* | 110 | /* |
| 75 | * Synchronise with the boot thread. | 111 | * Synchronise with the boot thread. |
| @@ -218,6 +254,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) | |||
| 218 | 254 | ||
| 219 | if (cpu_is_omap446x()) | 255 | if (cpu_is_omap446x()) |
| 220 | startup_addr = omap4460_secondary_startup; | 256 | startup_addr = omap4460_secondary_startup; |
| 257 | if (soc_is_dra74x() || soc_is_omap54xx()) | ||
| 258 | omap5_erratum_workaround_801819(); | ||
| 221 | 259 | ||
| 222 | /* | 260 | /* |
| 223 | * Write the address of secondary startup routine into the | 261 | * Write the address of secondary startup routine into the |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 78af6d8cf2e2..daf2753de7aa 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
| @@ -186,8 +186,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) | |||
| 186 | trace_state = (PWRDM_TRACE_STATES_FLAG | | 186 | trace_state = (PWRDM_TRACE_STATES_FLAG | |
| 187 | ((next & OMAP_POWERSTATE_MASK) << 8) | | 187 | ((next & OMAP_POWERSTATE_MASK) << 8) | |
| 188 | ((prev & OMAP_POWERSTATE_MASK) << 0)); | 188 | ((prev & OMAP_POWERSTATE_MASK) << 0)); |
| 189 | trace_power_domain_target(pwrdm->name, trace_state, | 189 | trace_power_domain_target_rcuidle(pwrdm->name, |
| 190 | smp_processor_id()); | 190 | trace_state, |
| 191 | smp_processor_id()); | ||
| 191 | } | 192 | } |
| 192 | break; | 193 | break; |
| 193 | default: | 194 | default: |
| @@ -523,8 +524,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 523 | 524 | ||
| 524 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { | 525 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { |
| 525 | /* Trace the pwrdm desired target state */ | 526 | /* Trace the pwrdm desired target state */ |
| 526 | trace_power_domain_target(pwrdm->name, pwrst, | 527 | trace_power_domain_target_rcuidle(pwrdm->name, pwrst, |
| 527 | smp_processor_id()); | 528 | smp_processor_id()); |
| 528 | /* Program the pwrdm desired target state */ | 529 | /* Program the pwrdm desired target state */ |
| 529 | ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); | 530 | ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); |
| 530 | } | 531 | } |
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 0ec2d00f4237..eb350a673133 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c | |||
| @@ -36,14 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = { | |||
| 36 | .prcm_offs = DRA7XX_PRM_IVA_INST, | 36 | .prcm_offs = DRA7XX_PRM_IVA_INST, |
| 37 | .prcm_partition = DRA7XX_PRM_PARTITION, | 37 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 38 | .pwrsts = PWRSTS_OFF_ON, | 38 | .pwrsts = PWRSTS_OFF_ON, |
| 39 | .pwrsts_logic_ret = PWRSTS_OFF, | ||
| 40 | .banks = 4, | 39 | .banks = 4, |
| 41 | .pwrsts_mem_ret = { | ||
| 42 | [0] = PWRSTS_OFF_RET, /* hwa_mem */ | ||
| 43 | [1] = PWRSTS_OFF_RET, /* sl2_mem */ | ||
| 44 | [2] = PWRSTS_OFF_RET, /* tcm1_mem */ | ||
| 45 | [3] = PWRSTS_OFF_RET, /* tcm2_mem */ | ||
| 46 | }, | ||
| 47 | .pwrsts_mem_on = { | 40 | .pwrsts_mem_on = { |
| 48 | [0] = PWRSTS_ON, /* hwa_mem */ | 41 | [0] = PWRSTS_ON, /* hwa_mem */ |
| 49 | [1] = PWRSTS_ON, /* sl2_mem */ | 42 | [1] = PWRSTS_ON, /* sl2_mem */ |
| @@ -76,12 +69,7 @@ static struct powerdomain ipu_7xx_pwrdm = { | |||
| 76 | .prcm_offs = DRA7XX_PRM_IPU_INST, | 69 | .prcm_offs = DRA7XX_PRM_IPU_INST, |
| 77 | .prcm_partition = DRA7XX_PRM_PARTITION, | 70 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 78 | .pwrsts = PWRSTS_OFF_ON, | 71 | .pwrsts = PWRSTS_OFF_ON, |
| 79 | .pwrsts_logic_ret = PWRSTS_OFF, | ||
| 80 | .banks = 2, | 72 | .banks = 2, |
| 81 | .pwrsts_mem_ret = { | ||
| 82 | [0] = PWRSTS_OFF_RET, /* aessmem */ | ||
| 83 | [1] = PWRSTS_OFF_RET, /* periphmem */ | ||
| 84 | }, | ||
| 85 | .pwrsts_mem_on = { | 73 | .pwrsts_mem_on = { |
| 86 | [0] = PWRSTS_ON, /* aessmem */ | 74 | [0] = PWRSTS_ON, /* aessmem */ |
| 87 | [1] = PWRSTS_ON, /* periphmem */ | 75 | [1] = PWRSTS_ON, /* periphmem */ |
| @@ -95,11 +83,7 @@ static struct powerdomain dss_7xx_pwrdm = { | |||
| 95 | .prcm_offs = DRA7XX_PRM_DSS_INST, | 83 | .prcm_offs = DRA7XX_PRM_DSS_INST, |
| 96 | .prcm_partition = DRA7XX_PRM_PARTITION, | 84 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 97 | .pwrsts = PWRSTS_OFF_ON, | 85 | .pwrsts = PWRSTS_OFF_ON, |
| 98 | .pwrsts_logic_ret = PWRSTS_OFF, | ||
| 99 | .banks = 1, | 86 | .banks = 1, |
| 100 | .pwrsts_mem_ret = { | ||
| 101 | [0] = PWRSTS_OFF_RET, /* dss_mem */ | ||
| 102 | }, | ||
| 103 | .pwrsts_mem_on = { | 87 | .pwrsts_mem_on = { |
| 104 | [0] = PWRSTS_ON, /* dss_mem */ | 88 | [0] = PWRSTS_ON, /* dss_mem */ |
| 105 | }, | 89 | }, |
| @@ -111,13 +95,8 @@ static struct powerdomain l4per_7xx_pwrdm = { | |||
| 111 | .name = "l4per_pwrdm", | 95 | .name = "l4per_pwrdm", |
| 112 | .prcm_offs = DRA7XX_PRM_L4PER_INST, | 96 | .prcm_offs = DRA7XX_PRM_L4PER_INST, |
| 113 | .prcm_partition = DRA7XX_PRM_PARTITION, | 97 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 114 | .pwrsts = PWRSTS_RET_ON, | 98 | .pwrsts = PWRSTS_ON, |
| 115 | .pwrsts_logic_ret = PWRSTS_RET, | ||
| 116 | .banks = 2, | 99 | .banks = 2, |
| 117 | .pwrsts_mem_ret = { | ||
| 118 | [0] = PWRSTS_OFF_RET, /* nonretained_bank */ | ||
| 119 | [1] = PWRSTS_OFF_RET, /* retained_bank */ | ||
| 120 | }, | ||
| 121 | .pwrsts_mem_on = { | 100 | .pwrsts_mem_on = { |
| 122 | [0] = PWRSTS_ON, /* nonretained_bank */ | 101 | [0] = PWRSTS_ON, /* nonretained_bank */ |
| 123 | [1] = PWRSTS_ON, /* retained_bank */ | 102 | [1] = PWRSTS_ON, /* retained_bank */ |
| @@ -132,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = { | |||
| 132 | .prcm_partition = DRA7XX_PRM_PARTITION, | 111 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 133 | .pwrsts = PWRSTS_OFF_ON, | 112 | .pwrsts = PWRSTS_OFF_ON, |
| 134 | .banks = 1, | 113 | .banks = 1, |
| 135 | .pwrsts_mem_ret = { | ||
| 136 | [0] = PWRSTS_OFF_RET, /* gpu_mem */ | ||
| 137 | }, | ||
| 138 | .pwrsts_mem_on = { | 114 | .pwrsts_mem_on = { |
| 139 | [0] = PWRSTS_ON, /* gpu_mem */ | 115 | [0] = PWRSTS_ON, /* gpu_mem */ |
| 140 | }, | 116 | }, |
| @@ -148,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = { | |||
| 148 | .prcm_partition = DRA7XX_PRM_PARTITION, | 124 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 149 | .pwrsts = PWRSTS_ON, | 125 | .pwrsts = PWRSTS_ON, |
| 150 | .banks = 1, | 126 | .banks = 1, |
| 151 | .pwrsts_mem_ret = { | ||
| 152 | }, | ||
| 153 | .pwrsts_mem_on = { | 127 | .pwrsts_mem_on = { |
| 154 | [0] = PWRSTS_ON, /* wkup_bank */ | 128 | [0] = PWRSTS_ON, /* wkup_bank */ |
| 155 | }, | 129 | }, |
| @@ -161,15 +135,7 @@ static struct powerdomain core_7xx_pwrdm = { | |||
| 161 | .prcm_offs = DRA7XX_PRM_CORE_INST, | 135 | .prcm_offs = DRA7XX_PRM_CORE_INST, |
| 162 | .prcm_partition = DRA7XX_PRM_PARTITION, | 136 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 163 | .pwrsts = PWRSTS_ON, | 137 | .pwrsts = PWRSTS_ON, |
| 164 | .pwrsts_logic_ret = PWRSTS_RET, | ||
| 165 | .banks = 5, | 138 | .banks = 5, |
| 166 | .pwrsts_mem_ret = { | ||
| 167 | [0] = PWRSTS_OFF_RET, /* core_nret_bank */ | ||
| 168 | [1] = PWRSTS_OFF_RET, /* core_ocmram */ | ||
| 169 | [2] = PWRSTS_OFF_RET, /* core_other_bank */ | ||
| 170 | [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ | ||
| 171 | [4] = PWRSTS_OFF_RET, /* ipu_unicache */ | ||
| 172 | }, | ||
| 173 | .pwrsts_mem_on = { | 139 | .pwrsts_mem_on = { |
| 174 | [0] = PWRSTS_ON, /* core_nret_bank */ | 140 | [0] = PWRSTS_ON, /* core_nret_bank */ |
| 175 | [1] = PWRSTS_ON, /* core_ocmram */ | 141 | [1] = PWRSTS_ON, /* core_ocmram */ |
| @@ -226,11 +192,7 @@ static struct powerdomain vpe_7xx_pwrdm = { | |||
| 226 | .prcm_offs = DRA7XX_PRM_VPE_INST, | 192 | .prcm_offs = DRA7XX_PRM_VPE_INST, |
| 227 | .prcm_partition = DRA7XX_PRM_PARTITION, | 193 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 228 | .pwrsts = PWRSTS_OFF_ON, | 194 | .pwrsts = PWRSTS_OFF_ON, |
| 229 | .pwrsts_logic_ret = PWRSTS_OFF, | ||
| 230 | .banks = 1, | 195 | .banks = 1, |
| 231 | .pwrsts_mem_ret = { | ||
| 232 | [0] = PWRSTS_OFF_RET, /* vpe_bank */ | ||
| 233 | }, | ||
| 234 | .pwrsts_mem_on = { | 196 | .pwrsts_mem_on = { |
| 235 | [0] = PWRSTS_ON, /* vpe_bank */ | 197 | [0] = PWRSTS_ON, /* vpe_bank */ |
| 236 | }, | 198 | }, |
| @@ -260,14 +222,8 @@ static struct powerdomain l3init_7xx_pwrdm = { | |||
| 260 | .name = "l3init_pwrdm", | 222 | .name = "l3init_pwrdm", |
| 261 | .prcm_offs = DRA7XX_PRM_L3INIT_INST, | 223 | .prcm_offs = DRA7XX_PRM_L3INIT_INST, |
| 262 | .prcm_partition = DRA7XX_PRM_PARTITION, | 224 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 263 | .pwrsts = PWRSTS_RET_ON, | 225 | .pwrsts = PWRSTS_ON, |
| 264 | .pwrsts_logic_ret = PWRSTS_RET, | ||
| 265 | .banks = 3, | 226 | .banks = 3, |
| 266 | .pwrsts_mem_ret = { | ||
| 267 | [0] = PWRSTS_OFF_RET, /* gmac_bank */ | ||
| 268 | [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ | ||
| 269 | [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ | ||
| 270 | }, | ||
| 271 | .pwrsts_mem_on = { | 227 | .pwrsts_mem_on = { |
| 272 | [0] = PWRSTS_ON, /* gmac_bank */ | 228 | [0] = PWRSTS_ON, /* gmac_bank */ |
| 273 | [1] = PWRSTS_ON, /* l3init_bank1 */ | 229 | [1] = PWRSTS_ON, /* l3init_bank1 */ |
| @@ -283,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = { | |||
| 283 | .prcm_partition = DRA7XX_PRM_PARTITION, | 239 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 284 | .pwrsts = PWRSTS_OFF_ON, | 240 | .pwrsts = PWRSTS_OFF_ON, |
| 285 | .banks = 1, | 241 | .banks = 1, |
| 286 | .pwrsts_mem_ret = { | ||
| 287 | [0] = PWRSTS_OFF_RET, /* eve3_bank */ | ||
| 288 | }, | ||
| 289 | .pwrsts_mem_on = { | 242 | .pwrsts_mem_on = { |
| 290 | [0] = PWRSTS_ON, /* eve3_bank */ | 243 | [0] = PWRSTS_ON, /* eve3_bank */ |
| 291 | }, | 244 | }, |
| @@ -299,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = { | |||
| 299 | .prcm_partition = DRA7XX_PRM_PARTITION, | 252 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 300 | .pwrsts = PWRSTS_OFF_ON, | 253 | .pwrsts = PWRSTS_OFF_ON, |
| 301 | .banks = 1, | 254 | .banks = 1, |
| 302 | .pwrsts_mem_ret = { | ||
| 303 | [0] = PWRSTS_OFF_RET, /* emu_bank */ | ||
| 304 | }, | ||
| 305 | .pwrsts_mem_on = { | 255 | .pwrsts_mem_on = { |
| 306 | [0] = PWRSTS_ON, /* emu_bank */ | 256 | [0] = PWRSTS_ON, /* emu_bank */ |
| 307 | }, | 257 | }, |
| @@ -314,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = { | |||
| 314 | .prcm_partition = DRA7XX_PRM_PARTITION, | 264 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 315 | .pwrsts = PWRSTS_OFF_ON, | 265 | .pwrsts = PWRSTS_OFF_ON, |
| 316 | .banks = 3, | 266 | .banks = 3, |
| 317 | .pwrsts_mem_ret = { | ||
| 318 | [0] = PWRSTS_OFF_RET, /* dsp2_edma */ | ||
| 319 | [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ | ||
| 320 | [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ | ||
| 321 | }, | ||
| 322 | .pwrsts_mem_on = { | 267 | .pwrsts_mem_on = { |
| 323 | [0] = PWRSTS_ON, /* dsp2_edma */ | 268 | [0] = PWRSTS_ON, /* dsp2_edma */ |
| 324 | [1] = PWRSTS_ON, /* dsp2_l1 */ | 269 | [1] = PWRSTS_ON, /* dsp2_l1 */ |
| @@ -334,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = { | |||
| 334 | .prcm_partition = DRA7XX_PRM_PARTITION, | 279 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 335 | .pwrsts = PWRSTS_OFF_ON, | 280 | .pwrsts = PWRSTS_OFF_ON, |
| 336 | .banks = 3, | 281 | .banks = 3, |
| 337 | .pwrsts_mem_ret = { | ||
| 338 | [0] = PWRSTS_OFF_RET, /* dsp1_edma */ | ||
| 339 | [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ | ||
| 340 | [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ | ||
| 341 | }, | ||
| 342 | .pwrsts_mem_on = { | 282 | .pwrsts_mem_on = { |
| 343 | [0] = PWRSTS_ON, /* dsp1_edma */ | 283 | [0] = PWRSTS_ON, /* dsp1_edma */ |
| 344 | [1] = PWRSTS_ON, /* dsp1_l1 */ | 284 | [1] = PWRSTS_ON, /* dsp1_l1 */ |
| @@ -354,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = { | |||
| 354 | .prcm_partition = DRA7XX_PRM_PARTITION, | 294 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 355 | .pwrsts = PWRSTS_OFF_ON, | 295 | .pwrsts = PWRSTS_OFF_ON, |
| 356 | .banks = 1, | 296 | .banks = 1, |
| 357 | .pwrsts_mem_ret = { | ||
| 358 | [0] = PWRSTS_OFF_RET, /* vip_bank */ | ||
| 359 | }, | ||
| 360 | .pwrsts_mem_on = { | 297 | .pwrsts_mem_on = { |
| 361 | [0] = PWRSTS_ON, /* vip_bank */ | 298 | [0] = PWRSTS_ON, /* vip_bank */ |
| 362 | }, | 299 | }, |
| @@ -370,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = { | |||
| 370 | .prcm_partition = DRA7XX_PRM_PARTITION, | 307 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 371 | .pwrsts = PWRSTS_OFF_ON, | 308 | .pwrsts = PWRSTS_OFF_ON, |
| 372 | .banks = 1, | 309 | .banks = 1, |
| 373 | .pwrsts_mem_ret = { | ||
| 374 | [0] = PWRSTS_OFF_RET, /* eve4_bank */ | ||
| 375 | }, | ||
| 376 | .pwrsts_mem_on = { | 310 | .pwrsts_mem_on = { |
| 377 | [0] = PWRSTS_ON, /* eve4_bank */ | 311 | [0] = PWRSTS_ON, /* eve4_bank */ |
| 378 | }, | 312 | }, |
| @@ -386,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = { | |||
| 386 | .prcm_partition = DRA7XX_PRM_PARTITION, | 320 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 387 | .pwrsts = PWRSTS_OFF_ON, | 321 | .pwrsts = PWRSTS_OFF_ON, |
| 388 | .banks = 1, | 322 | .banks = 1, |
| 389 | .pwrsts_mem_ret = { | ||
| 390 | [0] = PWRSTS_OFF_RET, /* eve2_bank */ | ||
| 391 | }, | ||
| 392 | .pwrsts_mem_on = { | 323 | .pwrsts_mem_on = { |
| 393 | [0] = PWRSTS_ON, /* eve2_bank */ | 324 | [0] = PWRSTS_ON, /* eve2_bank */ |
| 394 | }, | 325 | }, |
| @@ -402,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = { | |||
| 402 | .prcm_partition = DRA7XX_PRM_PARTITION, | 333 | .prcm_partition = DRA7XX_PRM_PARTITION, |
| 403 | .pwrsts = PWRSTS_OFF_ON, | 334 | .pwrsts = PWRSTS_OFF_ON, |
| 404 | .banks = 1, | 335 | .banks = 1, |
| 405 | .pwrsts_mem_ret = { | ||
| 406 | [0] = PWRSTS_OFF_RET, /* eve1_bank */ | ||
| 407 | }, | ||
| 408 | .pwrsts_mem_on = { | 336 | .pwrsts_mem_on = { |
| 409 | [0] = PWRSTS_ON, /* eve1_bank */ | 337 | [0] = PWRSTS_ON, /* eve1_bank */ |
| 410 | }, | 338 | }, |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 5b385bb8aff9..cb9497a20fb3 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -496,8 +496,7 @@ void __init omap_init_time(void) | |||
| 496 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", | 496 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", |
| 497 | 2, "timer_sys_ck", NULL, false); | 497 | 2, "timer_sys_ck", NULL, false); |
| 498 | 498 | ||
| 499 | if (of_have_populated_dt()) | 499 | clocksource_probe(); |
| 500 | clocksource_probe(); | ||
| 501 | } | 500 | } |
| 502 | 501 | ||
| 503 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) | 502 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) |
| @@ -505,6 +504,8 @@ void __init omap3_secure_sync32k_timer_init(void) | |||
| 505 | { | 504 | { |
| 506 | __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", | 505 | __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", |
| 507 | 2, "timer_sys_ck", NULL, false); | 506 | 2, "timer_sys_ck", NULL, false); |
| 507 | |||
| 508 | clocksource_probe(); | ||
| 508 | } | 509 | } |
| 509 | #endif /* CONFIG_ARCH_OMAP3 */ | 510 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 510 | 511 | ||
| @@ -513,6 +514,8 @@ void __init omap3_gptimer_timer_init(void) | |||
| 513 | { | 514 | { |
| 514 | __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, | 515 | __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, |
| 515 | 1, "timer_sys_ck", "ti,timer-alwon", true); | 516 | 1, "timer_sys_ck", "ti,timer-alwon", true); |
| 517 | |||
| 518 | clocksource_probe(); | ||
| 516 | } | 519 | } |
| 517 | #endif | 520 | #endif |
| 518 | 521 | ||
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 84baa16f4c0b..e93aa6734147 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
| @@ -68,7 +68,7 @@ | |||
| 68 | #include <linux/platform_data/asoc-s3c.h> | 68 | #include <linux/platform_data/asoc-s3c.h> |
| 69 | #include <linux/platform_data/spi-s3c64xx.h> | 69 | #include <linux/platform_data/spi-s3c64xx.h> |
| 70 | 70 | ||
| 71 | static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); | 71 | #define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) })) |
| 72 | 72 | ||
| 73 | /* AC97 */ | 73 | /* AC97 */ |
| 74 | #ifdef CONFIG_CPU_S3C2440 | 74 | #ifdef CONFIG_CPU_S3C2440 |
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 3a4e9a2ab313..fbafa24cd533 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi | |||
| @@ -125,7 +125,7 @@ | |||
| 125 | #size-cells = <1>; | 125 | #size-cells = <1>; |
| 126 | #interrupts-cells = <3>; | 126 | #interrupts-cells = <3>; |
| 127 | 127 | ||
| 128 | compatible = "arm,amba-bus"; | 128 | compatible = "simple-bus"; |
| 129 | interrupt-parent = <&gic>; | 129 | interrupt-parent = <&gic>; |
| 130 | ranges; | 130 | ranges; |
| 131 | 131 | ||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 46f325a143b0..d7f8e06910bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi | |||
| @@ -163,7 +163,7 @@ | |||
| 163 | }; | 163 | }; |
| 164 | 164 | ||
| 165 | amba { | 165 | amba { |
| 166 | compatible = "arm,amba-bus"; | 166 | compatible = "simple-bus"; |
| 167 | #address-cells = <2>; | 167 | #address-cells = <2>; |
| 168 | #size-cells = <2>; | 168 | #size-cells = <2>; |
| 169 | ranges; | 169 | ranges; |
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index af4884ba6b7c..15508df24e5d 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c | |||
| @@ -398,7 +398,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |||
| 398 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | 398 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, |
| 399 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | 399 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); |
| 400 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | 400 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, |
| 401 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | 401 | GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); |
| 402 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | 402 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, |
| 403 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | 403 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, |
| 404 | p->cycle2cyclesamecsen); | 404 | p->cycle2cyclesamecsen); |
