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-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/plat-stmp3xxx/Kconfig7
-rw-r--r--arch/arm/plat-stmp3xxx/Makefile5
-rw-r--r--arch/arm/plat-stmp3xxx/clock.c1134
-rw-r--r--arch/arm/plat-stmp3xxx/clock.h61
-rw-r--r--arch/arm/plat-stmp3xxx/core.c128
-rw-r--r--arch/arm/plat-stmp3xxx/devices.c389
-rw-r--r--arch/arm/plat-stmp3xxx/dma.c464
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/clkdev.h18
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/cputype.h33
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S39
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h153
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpio.h28
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpmi.h12
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/hardware.h32
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/io.h25
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/memory.h22
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/mmc.h14
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h157
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pins.h30
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h68
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h54
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h49
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/timex.h20
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/uncompress.h53
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/vmalloc.h12
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c50
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c550
-rw-r--r--arch/arm/plat-stmp3xxx/timer.c186
30 files changed, 0 insertions, 3806 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a595b08..c9f69e0b1f55 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -378,16 +378,6 @@ config ARCH_MXS
378 help 378 help
379 Support for Freescale MXS-based family of processors 379 Support for Freescale MXS-based family of processors
380 380
381config ARCH_STMP3XXX
382 bool "Freescale STMP3xxx"
383 select CPU_ARM926T
384 select CLKDEV_LOOKUP
385 select ARCH_REQUIRE_GPIOLIB
386 select GENERIC_CLOCKEVENTS
387 select USB_ARCH_HAS_EHCI
388 help
389 Support for systems based on the Freescale 3xxx CPUs.
390
391config ARCH_NETX 381config ARCH_NETX
392 bool "Hilscher NetX based" 382 bool "Hilscher NetX based"
393 select CPU_ARM926T 383 select CPU_ARM926T
@@ -1005,8 +995,6 @@ source "arch/arm/mach-exynos4/Kconfig"
1005 995
1006source "arch/arm/mach-shmobile/Kconfig" 996source "arch/arm/mach-shmobile/Kconfig"
1007 997
1008source "arch/arm/plat-stmp3xxx/Kconfig"
1009
1010source "arch/arm/mach-tegra/Kconfig" 998source "arch/arm/mach-tegra/Kconfig"
1011 999
1012source "arch/arm/mach-u300/Kconfig" 1000source "arch/arm/mach-u300/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ca473b1669a3..692c481196bd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -205,7 +205,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
205plat-$(CONFIG_ARCH_MXC) := mxc 205plat-$(CONFIG_ARCH_MXC) := mxc
206plat-$(CONFIG_ARCH_OMAP) := omap 206plat-$(CONFIG_ARCH_OMAP) := omap
207plat-$(CONFIG_ARCH_S3C64XX) := samsung 207plat-$(CONFIG_ARCH_S3C64XX) := samsung
208plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
209plat-$(CONFIG_ARCH_TCC_926) := tcc 208plat-$(CONFIG_ARCH_TCC_926) := tcc
210plat-$(CONFIG_PLAT_IOP) := iop 209plat-$(CONFIG_PLAT_IOP) := iop
211plat-$(CONFIG_PLAT_NOMADIK) := nomadik 210plat-$(CONFIG_PLAT_NOMADIK) := nomadik
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
deleted file mode 100644
index e6e312b6bdb5..000000000000
--- a/arch/arm/plat-stmp3xxx/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
1if ARCH_STMP3XXX
2
3menu "Freescale STMP3xxx implementations"
4
5endmenu
6
7endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
deleted file mode 100644
index 31dd518f37a5..000000000000
--- a/arch/arm/plat-stmp3xxx/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4# Object file lists.
5obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
deleted file mode 100644
index 2e712e17ce72..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ /dev/null
@@ -1,1134 +0,0 @@
1/*
2 * Clock manipulation routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clkdev.h>
29
30#include <asm/mach-types.h>
31#include <mach/platform.h>
32#include <mach/regs-clkctrl.h>
33
34#include "clock.h"
35
36static DEFINE_SPINLOCK(clocks_lock);
37
38static struct clk osc_24M;
39static struct clk pll_clk;
40static struct clk cpu_clk;
41static struct clk hclk;
42
43static int propagate_rate(struct clk *);
44
45static inline int clk_is_busy(struct clk *clk)
46{
47 return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
48}
49
50static inline int clk_good(struct clk *clk)
51{
52 return clk && !IS_ERR(clk) && clk->ops;
53}
54
55static int std_clk_enable(struct clk *clk)
56{
57 if (clk->enable_reg) {
58 u32 clk_reg = __raw_readl(clk->enable_reg);
59 if (clk->enable_negate)
60 clk_reg &= ~(1 << clk->enable_shift);
61 else
62 clk_reg |= (1 << clk->enable_shift);
63 __raw_writel(clk_reg, clk->enable_reg);
64 if (clk->enable_wait)
65 udelay(clk->enable_wait);
66 return 0;
67 } else
68 return -EINVAL;
69}
70
71static int std_clk_disable(struct clk *clk)
72{
73 if (clk->enable_reg) {
74 u32 clk_reg = __raw_readl(clk->enable_reg);
75 if (clk->enable_negate)
76 clk_reg |= (1 << clk->enable_shift);
77 else
78 clk_reg &= ~(1 << clk->enable_shift);
79 __raw_writel(clk_reg, clk->enable_reg);
80 return 0;
81 } else
82 return -EINVAL;
83}
84
85static int io_set_rate(struct clk *clk, u32 rate)
86{
87 u32 reg_frac, clkctrl_frac;
88 int i, ret = 0, mask = 0x1f;
89
90 clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
91
92 if (clkctrl_frac < 18 || clkctrl_frac > 35) {
93 ret = -EINVAL;
94 goto out;
95 }
96
97 reg_frac = __raw_readl(clk->scale_reg);
98 reg_frac &= ~(mask << clk->scale_shift);
99 __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
100 clk->scale_reg);
101 if (clk->busy_reg) {
102 for (i = 10000; i; i--)
103 if (!clk_is_busy(clk))
104 break;
105 if (!i)
106 ret = -ETIMEDOUT;
107 else
108 ret = 0;
109 }
110out:
111 return ret;
112}
113
114static long io_get_rate(struct clk *clk)
115{
116 long rate = clk->parent->rate * 18;
117 int mask = 0x1f;
118
119 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
120 clk->rate = rate;
121
122 return rate;
123}
124
125static long per_get_rate(struct clk *clk)
126{
127 long rate = clk->parent->rate;
128 long div;
129 const int mask = 0xff;
130
131 if (clk->enable_reg &&
132 !(__raw_readl(clk->enable_reg) & clk->enable_shift))
133 clk->rate = 0;
134 else {
135 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
136 if (div)
137 rate /= div;
138 clk->rate = rate;
139 }
140
141 return clk->rate;
142}
143
144static int per_set_rate(struct clk *clk, u32 rate)
145{
146 int ret = -EINVAL;
147 int div = (clk->parent->rate + rate - 1) / rate;
148 u32 reg_frac;
149 const int mask = 0xff;
150 int try = 10;
151 int i = -1;
152
153 if (div == 0 || div > mask)
154 goto out;
155
156 reg_frac = __raw_readl(clk->scale_reg);
157 reg_frac &= ~(mask << clk->scale_shift);
158
159 while (try--) {
160 __raw_writel(reg_frac | (div << clk->scale_shift),
161 clk->scale_reg);
162
163 if (clk->busy_reg) {
164 for (i = 10000; i; i--)
165 if (!clk_is_busy(clk))
166 break;
167 }
168 if (i)
169 break;
170 }
171
172 if (!i)
173 ret = -ETIMEDOUT;
174 else
175 ret = 0;
176
177out:
178 if (ret != 0)
179 printk(KERN_ERR "%s: error %d\n", __func__, ret);
180 return ret;
181}
182
183static long lcdif_get_rate(struct clk *clk)
184{
185 long rate = clk->parent->rate;
186 long div;
187 const int mask = 0xff;
188
189 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
190 if (div) {
191 rate /= div;
192 div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
193 BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
194 rate /= div;
195 }
196 clk->rate = rate;
197
198 return rate;
199}
200
201static int lcdif_set_rate(struct clk *clk, u32 rate)
202{
203 int ret = 0;
204 /*
205 * On 3700, we can get most timings exact by modifying ref_pix
206 * and the divider, but keeping the phase timings at 1 (2
207 * phases per cycle).
208 *
209 * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
210 * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
211 *
212 * ns_cycle >= 2*18e3/(18*480) = 25/6
213 * ns_cycle <= 2*35e3/(18*480) = 875/108
214 *
215 * Multiply the ns_cycle by 'div' to lengthen it until it fits the
216 * bounds. This is the divider we'll use after ref_pix.
217 *
218 * 6 * ns_cycle >= 25 * div
219 * 108 * ns_cycle <= 875 * div
220 */
221 u32 ns_cycle = 1000000 / rate;
222 u32 div, reg_val;
223 u32 lowest_result = (u32) -1;
224 u32 lowest_div = 0, lowest_fracdiv = 0;
225
226 for (div = 1; div < 256; ++div) {
227 u32 fracdiv;
228 u32 ps_result;
229 int lower_bound = 6 * ns_cycle >= 25 * div;
230 int upper_bound = 108 * ns_cycle <= 875 * div;
231 if (!lower_bound)
232 break;
233 if (!upper_bound)
234 continue;
235 /*
236 * Found a matching div. Calculate fractional divider needed,
237 * rounded up.
238 */
239 fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
240 ns_cycle + 1000 * div - 1) /
241 (1000 * div);
242 if (fracdiv < 18 || fracdiv > 35) {
243 ret = -EINVAL;
244 goto out;
245 }
246 /* Calculate the actual cycle time this results in */
247 ps_result = 6250 * div * fracdiv / 27;
248
249 /* Use the fastest result that doesn't break ns_cycle */
250 if (ps_result <= lowest_result) {
251 lowest_result = ps_result;
252 lowest_div = div;
253 lowest_fracdiv = fracdiv;
254 }
255 }
256
257 if (div >= 256 || lowest_result == (u32) -1) {
258 ret = -EINVAL;
259 goto out;
260 }
261 pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
262 "PIXCLK=%uMHz cycle=%u.%03uns\n",
263 lowest_fracdiv, lowest_div,
264 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
265 lowest_result / 1000, lowest_result % 1000);
266
267 /* Program ref_pix phase fractional divider */
268 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
269 reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
270 reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
271 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
272
273 /* Ungate PFD */
274 stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
275 REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
276
277 /* Program pix divider */
278 reg_val = __raw_readl(clk->scale_reg);
279 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
280 reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
281 __raw_writel(reg_val, clk->scale_reg);
282
283 /* Wait for divider update */
284 if (clk->busy_reg) {
285 int i;
286 for (i = 10000; i; i--)
287 if (!clk_is_busy(clk))
288 break;
289 if (!i) {
290 ret = -ETIMEDOUT;
291 goto out;
292 }
293 }
294
295 /* Switch to ref_pix source */
296 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
297 reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
298 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
299
300out:
301 return ret;
302}
303
304
305static int cpu_set_rate(struct clk *clk, u32 rate)
306{
307 u32 reg_val;
308
309 if (rate < 24000)
310 return -EINVAL;
311 else if (rate == 24000) {
312 /* switch to the 24M source */
313 clk_set_parent(clk, &osc_24M);
314 } else {
315 int i;
316 u32 clkctrl_cpu = 1;
317 u32 c = clkctrl_cpu;
318 u32 clkctrl_frac = 1;
319 u32 val;
320 for ( ; c < 0x40; c++) {
321 u32 f = (pll_clk.rate*18/c + rate/2) / rate;
322 int s1, s2;
323
324 if (f < 18 || f > 35)
325 continue;
326 s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
327 s2 = pll_clk.rate*18/c/f - rate;
328 pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
329 if (abs(s1) > abs(s2)) {
330 clkctrl_cpu = c;
331 clkctrl_frac = f;
332 }
333 if (s2 == 0)
334 break;
335 };
336 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
337 clkctrl_cpu, clkctrl_frac);
338 if (c == 0x40) {
339 int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
340 rate;
341 if (abs(d) > 100 ||
342 clkctrl_frac < 18 || clkctrl_frac > 35)
343 return -EINVAL;
344 }
345
346 /* 4.6.2 */
347 val = __raw_readl(clk->scale_reg);
348 val &= ~(0x3f << clk->scale_shift);
349 val |= clkctrl_frac;
350 clk_set_parent(clk, &osc_24M);
351 udelay(10);
352 __raw_writel(val, clk->scale_reg);
353 /* ungate */
354 __raw_writel(1<<7, clk->scale_reg + 8);
355 /* write clkctrl_cpu */
356 clk->saved_div = clkctrl_cpu;
357
358 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
359 reg_val &= ~0x3F;
360 reg_val |= clkctrl_cpu;
361 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
362
363 for (i = 10000; i; i--)
364 if (!clk_is_busy(clk))
365 break;
366 if (!i) {
367 printk(KERN_ERR "couldn't set up CPU divisor\n");
368 return -ETIMEDOUT;
369 }
370 clk_set_parent(clk, &pll_clk);
371 clk->saved_div = 0;
372 udelay(10);
373 }
374 return 0;
375}
376
377static long cpu_get_rate(struct clk *clk)
378{
379 long rate = clk->parent->rate * 18;
380
381 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
382 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
383 rate = ((rate + 9) / 10) * 10;
384 clk->rate = rate;
385
386 return rate;
387}
388
389static long cpu_round_rate(struct clk *clk, u32 rate)
390{
391 unsigned long r = 0;
392
393 if (rate <= 24000)
394 r = 24000;
395 else {
396 u32 clkctrl_cpu = 1;
397 u32 clkctrl_frac;
398 do {
399 clkctrl_frac =
400 (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
401 if (clkctrl_frac > 35)
402 continue;
403 if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
404 rate / 10)
405 break;
406 } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
407 if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
408 clkctrl_cpu--;
409 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
410 clkctrl_cpu, clkctrl_frac);
411 if (clkctrl_frac < 18)
412 clkctrl_frac = 18;
413 if (clkctrl_frac > 35)
414 clkctrl_frac = 35;
415
416 r = pll_clk.rate * 18;
417 r /= clkctrl_frac;
418 r /= clkctrl_cpu;
419 r = 10 * ((r + 9) / 10);
420 }
421 return r;
422}
423
424static long emi_get_rate(struct clk *clk)
425{
426 long rate = clk->parent->rate * 18;
427
428 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
429 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
430 clk->rate = rate;
431
432 return rate;
433}
434
435static int clkseq_set_parent(struct clk *clk, struct clk *parent)
436{
437 int ret = -EINVAL;
438 int shift = 8;
439
440 /* bypass? */
441 if (parent == &osc_24M)
442 shift = 4;
443
444 if (clk->bypass_reg) {
445#ifdef CONFIG_ARCH_STMP378X
446 u32 hbus_val, cpu_val;
447
448 if (clk == &cpu_clk && shift == 4) {
449 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
450 HW_CLKCTRL_HBUS);
451 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
452 HW_CLKCTRL_CPU);
453
454 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
455 BM_CLKCTRL_HBUS_DIV);
456 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
457 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
458 cpu_val |= 1;
459
460 if (machine_is_stmp378x()) {
461 __raw_writel(hbus_val,
462 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
463 __raw_writel(cpu_val,
464 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
465 hclk.rate = 0;
466 }
467 } else if (clk == &cpu_clk && shift == 8) {
468 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
469 HW_CLKCTRL_HBUS);
470 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
471 HW_CLKCTRL_CPU);
472 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
473 BM_CLKCTRL_HBUS_DIV);
474 hbus_val |= 2;
475 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
476 if (clk->saved_div)
477 cpu_val |= clk->saved_div;
478 else
479 cpu_val |= 2;
480
481 if (machine_is_stmp378x()) {
482 __raw_writel(hbus_val,
483 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
484 __raw_writel(cpu_val,
485 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
486 hclk.rate = 0;
487 }
488 }
489#endif
490 __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
491
492 ret = 0;
493 }
494
495 return ret;
496}
497
498static int hbus_set_rate(struct clk *clk, u32 rate)
499{
500 u8 div = 0;
501 int is_frac = 0;
502 u32 clkctrl_hbus;
503 struct clk *parent = clk->parent;
504
505 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
506 parent->rate);
507
508 if (rate > parent->rate)
509 return -EINVAL;
510
511 if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
512 parent->rate / rate < 32) {
513 pr_debug("%s: switching to fractional mode\n", __func__);
514 is_frac = 1;
515 }
516
517 if (is_frac)
518 div = (32 * rate + parent->rate / 2) / parent->rate;
519 else
520 div = (parent->rate + rate - 1) / rate;
521 pr_debug("%s: div calculated is %d\n", __func__, div);
522 if (!div || div > 0x1f)
523 return -EINVAL;
524
525 clk_set_parent(&cpu_clk, &osc_24M);
526 udelay(10);
527 clkctrl_hbus = __raw_readl(clk->scale_reg);
528 clkctrl_hbus &= ~0x3f;
529 clkctrl_hbus |= div;
530 clkctrl_hbus |= (is_frac << 5);
531
532 __raw_writel(clkctrl_hbus, clk->scale_reg);
533 if (clk->busy_reg) {
534 int i;
535 for (i = 10000; i; i--)
536 if (!clk_is_busy(clk))
537 break;
538 if (!i) {
539 printk(KERN_ERR "couldn't set up CPU divisor\n");
540 return -ETIMEDOUT;
541 }
542 }
543 clk_set_parent(&cpu_clk, &pll_clk);
544 __raw_writel(clkctrl_hbus, clk->scale_reg);
545 udelay(10);
546 return 0;
547}
548
549static long hbus_get_rate(struct clk *clk)
550{
551 long rate = clk->parent->rate;
552
553 if (__raw_readl(clk->scale_reg) & 0x20) {
554 rate *= __raw_readl(clk->scale_reg) & 0x1f;
555 rate /= 32;
556 } else
557 rate /= __raw_readl(clk->scale_reg) & 0x1f;
558 clk->rate = rate;
559
560 return rate;
561}
562
563static int xbus_set_rate(struct clk *clk, u32 rate)
564{
565 u16 div = 0;
566 u32 clkctrl_xbus;
567
568 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
569 clk->parent->rate);
570
571 div = (clk->parent->rate + rate - 1) / rate;
572 pr_debug("%s: div calculated is %d\n", __func__, div);
573 if (!div || div > 0x3ff)
574 return -EINVAL;
575
576 clkctrl_xbus = __raw_readl(clk->scale_reg);
577 clkctrl_xbus &= ~0x3ff;
578 clkctrl_xbus |= div;
579 __raw_writel(clkctrl_xbus, clk->scale_reg);
580 if (clk->busy_reg) {
581 int i;
582 for (i = 10000; i; i--)
583 if (!clk_is_busy(clk))
584 break;
585 if (!i) {
586 printk(KERN_ERR "couldn't set up xbus divisor\n");
587 return -ETIMEDOUT;
588 }
589 }
590 return 0;
591}
592
593static long xbus_get_rate(struct clk *clk)
594{
595 long rate = clk->parent->rate;
596
597 rate /= __raw_readl(clk->scale_reg) & 0x3ff;
598 clk->rate = rate;
599
600 return rate;
601}
602
603
604/* Clock ops */
605
606static struct clk_ops std_ops = {
607 .enable = std_clk_enable,
608 .disable = std_clk_disable,
609 .get_rate = per_get_rate,
610 .set_rate = per_set_rate,
611 .set_parent = clkseq_set_parent,
612};
613
614static struct clk_ops min_ops = {
615 .enable = std_clk_enable,
616 .disable = std_clk_disable,
617};
618
619static struct clk_ops cpu_ops = {
620 .enable = std_clk_enable,
621 .disable = std_clk_disable,
622 .get_rate = cpu_get_rate,
623 .set_rate = cpu_set_rate,
624 .round_rate = cpu_round_rate,
625 .set_parent = clkseq_set_parent,
626};
627
628static struct clk_ops io_ops = {
629 .enable = std_clk_enable,
630 .disable = std_clk_disable,
631 .get_rate = io_get_rate,
632 .set_rate = io_set_rate,
633};
634
635static struct clk_ops hbus_ops = {
636 .get_rate = hbus_get_rate,
637 .set_rate = hbus_set_rate,
638};
639
640static struct clk_ops xbus_ops = {
641 .get_rate = xbus_get_rate,
642 .set_rate = xbus_set_rate,
643};
644
645static struct clk_ops lcdif_ops = {
646 .enable = std_clk_enable,
647 .disable = std_clk_disable,
648 .get_rate = lcdif_get_rate,
649 .set_rate = lcdif_set_rate,
650 .set_parent = clkseq_set_parent,
651};
652
653static struct clk_ops emi_ops = {
654 .get_rate = emi_get_rate,
655};
656
657/* List of on-chip clocks */
658
659static struct clk osc_24M = {
660 .flags = FIXED_RATE | ENABLED,
661 .rate = 24000,
662};
663
664static struct clk pll_clk = {
665 .parent = &osc_24M,
666 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
667 .enable_shift = 16,
668 .enable_wait = 10,
669 .flags = FIXED_RATE | ENABLED,
670 .rate = 480000,
671 .ops = &min_ops,
672};
673
674static struct clk cpu_clk = {
675 .parent = &pll_clk,
676 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
677 .scale_shift = 0,
678 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
679 .bypass_shift = 7,
680 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
681 .busy_bit = 28,
682 .flags = RATE_PROPAGATES | ENABLED,
683 .ops = &cpu_ops,
684};
685
686static struct clk io_clk = {
687 .parent = &pll_clk,
688 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
689 .enable_shift = 31,
690 .enable_negate = 1,
691 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
692 .scale_shift = 24,
693 .flags = RATE_PROPAGATES | ENABLED,
694 .ops = &io_ops,
695};
696
697static struct clk hclk = {
698 .parent = &cpu_clk,
699 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
700 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
701 .bypass_shift = 7,
702 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
703 .busy_bit = 29,
704 .flags = RATE_PROPAGATES | ENABLED,
705 .ops = &hbus_ops,
706};
707
708static struct clk xclk = {
709 .parent = &osc_24M,
710 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
711 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
712 .busy_bit = 31,
713 .flags = RATE_PROPAGATES | ENABLED,
714 .ops = &xbus_ops,
715};
716
717static struct clk uart_clk = {
718 .parent = &xclk,
719 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
720 .enable_shift = 31,
721 .enable_negate = 1,
722 .flags = ENABLED,
723 .ops = &min_ops,
724};
725
726static struct clk audio_clk = {
727 .parent = &xclk,
728 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
729 .enable_shift = 30,
730 .enable_negate = 1,
731 .ops = &min_ops,
732};
733
734static struct clk pwm_clk = {
735 .parent = &xclk,
736 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
737 .enable_shift = 29,
738 .enable_negate = 1,
739 .ops = &min_ops,
740};
741
742static struct clk dri_clk = {
743 .parent = &xclk,
744 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
745 .enable_shift = 28,
746 .enable_negate = 1,
747 .ops = &min_ops,
748};
749
750static struct clk digctl_clk = {
751 .parent = &xclk,
752 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
753 .enable_shift = 27,
754 .enable_negate = 1,
755 .ops = &min_ops,
756};
757
758static struct clk timer_clk = {
759 .parent = &xclk,
760 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
761 .enable_shift = 26,
762 .enable_negate = 1,
763 .flags = ENABLED,
764 .ops = &min_ops,
765};
766
767static struct clk lcdif_clk = {
768 .parent = &pll_clk,
769 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
770 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
771 .busy_bit = 29,
772 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
773 .enable_shift = 31,
774 .enable_negate = 1,
775 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
776 .bypass_shift = 1,
777 .flags = NEEDS_SET_PARENT,
778 .ops = &lcdif_ops,
779};
780
781static struct clk ssp_clk = {
782 .parent = &io_clk,
783 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
784 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
785 .busy_bit = 29,
786 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
787 .enable_shift = 31,
788 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
789 .bypass_shift = 5,
790 .enable_negate = 1,
791 .flags = NEEDS_SET_PARENT,
792 .ops = &std_ops,
793};
794
795static struct clk gpmi_clk = {
796 .parent = &io_clk,
797 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
798 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
799 .busy_bit = 29,
800 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
801 .enable_shift = 31,
802 .enable_negate = 1,
803 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
804 .bypass_shift = 4,
805 .flags = NEEDS_SET_PARENT,
806 .ops = &std_ops,
807};
808
809static struct clk spdif_clk = {
810 .parent = &pll_clk,
811 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
812 .enable_shift = 31,
813 .enable_negate = 1,
814 .ops = &min_ops,
815};
816
817static struct clk emi_clk = {
818 .parent = &pll_clk,
819 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
820 .enable_shift = 31,
821 .enable_negate = 1,
822 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
823 .scale_shift = 8,
824 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
825 .busy_bit = 28,
826 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
827 .bypass_shift = 6,
828 .flags = ENABLED,
829 .ops = &emi_ops,
830};
831
832static struct clk ir_clk = {
833 .parent = &io_clk,
834 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
835 .enable_shift = 31,
836 .enable_negate = 1,
837 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
838 .bypass_shift = 3,
839 .ops = &min_ops,
840};
841
842static struct clk saif_clk = {
843 .parent = &pll_clk,
844 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
845 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
846 .busy_bit = 29,
847 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
848 .enable_shift = 31,
849 .enable_negate = 1,
850 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
851 .bypass_shift = 0,
852 .ops = &std_ops,
853};
854
855static struct clk usb_clk = {
856 .parent = &pll_clk,
857 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
858 .enable_shift = 18,
859 .enable_negate = 1,
860 .ops = &min_ops,
861};
862
863/* list of all the clocks */
864static struct clk_lookup onchip_clks[] = {
865 {
866 .con_id = "osc_24M",
867 .clk = &osc_24M,
868 }, {
869 .con_id = "pll",
870 .clk = &pll_clk,
871 }, {
872 .con_id = "cpu",
873 .clk = &cpu_clk,
874 }, {
875 .con_id = "hclk",
876 .clk = &hclk,
877 }, {
878 .con_id = "xclk",
879 .clk = &xclk,
880 }, {
881 .con_id = "io",
882 .clk = &io_clk,
883 }, {
884 .con_id = "uart",
885 .clk = &uart_clk,
886 }, {
887 .con_id = "audio",
888 .clk = &audio_clk,
889 }, {
890 .con_id = "pwm",
891 .clk = &pwm_clk,
892 }, {
893 .con_id = "dri",
894 .clk = &dri_clk,
895 }, {
896 .con_id = "digctl",
897 .clk = &digctl_clk,
898 }, {
899 .con_id = "timer",
900 .clk = &timer_clk,
901 }, {
902 .con_id = "lcdif",
903 .clk = &lcdif_clk,
904 }, {
905 .con_id = "ssp",
906 .clk = &ssp_clk,
907 }, {
908 .con_id = "gpmi",
909 .clk = &gpmi_clk,
910 }, {
911 .con_id = "spdif",
912 .clk = &spdif_clk,
913 }, {
914 .con_id = "emi",
915 .clk = &emi_clk,
916 }, {
917 .con_id = "ir",
918 .clk = &ir_clk,
919 }, {
920 .con_id = "saif",
921 .clk = &saif_clk,
922 }, {
923 .con_id = "usb",
924 .clk = &usb_clk,
925 },
926};
927
928static int __init propagate_rate(struct clk *clk)
929{
930 struct clk_lookup *cl;
931
932 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
933 cl++) {
934 if (unlikely(!clk_good(cl->clk)))
935 continue;
936 if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
937 cl->clk->ops->get_rate(cl->clk);
938 if (cl->clk->flags & RATE_PROPAGATES)
939 propagate_rate(cl->clk);
940 }
941 }
942
943 return 0;
944}
945
946/* Exported API */
947unsigned long clk_get_rate(struct clk *clk)
948{
949 if (unlikely(!clk_good(clk)))
950 return 0;
951
952 if (clk->rate != 0)
953 return clk->rate;
954
955 if (clk->ops->get_rate != NULL)
956 return clk->ops->get_rate(clk);
957
958 return clk_get_rate(clk->parent);
959}
960EXPORT_SYMBOL(clk_get_rate);
961
962long clk_round_rate(struct clk *clk, unsigned long rate)
963{
964 if (unlikely(!clk_good(clk)))
965 return 0;
966
967 if (clk->ops->round_rate)
968 return clk->ops->round_rate(clk, rate);
969
970 return 0;
971}
972EXPORT_SYMBOL(clk_round_rate);
973
974static inline int close_enough(long rate1, long rate2)
975{
976 return rate1 && !((rate2 - rate1) * 1000 / rate1);
977}
978
979int clk_set_rate(struct clk *clk, unsigned long rate)
980{
981 int ret = -EINVAL;
982
983 if (unlikely(!clk_good(clk)))
984 goto out;
985
986 if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
987 goto out;
988
989 else if (!close_enough(clk->rate, rate)) {
990 ret = clk->ops->set_rate(clk, rate);
991 if (ret < 0)
992 goto out;
993 clk->rate = rate;
994 if (clk->flags & RATE_PROPAGATES)
995 propagate_rate(clk);
996 } else
997 ret = 0;
998
999out:
1000 return ret;
1001}
1002EXPORT_SYMBOL(clk_set_rate);
1003
1004int clk_enable(struct clk *clk)
1005{
1006 unsigned long clocks_flags;
1007
1008 if (unlikely(!clk_good(clk)))
1009 return -EINVAL;
1010
1011 if (clk->parent)
1012 clk_enable(clk->parent);
1013
1014 spin_lock_irqsave(&clocks_lock, clocks_flags);
1015
1016 clk->usage++;
1017 if (clk->ops && clk->ops->enable)
1018 clk->ops->enable(clk);
1019
1020 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1021 return 0;
1022}
1023EXPORT_SYMBOL(clk_enable);
1024
1025static void local_clk_disable(struct clk *clk)
1026{
1027 if (unlikely(!clk_good(clk)))
1028 return;
1029
1030 if (clk->usage == 0 && clk->ops->disable)
1031 clk->ops->disable(clk);
1032
1033 if (clk->parent)
1034 local_clk_disable(clk->parent);
1035}
1036
1037void clk_disable(struct clk *clk)
1038{
1039 unsigned long clocks_flags;
1040
1041 if (unlikely(!clk_good(clk)))
1042 return;
1043
1044 spin_lock_irqsave(&clocks_lock, clocks_flags);
1045
1046 if ((--clk->usage) == 0 && clk->ops->disable)
1047 clk->ops->disable(clk);
1048
1049 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1050 if (clk->parent)
1051 clk_disable(clk->parent);
1052}
1053EXPORT_SYMBOL(clk_disable);
1054
1055/* Some additional API */
1056int clk_set_parent(struct clk *clk, struct clk *parent)
1057{
1058 int ret = -ENODEV;
1059 unsigned long clocks_flags;
1060
1061 if (unlikely(!clk_good(clk)))
1062 goto out;
1063
1064 if (!clk->ops->set_parent)
1065 goto out;
1066
1067 spin_lock_irqsave(&clocks_lock, clocks_flags);
1068
1069 ret = clk->ops->set_parent(clk, parent);
1070 if (!ret) {
1071 /* disable if usage count is 0 */
1072 local_clk_disable(parent);
1073
1074 parent->usage += clk->usage;
1075 clk->parent->usage -= clk->usage;
1076
1077 /* disable if new usage count is 0 */
1078 local_clk_disable(clk->parent);
1079
1080 clk->parent = parent;
1081 }
1082 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1083
1084out:
1085 return ret;
1086}
1087EXPORT_SYMBOL(clk_set_parent);
1088
1089struct clk *clk_get_parent(struct clk *clk)
1090{
1091 if (unlikely(!clk_good(clk)))
1092 return NULL;
1093 return clk->parent;
1094}
1095EXPORT_SYMBOL(clk_get_parent);
1096
1097static int __init clk_init(void)
1098{
1099 struct clk_lookup *cl;
1100 struct clk_ops *ops;
1101
1102 spin_lock_init(&clocks_lock);
1103
1104 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
1105 cl++) {
1106 if (cl->clk->flags & ENABLED)
1107 clk_enable(cl->clk);
1108 else
1109 local_clk_disable(cl->clk);
1110
1111 ops = cl->clk->ops;
1112
1113 if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
1114 ops && ops->set_rate)
1115 ops->set_rate(cl->clk, cl->clk->rate);
1116
1117 if (cl->clk->flags & FIXED_RATE) {
1118 if (cl->clk->flags & RATE_PROPAGATES)
1119 propagate_rate(cl->clk);
1120 } else {
1121 if (ops && ops->get_rate)
1122 ops->get_rate(cl->clk);
1123 }
1124
1125 if (cl->clk->flags & NEEDS_SET_PARENT) {
1126 if (ops && ops->set_parent)
1127 ops->set_parent(cl->clk, cl->clk->parent);
1128 }
1129 }
1130 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
1131 return 0;
1132}
1133
1134arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
deleted file mode 100644
index a6611e1a3510..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
19#define __ARCH_ARM_STMX3XXX_CLOCK_H__
20
21#ifndef __ASSEMBLER__
22
23struct clk_ops {
24 int (*enable) (struct clk *);
25 int (*disable) (struct clk *);
26 long (*get_rate) (struct clk *);
27 long (*round_rate) (struct clk *, u32);
28 int (*set_rate) (struct clk *, u32);
29 int (*set_parent) (struct clk *, struct clk *);
30};
31
32struct clk {
33 struct clk *parent;
34 u32 rate;
35 u32 flags;
36 u8 scale_shift;
37 u8 enable_shift;
38 u8 bypass_shift;
39 u8 busy_bit;
40 s8 usage;
41 int enable_wait;
42 int enable_negate;
43 u32 saved_div;
44 void __iomem *enable_reg;
45 void __iomem *scale_reg;
46 void __iomem *bypass_reg;
47 void __iomem *busy_reg;
48 struct clk_ops *ops;
49};
50
51#endif /* __ASSEMBLER__ */
52
53/* Flags */
54#define RATE_PROPAGATES (1<<0)
55#define NEEDS_INITIALIZATION (1<<1)
56#define PARENT_SET_RATE (1<<2)
57#define FIXED_RATE (1<<3)
58#define ENABLED (1<<4)
59#define NEEDS_SET_PARENT (1<<5)
60
61#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
deleted file mode 100644
index 37b8a09148a4..000000000000
--- a/arch/arm/plat-stmp3xxx/core.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core routines
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <mach/stmp3xxx.h>
23#include <mach/platform.h>
24#include <mach/dma.h>
25#include <mach/regs-clkctrl.h>
26
27static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
28{
29 u32 c;
30 int timeout;
31
32 /* the process of software reset of IP block is done
33 in several steps:
34
35 - clear SFTRST and wait for block is enabled;
36 - clear clock gating (CLKGATE bit);
37 - set the SFTRST again and wait for block is in reset;
38 - clear SFTRST and wait for reset completion.
39 */
40 c = __raw_readl(hwreg);
41 c &= ~(1<<31); /* clear SFTRST */
42 __raw_writel(c, hwreg);
43 for (timeout = 1000000; timeout > 0; timeout--)
44 /* still in SFTRST state ? */
45 if ((__raw_readl(hwreg) & (1<<31)) == 0)
46 break;
47 if (timeout <= 0) {
48 printk(KERN_ERR"%s(%p): timeout when enabling\n",
49 __func__, hwreg);
50 return -ETIME;
51 }
52
53 c = __raw_readl(hwreg);
54 c &= ~(1<<30); /* clear CLKGATE */
55 __raw_writel(c, hwreg);
56
57 if (!just_enable) {
58 c = __raw_readl(hwreg);
59 c |= (1<<31); /* now again set SFTRST */
60 __raw_writel(c, hwreg);
61 for (timeout = 1000000; timeout > 0; timeout--)
62 /* poll until CLKGATE set */
63 if (__raw_readl(hwreg) & (1<<30))
64 break;
65 if (timeout <= 0) {
66 printk(KERN_ERR"%s(%p): timeout when resetting\n",
67 __func__, hwreg);
68 return -ETIME;
69 }
70
71 c = __raw_readl(hwreg);
72 c &= ~(1<<31); /* clear SFTRST */
73 __raw_writel(c, hwreg);
74 for (timeout = 1000000; timeout > 0; timeout--)
75 /* still in SFTRST state ? */
76 if ((__raw_readl(hwreg) & (1<<31)) == 0)
77 break;
78 if (timeout <= 0) {
79 printk(KERN_ERR"%s(%p): timeout when enabling "
80 "after reset\n", __func__, hwreg);
81 return -ETIME;
82 }
83
84 c = __raw_readl(hwreg);
85 c &= ~(1<<30); /* clear CLKGATE */
86 __raw_writel(c, hwreg);
87 }
88 for (timeout = 1000000; timeout > 0; timeout--)
89 /* still in SFTRST state ? */
90 if ((__raw_readl(hwreg) & (1<<30)) == 0)
91 break;
92
93 if (timeout <= 0) {
94 printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
95 __func__, hwreg);
96 return -ETIME;
97 }
98
99 return 0;
100}
101
102int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
103{
104 int try = 10;
105 int r;
106
107 while (try--) {
108 r = __stmp3xxx_reset_block(hwreg, just_enable);
109 if (!r)
110 break;
111 pr_debug("%s: try %d failed\n", __func__, 10 - try);
112 }
113 return r;
114}
115EXPORT_SYMBOL(stmp3xxx_reset_block);
116
117struct platform_device stmp3xxx_dbguart = {
118 .name = "stmp3xxx-dbguart",
119 .id = -1,
120};
121
122void __init stmp3xxx_init(void)
123{
124 /* Turn off auto-slow and other tricks */
125 stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
126
127 stmp3xxx_dma_init();
128}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
deleted file mode 100644
index 68fed4b8746a..000000000000
--- a/arch/arm/plat-stmp3xxx/devices.c
+++ /dev/null
@@ -1,389 +0,0 @@
1/*
2* Freescale STMP37XX/STMP378X platform devices
3*
4* Embedded Alley Solutions, Inc <source@embeddedalley.com>
5*
6* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8*/
9
10/*
11* The code contained herein is licensed under the GNU General Public
12* License. You may obtain a copy of the GNU General Public License
13* Version 2 or later at the following locations:
14*
15* http://www.opensource.org/licenses/gpl-license.html
16* http://www.gnu.org/copyleft/gpl.html
17*/
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23
24#include <mach/dma.h>
25#include <mach/platform.h>
26#include <mach/stmp3xxx.h>
27#include <mach/regs-lcdif.h>
28#include <mach/regs-uartapp.h>
29#include <mach/regs-gpmi.h>
30#include <mach/regs-usbctrl.h>
31#include <mach/regs-ssp.h>
32#include <mach/regs-rtc.h>
33
34static u64 common_dmamask = DMA_BIT_MASK(32);
35
36static struct resource appuart_resources[] = {
37 {
38 .start = IRQ_UARTAPP_INTERNAL,
39 .end = IRQ_UARTAPP_INTERNAL,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = IRQ_UARTAPP_RX_DMA,
43 .end = IRQ_UARTAPP_RX_DMA,
44 .flags = IORESOURCE_IRQ,
45 }, {
46 .start = IRQ_UARTAPP_TX_DMA,
47 .end = IRQ_UARTAPP_TX_DMA,
48 .flags = IORESOURCE_IRQ,
49 }, {
50 .start = REGS_UARTAPP1_PHYS,
51 .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
52 .flags = IORESOURCE_MEM,
53 }, {
54 /* Rx DMA channel */
55 .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
56 .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
57 .flags = IORESOURCE_DMA,
58 }, {
59 /* Tx DMA channel */
60 .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
61 .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device stmp3xxx_appuart = {
67 .name = "stmp3xxx-appuart",
68 .id = 0,
69 .resource = appuart_resources,
70 .num_resources = ARRAY_SIZE(appuart_resources),
71 .dev = {
72 .dma_mask = &common_dmamask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 },
75};
76
77struct platform_device stmp3xxx_watchdog = {
78 .name = "stmp3xxx_wdt",
79 .id = -1,
80};
81
82static struct resource ts_resource[] = {
83 {
84 .flags = IORESOURCE_IRQ,
85 .start = IRQ_TOUCH_DETECT,
86 .end = IRQ_TOUCH_DETECT,
87 }, {
88 .flags = IORESOURCE_IRQ,
89 .start = IRQ_LRADC_CH5,
90 .end = IRQ_LRADC_CH5,
91 },
92};
93
94struct platform_device stmp3xxx_touchscreen = {
95 .name = "stmp3xxx_ts",
96 .id = -1,
97 .resource = ts_resource,
98 .num_resources = ARRAY_SIZE(ts_resource),
99};
100
101/*
102* Keypad device
103*/
104struct platform_device stmp3xxx_keyboard = {
105 .name = "stmp3xxx-keyboard",
106 .id = -1,
107};
108
109static struct resource gpmi_resources[] = {
110 {
111 .flags = IORESOURCE_MEM,
112 .start = REGS_GPMI_PHYS,
113 .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
114 }, {
115 .flags = IORESOURCE_IRQ,
116 .start = IRQ_GPMI_DMA,
117 .end = IRQ_GPMI_DMA,
118 }, {
119 .flags = IORESOURCE_DMA,
120 .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
121 .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
122 },
123};
124
125struct platform_device stmp3xxx_gpmi = {
126 .name = "gpmi",
127 .id = -1,
128 .dev = {
129 .dma_mask = &common_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 },
132 .resource = gpmi_resources,
133 .num_resources = ARRAY_SIZE(gpmi_resources),
134};
135
136static struct resource mmc1_resource[] = {
137 {
138 .flags = IORESOURCE_MEM,
139 .start = REGS_SSP1_PHYS,
140 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
141 }, {
142 .flags = IORESOURCE_DMA,
143 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
144 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
145 }, {
146 .flags = IORESOURCE_IRQ,
147 .start = IRQ_SSP1_DMA,
148 .end = IRQ_SSP1_DMA,
149 }, {
150 .flags = IORESOURCE_IRQ,
151 .start = IRQ_SSP_ERROR,
152 .end = IRQ_SSP_ERROR,
153 },
154};
155
156struct platform_device stmp3xxx_mmc = {
157 .name = "stmp3xxx-mmc",
158 .id = 1,
159 .dev = {
160 .dma_mask = &common_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163 .resource = mmc1_resource,
164 .num_resources = ARRAY_SIZE(mmc1_resource),
165};
166
167static struct resource usb_resources[] = {
168 {
169 .start = REGS_USBCTRL_PHYS,
170 .end = REGS_USBCTRL_PHYS + SZ_4K,
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_USB_CTRL,
174 .end = IRQ_USB_CTRL,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179struct platform_device stmp3xxx_udc = {
180 .name = "fsl-usb2-udc",
181 .id = -1,
182 .dev = {
183 .dma_mask = &common_dmamask,
184 .coherent_dma_mask = DMA_BIT_MASK(32),
185 },
186 .resource = usb_resources,
187 .num_resources = ARRAY_SIZE(usb_resources),
188};
189
190struct platform_device stmp3xxx_ehci = {
191 .name = "fsl-ehci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &common_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 },
197 .resource = usb_resources,
198 .num_resources = ARRAY_SIZE(usb_resources),
199};
200
201static struct resource rtc_resources[] = {
202 {
203 .start = REGS_RTC_PHYS,
204 .end = REGS_RTC_PHYS + REGS_RTC_SIZE,
205 .flags = IORESOURCE_MEM,
206 }, {
207 .start = IRQ_RTC_ALARM,
208 .end = IRQ_RTC_ALARM,
209 .flags = IORESOURCE_IRQ,
210 }, {
211 .start = IRQ_RTC_1MSEC,
212 .end = IRQ_RTC_1MSEC,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217struct platform_device stmp3xxx_rtc = {
218 .name = "stmp3xxx-rtc",
219 .id = -1,
220 .resource = rtc_resources,
221 .num_resources = ARRAY_SIZE(rtc_resources),
222};
223
224static struct resource ssp1_resources[] = {
225 {
226 .start = REGS_SSP1_PHYS,
227 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .start = IRQ_SSP1_DMA,
231 .end = IRQ_SSP1_DMA,
232 .flags = IORESOURCE_IRQ,
233 }, {
234 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
235 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
236 .flags = IORESOURCE_DMA,
237 },
238};
239
240static struct resource ssp2_resources[] = {
241 {
242 .start = REGS_SSP2_PHYS,
243 .end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = IRQ_SSP2_DMA,
247 .end = IRQ_SSP2_DMA,
248 .flags = IORESOURCE_IRQ,
249 }, {
250 .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
251 .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
252 .flags = IORESOURCE_DMA,
253 },
254};
255
256struct platform_device stmp3xxx_spi1 = {
257 .name = "stmp3xxx_ssp",
258 .id = 1,
259 .dev = {
260 .dma_mask = &common_dmamask,
261 .coherent_dma_mask = DMA_BIT_MASK(32),
262 },
263 .resource = ssp1_resources,
264 .num_resources = ARRAY_SIZE(ssp1_resources),
265};
266
267struct platform_device stmp3xxx_spi2 = {
268 .name = "stmp3xxx_ssp",
269 .id = 2,
270 .dev = {
271 .dma_mask = &common_dmamask,
272 .coherent_dma_mask = DMA_BIT_MASK(32),
273 },
274 .resource = ssp2_resources,
275 .num_resources = ARRAY_SIZE(ssp2_resources),
276};
277
278static struct resource fb_resource[] = {
279 {
280 .flags = IORESOURCE_IRQ,
281 .start = IRQ_LCDIF_DMA,
282 .end = IRQ_LCDIF_DMA,
283 }, {
284 .flags = IORESOURCE_IRQ,
285 .start = IRQ_LCDIF_ERROR,
286 .end = IRQ_LCDIF_ERROR,
287 }, {
288 .flags = IORESOURCE_MEM,
289 .start = REGS_LCDIF_PHYS,
290 .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
291 },
292};
293
294struct platform_device stmp3xxx_framebuffer = {
295 .name = "stmp3xxx-fb",
296 .id = -1,
297 .dev = {
298 .dma_mask = &common_dmamask,
299 .coherent_dma_mask = DMA_BIT_MASK(32),
300 },
301 .num_resources = ARRAY_SIZE(fb_resource),
302 .resource = fb_resource,
303};
304
305#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
306 static char *cmdline_device_##name; \
307 static int cmdline_device_##name##_setup(char *dev) \
308 { \
309 cmdline_device_##name = dev + 1; \
310 return 0; \
311 } \
312 __setup(#name, cmdline_device_##name##_setup); \
313 int stmp3xxx_##name##_device_register(void) \
314 { \
315 struct platform_device *d = NULL; \
316 if (!cmdline_device_##name || \
317 !strcmp(cmdline_device_##name, #dev1)) \
318 d = &stmp3xxx_##dev1; \
319 else if (!strcmp(cmdline_device_##name, #dev2)) \
320 d = &stmp3xxx_##dev2; \
321 else \
322 printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
323 #name, cmdline_device_##name); \
324 return d ? platform_device_register(d) : -ENOENT; \
325 }
326
327CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
328CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
329
330struct platform_device stmp3xxx_backlight = {
331 .name = "stmp3xxx-bl",
332 .id = -1,
333};
334
335struct platform_device stmp3xxx_rotdec = {
336 .name = "stmp3xxx-rotdec",
337 .id = -1,
338};
339
340struct platform_device stmp3xxx_persistent = {
341 .name = "stmp3xxx-persistent",
342 .id = -1,
343};
344
345struct platform_device stmp3xxx_dcp_bootstream = {
346 .name = "stmp3xxx-dcpboot",
347 .id = -1,
348 .dev = {
349 .dma_mask = &common_dmamask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352};
353
354static struct resource dcp_resources[] = {
355 {
356 .start = IRQ_DCP_VMI,
357 .end = IRQ_DCP_VMI,
358 .flags = IORESOURCE_IRQ,
359 }, {
360 .start = IRQ_DCP,
361 .end = IRQ_DCP,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366struct platform_device stmp3xxx_dcp = {
367 .name = "stmp3xxx-dcp",
368 .id = -1,
369 .resource = dcp_resources,
370 .num_resources = ARRAY_SIZE(dcp_resources),
371 .dev = {
372 .dma_mask = &common_dmamask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
374 },
375};
376
377static struct resource battery_resource[] = {
378 {
379 .flags = IORESOURCE_IRQ,
380 .start = IRQ_VDD5V,
381 .end = IRQ_VDD5V,
382 },
383};
384
385struct platform_device stmp3xxx_battery = {
386 .name = "stmp3xxx-battery",
387 .resource = battery_resource,
388 .num_resources = ARRAY_SIZE(battery_resource),
389};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
deleted file mode 100644
index b4dcf8c0477d..000000000000
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ /dev/null
@@ -1,464 +0,0 @@
1/*
2 * DMA helper routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: dmitry pervushin <dpervushin@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/gfp.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/dmapool.h>
22#include <linux/sysdev.h>
23#include <linux/cpufreq.h>
24
25#include <asm/page.h>
26
27#include <mach/platform.h>
28#include <mach/dma.h>
29#include <mach/regs-apbx.h>
30#include <mach/regs-apbh.h>
31
32static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
33static const size_t pool_alignment = 8;
34static struct stmp3xxx_dma_user {
35 void *pool;
36 int inuse;
37 const char *name;
38} channels[MAX_DMA_CHANNELS];
39
40#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
41#define IS_USED(ch) (channels[ch].inuse)
42
43int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
44{
45 struct stmp3xxx_dma_user *user;
46 int err = 0;
47
48 user = channels + ch;
49 if (!IS_VALID_CHANNEL(ch)) {
50 err = -ENODEV;
51 goto out;
52 }
53 if (IS_USED(ch)) {
54 err = -EBUSY;
55 goto out;
56 }
57 /* Create a pool to allocate dma commands from */
58 user->pool = dma_pool_create(name, dev, pool_item_size,
59 pool_alignment, PAGE_SIZE);
60 if (user->pool == NULL) {
61 err = -ENOMEM;
62 goto out;
63 }
64 user->name = name;
65 user->inuse++;
66out:
67 return err;
68}
69EXPORT_SYMBOL(stmp3xxx_dma_request);
70
71int stmp3xxx_dma_release(int ch)
72{
73 struct stmp3xxx_dma_user *user = channels + ch;
74 int err = 0;
75
76 if (!IS_VALID_CHANNEL(ch)) {
77 err = -ENODEV;
78 goto out;
79 }
80 if (!IS_USED(ch)) {
81 err = -EBUSY;
82 goto out;
83 }
84 BUG_ON(user->pool == NULL);
85 dma_pool_destroy(user->pool);
86 user->inuse--;
87out:
88 return err;
89}
90EXPORT_SYMBOL(stmp3xxx_dma_release);
91
92int stmp3xxx_dma_read_semaphore(int channel)
93{
94 int sem = -1;
95
96 switch (STMP3XXX_DMA_BUS(channel)) {
97 case STMP3XXX_BUS_APBH:
98 sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
99 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
100 sem &= BM_APBH_CHn_SEMA_PHORE;
101 sem >>= BP_APBH_CHn_SEMA_PHORE;
102 break;
103
104 case STMP3XXX_BUS_APBX:
105 sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
106 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
107 sem &= BM_APBX_CHn_SEMA_PHORE;
108 sem >>= BP_APBX_CHn_SEMA_PHORE;
109 break;
110 default:
111 BUG();
112 }
113 return sem;
114}
115EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
116
117int stmp3xxx_dma_allocate_command(int channel,
118 struct stmp3xxx_dma_descriptor *descriptor)
119{
120 struct stmp3xxx_dma_user *user = channels + channel;
121 int err = 0;
122
123 if (!IS_VALID_CHANNEL(channel)) {
124 err = -ENODEV;
125 goto out;
126 }
127 if (!IS_USED(channel)) {
128 err = -EBUSY;
129 goto out;
130 }
131 if (descriptor == NULL) {
132 err = -EINVAL;
133 goto out;
134 }
135
136 /* Allocate memory for a command from the buffer */
137 descriptor->command =
138 dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
139
140 /* Check it worked */
141 if (!descriptor->command) {
142 err = -ENOMEM;
143 goto out;
144 }
145
146 memset(descriptor->command, 0, pool_item_size);
147out:
148 WARN_ON(err);
149 return err;
150}
151EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
152
153int stmp3xxx_dma_free_command(int channel,
154 struct stmp3xxx_dma_descriptor *descriptor)
155{
156 int err = 0;
157
158 if (!IS_VALID_CHANNEL(channel)) {
159 err = -ENODEV;
160 goto out;
161 }
162 if (!IS_USED(channel)) {
163 err = -EBUSY;
164 goto out;
165 }
166
167 /* Return the command memory to the pool */
168 dma_pool_free(channels[channel].pool, descriptor->command,
169 descriptor->handle);
170
171 /* Initialise descriptor so we're not tempted to use it */
172 descriptor->command = NULL;
173 descriptor->handle = 0;
174 descriptor->virtual_buf_ptr = NULL;
175 descriptor->next_descr = NULL;
176
177 WARN_ON(err);
178out:
179 return err;
180}
181EXPORT_SYMBOL(stmp3xxx_dma_free_command);
182
183void stmp3xxx_dma_go(int channel,
184 struct stmp3xxx_dma_descriptor *head, u32 semaphore)
185{
186 int ch = STMP3XXX_DMA_CHANNEL(channel);
187 void __iomem *c, *s;
188
189 switch (STMP3XXX_DMA_BUS(channel)) {
190 case STMP3XXX_BUS_APBH:
191 c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
192 s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
193 break;
194
195 case STMP3XXX_BUS_APBX:
196 c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
197 s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
198 break;
199
200 default:
201 return;
202 }
203
204 /* Set next command */
205 __raw_writel(head->handle, c);
206 /* Set counting semaphore (kicks off transfer). Assumes
207 peripheral has been set up correctly */
208 __raw_writel(semaphore, s);
209}
210EXPORT_SYMBOL(stmp3xxx_dma_go);
211
212int stmp3xxx_dma_running(int channel)
213{
214 switch (STMP3XXX_DMA_BUS(channel)) {
215 case STMP3XXX_BUS_APBH:
216 return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
217 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
218 BM_APBH_CHn_SEMA_PHORE;
219
220 case STMP3XXX_BUS_APBX:
221 return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
222 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
223 BM_APBX_CHn_SEMA_PHORE;
224 default:
225 BUG();
226 return 0;
227 }
228}
229EXPORT_SYMBOL(stmp3xxx_dma_running);
230
231/*
232 * Circular dma chain management
233 */
234void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
235{
236 int i;
237
238 for (i = 0; i < chain->total_count; i++)
239 stmp3xxx_dma_free_command(
240 STMP3XXX_DMA(chain->channel, chain->bus),
241 &chain->chain[i]);
242}
243EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
244
245int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
246 struct stmp3xxx_dma_descriptor descriptors[],
247 unsigned items)
248{
249 int i;
250 int err = 0;
251
252 if (items == 0)
253 return err;
254
255 for (i = 0; i < items; i++) {
256 err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
257 if (err) {
258 WARN_ON(err);
259 /*
260 * Couldn't allocate the whole chain.
261 * deallocate what has been allocated
262 */
263 if (i) {
264 do {
265 stmp3xxx_dma_free_command(ch,
266 &descriptors
267 [i]);
268 } while (i-- > 0);
269 }
270 return err;
271 }
272
273 /* link them! */
274 if (i > 0) {
275 descriptors[i - 1].next_descr = &descriptors[i];
276 descriptors[i - 1].command->next =
277 descriptors[i].handle;
278 }
279 }
280
281 /* make list circular */
282 descriptors[items - 1].next_descr = &descriptors[0];
283 descriptors[items - 1].command->next = descriptors[0].handle;
284
285 chain->total_count = items;
286 chain->chain = descriptors;
287 chain->free_index = 0;
288 chain->active_index = 0;
289 chain->cooked_index = 0;
290 chain->free_count = items;
291 chain->active_count = 0;
292 chain->cooked_count = 0;
293 chain->bus = STMP3XXX_DMA_BUS(ch);
294 chain->channel = STMP3XXX_DMA_CHANNEL(ch);
295 return err;
296}
297EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
298
299void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
300{
301 BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
302 chain->free_index = 0;
303 chain->active_index = 0;
304 chain->cooked_index = 0;
305 chain->free_count = chain->total_count;
306 chain->active_count = 0;
307 chain->cooked_count = 0;
308}
309EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
310
311void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
312 unsigned count)
313{
314 BUG_ON(chain->cooked_count < count);
315
316 chain->cooked_count -= count;
317 chain->cooked_index += count;
318 chain->cooked_index %= chain->total_count;
319 chain->free_count += count;
320}
321EXPORT_SYMBOL(stmp37xx_circ_advance_free);
322
323void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
324 unsigned count)
325{
326 void __iomem *c;
327 u32 mask_clr, mask;
328 BUG_ON(chain->free_count < count);
329
330 chain->free_count -= count;
331 chain->free_index += count;
332 chain->free_index %= chain->total_count;
333 chain->active_count += count;
334
335 switch (chain->bus) {
336 case STMP3XXX_BUS_APBH:
337 c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
338 mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
339 mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
340 break;
341 case STMP3XXX_BUS_APBX:
342 c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
343 mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
344 mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
345 break;
346 default:
347 BUG();
348 return;
349 }
350
351 /* Set counting semaphore (kicks off transfer). Assumes
352 peripheral has been set up correctly */
353 stmp3xxx_clearl(mask_clr, c);
354 stmp3xxx_setl(mask, c);
355}
356EXPORT_SYMBOL(stmp37xx_circ_advance_active);
357
358unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
359{
360 unsigned cooked;
361
362 cooked = chain->active_count -
363 stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
364
365 chain->active_count -= cooked;
366 chain->active_index += cooked;
367 chain->active_index %= chain->total_count;
368
369 chain->cooked_count += cooked;
370
371 return cooked;
372}
373EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
374
375void stmp3xxx_dma_set_alt_target(int channel, int function)
376{
377#if defined(CONFIG_ARCH_STMP37XX)
378 unsigned bits = 4;
379#elif defined(CONFIG_ARCH_STMP378X)
380 unsigned bits = 2;
381#else
382#error wrong arch
383#endif
384 int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
385 unsigned mask = (1<<bits) - 1;
386 void __iomem *c;
387
388 BUG_ON(function < 0 || function >= (1<<bits));
389 pr_debug("%s: channel = %d, using mask %x, "
390 "shift = %d\n", __func__, channel, mask, shift);
391
392 switch (STMP3XXX_DMA_BUS(channel)) {
393 case STMP3XXX_BUS_APBH:
394 c = REGS_APBH_BASE + HW_APBH_DEVSEL;
395 break;
396 case STMP3XXX_BUS_APBX:
397 c = REGS_APBX_BASE + HW_APBX_DEVSEL;
398 break;
399 default:
400 BUG();
401 }
402 stmp3xxx_clearl(mask << shift, c);
403 stmp3xxx_setl(mask << shift, c);
404}
405EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
406
407void stmp3xxx_dma_suspend(void)
408{
409 stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
410 stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
411}
412
413void stmp3xxx_dma_resume(void)
414{
415 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
416 REGS_APBH_BASE + HW_APBH_CTRL0);
417 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
418 REGS_APBX_BASE + HW_APBX_CTRL0);
419}
420
421#ifdef CONFIG_CPU_FREQ
422
423struct dma_notifier_block {
424 struct notifier_block nb;
425 void *data;
426};
427
428static int dma_cpufreq_notifier(struct notifier_block *self,
429 unsigned long phase, void *p)
430{
431 switch (phase) {
432 case CPUFREQ_POSTCHANGE:
433 stmp3xxx_dma_resume();
434 break;
435
436 case CPUFREQ_PRECHANGE:
437 stmp3xxx_dma_suspend();
438 break;
439
440 default:
441 break;
442 }
443
444 return NOTIFY_DONE;
445}
446
447static struct dma_notifier_block dma_cpufreq_nb = {
448 .nb = {
449 .notifier_call = dma_cpufreq_notifier,
450 },
451};
452#endif /* CONFIG_CPU_FREQ */
453
454void __init stmp3xxx_dma_init(void)
455{
456 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
457 REGS_APBH_BASE + HW_APBH_CTRL0);
458 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
459 REGS_APBX_BASE + HW_APBX_CTRL0);
460#ifdef CONFIG_CPU_FREQ
461 cpufreq_register_notifier(&dma_cpufreq_nb.nb,
462 CPUFREQ_TRANSITION_NOTIFIER);
463#endif /* CONFIG_CPU_FREQ */
464}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
deleted file mode 100644
index f9c39772d7c5..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#ifndef __ASM_MACH_CLKDEV_H
13#define __ASM_MACH_CLKDEV_H
14
15#define __clk_get(clk) ({ 1; })
16#define __clk_put(clk) do { } while (0)
17
18#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
deleted file mode 100644
index b4e205b95f2c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X CPU type detection
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_CPU_H
19#define __ASM_PLAT_CPU_H
20
21#ifdef CONFIG_ARCH_STMP37XX
22#define cpu_is_stmp37xx() (1)
23#else
24#define cpu_is_stmp37xx() (0)
25#endif
26
27#ifdef CONFIG_ARCH_STMP378X
28#define cpu_is_stmp378x() (1)
29#else
30#define cpu_is_stmp378x() (0)
31#endif
32
33#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
deleted file mode 100644
index d3a0985c9681..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro addruart, rp, rv
20 mov \rp, #0x00070000
21 add \rv, \rp, #0xf0000000 @ virtual base
22 add \rp, \rp, #0x80000000 @ physical base
23 .endm
24
25 .macro senduart,rd,rx
26 strb \rd, [\rx, #0] @ data register at 0
27 .endm
28
29 .macro waituart,rd,rx
301001: ldr \rd, [\rx, #0x18] @ UARTFLG
31 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
32 bne 1001b
33 .endm
34
35 .macro busyuart,rd,rx
361001: ldr \rd, [\rx, #0x18] @ UARTFLG
37 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
38 bne 1001b
39 .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
deleted file mode 100644
index 7c58557c6766..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/dma.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X DMA helper interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_DMA_H
19#define __ASM_PLAT_STMP3XXX_DMA_H
20
21#include <linux/platform_device.h>
22#include <linux/dmapool.h>
23
24#if !defined(MAX_PIO_WORDS)
25#define MAX_PIO_WORDS (15)
26#endif
27
28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16
31#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
32#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
33#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
34#define MAX_DMA_ADDRESS 0xffffffff
35#define MAX_DMA_CHANNELS 32
36
37struct stmp3xxx_dma_command {
38 u32 next;
39 u32 cmd;
40 union {
41 u32 buf_ptr;
42 u32 alternate;
43 };
44 u32 pio_words[MAX_PIO_WORDS];
45};
46
47struct stmp3xxx_dma_descriptor {
48 struct stmp3xxx_dma_command *command;
49 dma_addr_t handle;
50
51 /* The virtual address of the buffer pointer */
52 void *virtual_buf_ptr;
53 /* The next descriptor in a the DMA chain (optional) */
54 struct stmp3xxx_dma_descriptor *next_descr;
55};
56
57struct stmp37xx_circ_dma_chain {
58 unsigned total_count;
59 struct stmp3xxx_dma_descriptor *chain;
60
61 unsigned free_index;
62 unsigned free_count;
63 unsigned active_index;
64 unsigned active_count;
65 unsigned cooked_index;
66 unsigned cooked_count;
67
68 int bus;
69 unsigned channel;
70};
71
72static inline struct stmp3xxx_dma_descriptor
73 *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
74{
75 return &(chain->chain[chain->free_index]);
76}
77
78static inline struct stmp3xxx_dma_descriptor
79 *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
80{
81 return &(chain->chain[chain->cooked_index]);
82}
83
84int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
85int stmp3xxx_dma_release(int ch);
86int stmp3xxx_dma_allocate_command(int ch,
87 struct stmp3xxx_dma_descriptor *descriptor);
88int stmp3xxx_dma_free_command(int ch,
89 struct stmp3xxx_dma_descriptor *descriptor);
90void stmp3xxx_dma_continue(int channel, u32 semaphore);
91void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
92 u32 semaphore);
93int stmp3xxx_dma_running(int ch);
94int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
95 struct stmp3xxx_dma_descriptor descriptors[],
96 unsigned items);
97void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
98void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
99void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
100 unsigned count);
101void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
102 unsigned count);
103unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
104int stmp3xxx_dma_read_semaphore(int ch);
105void stmp3xxx_dma_init(void);
106void stmp3xxx_dma_set_alt_target(int ch, int target);
107void stmp3xxx_dma_suspend(void);
108void stmp3xxx_dma_resume(void);
109
110/*
111 * STMP37xx and STMP378x have different DMA control
112 * registers layout
113 */
114
115void stmp3xxx_arch_dma_freeze(int ch);
116void stmp3xxx_arch_dma_unfreeze(int ch);
117void stmp3xxx_arch_dma_reset_channel(int ch);
118void stmp3xxx_arch_dma_enable_interrupt(int ch);
119void stmp3xxx_arch_dma_clear_interrupt(int ch);
120int stmp3xxx_arch_dma_is_interrupt(int ch);
121
122static inline void stmp3xxx_dma_reset_channel(int ch)
123{
124 stmp3xxx_arch_dma_reset_channel(ch);
125}
126
127
128static inline void stmp3xxx_dma_freeze(int ch)
129{
130 stmp3xxx_arch_dma_freeze(ch);
131}
132
133static inline void stmp3xxx_dma_unfreeze(int ch)
134{
135 stmp3xxx_arch_dma_unfreeze(ch);
136}
137
138static inline void stmp3xxx_dma_enable_interrupt(int ch)
139{
140 stmp3xxx_arch_dma_enable_interrupt(ch);
141}
142
143static inline void stmp3xxx_dma_clear_interrupt(int ch)
144{
145 stmp3xxx_arch_dma_clear_interrupt(ch);
146}
147
148static inline int stmp3xxx_dma_is_interrupt(int ch)
149{
150 return stmp3xxx_arch_dma_is_interrupt(ch);
151}
152
153#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
deleted file mode 100644
index a8b579256170..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X GPIO interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_GPIO_H
19#define __ASM_PLAT_GPIO_H
20
21#define ARCH_NR_GPIOS (32 * 3)
22#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
23#define gpio_get_value(gpio) __gpio_get_value(gpio)
24#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
25
26#include <asm-generic/gpio.h>
27
28#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
deleted file mode 100644
index e166432910ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __MACH_GPMI_H
2
3#include <linux/mtd/partitions.h>
4#include <mach/regs-gpmi.h>
5
6struct gpmi_platform_data {
7 void *pins;
8 int nr_parts;
9 struct mtd_partition *parts;
10 const char *part_types[];
11};
12#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
deleted file mode 100644
index 47b8978405bc..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file contains the hardware definitions of the Freescale STMP3XXX
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_HARDWARE_H
19#define __ASM_ARCH_HARDWARE_H
20
21/*
22 * Where in virtual memory the IO devices (timers, system controllers
23 * and so on)
24 */
25#define IO_BASE 0xF0000000 /* VA of IO */
26#define IO_SIZE 0x00100000 /* How much? */
27#define IO_START 0x80000000 /* PA of IO */
28
29/* macro to get at IO space when running virtually */
30#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
31
32#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
deleted file mode 100644
index d08b1b7f3d1c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23#define __mem_isa(a) (a)
24
25#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
deleted file mode 100644
index 61fa54882e12..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET UL(0x40000000)
21
22#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
deleted file mode 100644
index ba81e1543761..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _MACH_MMC_H
2#define _MACH_MMC_H
3
4#include <mach/regs-ssp.h>
5
6struct stmp3xxxmmc_platform_data {
7 int (*get_wp)(void);
8 unsigned long (*setclock)(void __iomem *base, unsigned long);
9 void (*cmd_pullup)(int);
10 int (*hw_init)(void);
11 void (*hw_release)(void);
12};
13
14#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
deleted file mode 100644
index cc5af82279ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __PINMUX_H
19#define __PINMUX_H
20
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <asm-generic/gpio.h>
25
26/* Pin definitions */
27#include "pins.h"
28#include <mach/pins.h>
29
30/*
31 * Each pin may be routed up to four different HW interfaces
32 * including GPIO
33 */
34enum pin_fun {
35 PIN_FUN1 = 0,
36 PIN_FUN2,
37 PIN_FUN3,
38 PIN_GPIO,
39};
40
41/*
42 * Each pin may have different output drive strength in range from
43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
44 */
45enum pin_strength {
46 PIN_4MA = 0,
47 PIN_8MA,
48 PIN_12MA,
49 PIN_16MA,
50 PIN_20MA,
51};
52
53/*
54 * Each pin can be programmed for 1.8V or 3.3V
55 */
56enum pin_voltage {
57 PIN_1_8V = 0,
58 PIN_3_3V,
59};
60
61/*
62 * Structure to define a group of pins and their parameters
63 */
64struct pin_desc {
65 unsigned id;
66 enum pin_fun fun;
67 enum pin_strength strength;
68 enum pin_voltage voltage;
69 unsigned pullup:1;
70};
71
72struct pin_group {
73 struct pin_desc *pins;
74 int nr_pins;
75};
76
77/* Set pin drive strength */
78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
79 const char *label);
80
81/* Set pin voltage */
82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
83 const char *label);
84
85/* Enable pull-up resistor for a pin */
86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
87
88/*
89 * Request a pin ownership, only one module (identified by @label)
90 * may own a pin.
91 */
92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
93
94/* Release pin */
95void stmp3xxx_release_pin(unsigned id, const char *label);
96
97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
98
99/*
100 * Each bank is associated with a number of registers to control
101 * pin function, drive strength, voltage and pull-up reigster. The
102 * number of registers of a given type depends on the number of bits
103 * describin particular pin.
104 */
105#define HW_MUXSEL_NUM 2 /* registers per bank */
106#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
107#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
108#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
109#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
110
111#define HW_DRIVE_NUM 4 /* registers per bank */
112#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
113#define HW_DRIVE_PIN_NUM 8 /* pins per register */
114#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
115#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
116#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
117
118
119struct stmp3xxx_pinmux_bank {
120 struct gpio_chip chip;
121
122 /* Pins allocation map */
123 unsigned long pin_map;
124
125 /* Pin owner names */
126 const char *pin_labels[32];
127
128 /* Bank registers */
129 void __iomem *hw_muxsel[HW_MUXSEL_NUM];
130 void __iomem *hw_drive[HW_DRIVE_NUM];
131 void __iomem *hw_pull;
132
133 void __iomem *pin2irq,
134 *irqlevel,
135 *irqpolarity,
136 *irqen,
137 *irqstat;
138
139 /* HW MUXSEL register function bit values */
140 u8 functions[HW_MUXSEL_PINFUN_NUM];
141
142 /*
143 * HW DRIVE register strength bit values:
144 * 0xff - requested strength is not supported for this bank
145 */
146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147
148 /* GPIO things */
149 void __iomem *hw_gpio_in,
150 *hw_gpio_out,
151 *hw_gpio_doe;
152 int irq, virq;
153};
154
155int __init stmp3xxx_pinmux_init(int virtual_irq_start);
156
157#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
deleted file mode 100644
index c573318e1caa..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pins.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_PINS_H
19#define __ASM_PLAT_PINS_H
20
21#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
22#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
23#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
24
25/*
26 * Special invalid pin identificator to show a pin doesn't exist
27 */
28#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
29
30#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
deleted file mode 100644
index 7007ddaa91eb..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/platform.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H
16
17#ifndef __ASSEMBLER__
18#include <linux/io.h>
19#endif
20#include <asm/sizes.h>
21
22/* Virtual address where registers are mapped */
23#define STMP3XXX_REGS_PHBASE 0x80000000
24#ifdef __ASSEMBLER__
25#define STMP3XXX_REGS_BASE 0xF0000000
26#else
27#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
28#endif
29#define STMP3XXX_REGS_SIZE SZ_1M
30
31/* Virtual address where OCRAM is mapped */
32#define STMP3XXX_OCRAM_PHBASE 0x00000000
33#ifdef __ASSEMBLER__
34#define STMP3XXX_OCRAM_BASE 0xf1000000
35#else
36#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
37#endif
38#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
39
40#ifdef CONFIG_ARCH_STMP37XX
41#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
42#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
43#endif
44
45#ifdef CONFIG_ARCH_STMP378X
46#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
47#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
48#endif
49
50#define HW_STMP3XXX_SET 0x04
51#define HW_STMP3XXX_CLR 0x08
52#define HW_STMP3XXX_TOG 0x0c
53
54#ifndef __ASSEMBLER__
55static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
56{
57 __raw_writel(v, r + HW_STMP3XXX_CLR);
58}
59
60static inline void stmp3xxx_setl(u32 v, void __iomem *r)
61{
62 __raw_writel(v, r + HW_STMP3XXX_SET);
63}
64#endif
65
66#define BF(value, field) (((value) << BP_##field) & BM_##field)
67
68#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
deleted file mode 100644
index 2e300feaa4cf..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core structure and function declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_H
19#define __ASM_PLAT_STMP3XXX_H
20
21#include <linux/irq.h>
22
23extern struct sys_timer stmp3xxx_timer;
24
25void stmp3xxx_init_irq(struct irq_chip *chip);
26void stmp3xxx_init(void);
27int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
28extern struct platform_device stmp3xxx_dbguart,
29 stmp3xxx_appuart,
30 stmp3xxx_watchdog,
31 stmp3xxx_touchscreen,
32 stmp3xxx_keyboard,
33 stmp3xxx_gpmi,
34 stmp3xxx_mmc,
35 stmp3xxx_udc,
36 stmp3xxx_ehci,
37 stmp3xxx_rtc,
38 stmp3xxx_spi1,
39 stmp3xxx_spi2,
40 stmp3xxx_backlight,
41 stmp3xxx_rotdec,
42 stmp3xxx_dcp,
43 stmp3xxx_dcp_bootstream,
44 stmp3xxx_persistent,
45 stmp3xxx_framebuffer,
46 stmp3xxx_battery;
47int stmp3xxx_ssp1_device_register(void);
48int stmp3xxx_ssp2_device_register(void);
49
50struct pin_group;
51void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
52int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
53
54#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
deleted file mode 100644
index 28a988889319..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
20#include <mach/platform.h>
21#include <mach/regs-clkctrl.h>
22#include <mach/regs-power.h>
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30
31 cpu_do_idle();
32}
33
34static inline void arch_reset(char mode, const char *cmd)
35{
36 /* Set BATTCHRG to default value */
37 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
38
39 /* Set MINPWR to default value */
40 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
41
42 /* Reset digital side of chip (but not power or RTC) */
43 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
45
46 /* Should not return */
47}
48
49#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
deleted file mode 100644
index 3373985d7a8e..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/*
18 * System time clock is sourced from the 32k clock
19 */
20#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
deleted file mode 100644
index f79f5ee56cd4..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 *
3 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 */
6
7/*
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
11 *
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
14 */
15#ifndef __ASM_PLAT_UNCOMPRESS_H
16#define __ASM_PLAT_UNCOMPRESS_H
17
18/*
19 * Register includes are for when the MMU enabled; we need to define our
20 * own stuff here for pre-MMU use
21 */
22#define UARTDBG_BASE 0x80070000
23#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
24
25/*
26 * This does not append a newline
27 */
28static void putc(char c)
29{
30 /* Wait for TX fifo empty */
31 while ((UART(6) & (1<<7)) == 0)
32 continue;
33
34 /* Write byte */
35 UART(0) = c;
36
37 /* Wait for last bit to exit the UART */
38 while (UART(6) & (1<<3))
39 continue;
40}
41
42static void flush(void)
43{
44}
45
46/*
47 * nothing to do
48 */
49#define arch_decomp_setup()
50
51#define arch_decomp_wdog()
52
53#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 943c1a29d641..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
deleted file mode 100644
index 6fdf9acf82ed..000000000000
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X common interrupt handling code
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/sysdev.h>
23
24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
26#include <mach/regs-icoll.h>
27
28void __init stmp3xxx_init_irq(struct irq_chip *chip)
29{
30 unsigned int i, lv;
31
32 /* Reset the interrupt controller */
33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
34
35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->irq_mask(irq_get_irq_data(i));
38 irq_set_chip_and_handler(i, chip, handle_level_irq);
39 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
40 }
41
42 /* Ensure vector is cleared */
43 for (lv = 0; lv < 4; lv++)
44 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
45 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
46
47 /* Barrier */
48 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
49}
50
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
deleted file mode 100644
index 3def03b3217d..000000000000
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ /dev/null
@@ -1,550 +0,0 @@
1/*
2 * Freescale STMP378X/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/sysdev.h>
23#include <linux/string.h>
24#include <linux/bitops.h>
25#include <linux/irq.h>
26
27#include <mach/hardware.h>
28#include <mach/platform.h>
29#include <mach/regs-pinctrl.h>
30#include <mach/pins.h>
31#include <mach/pinmux.h>
32
33#define NR_BANKS ARRAY_SIZE(pinmux_banks)
34static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
35 [0] = {
36 .hw_muxsel = {
37 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
38 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
39 },
40 .hw_drive = {
41 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
42 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
43 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
44 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
45 },
46 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
47 .functions = { 0x0, 0x1, 0x2, 0x3 },
48 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
49
50 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
51 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
52 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
53 .irq = IRQ_GPIO0,
54
55 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
56 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
57 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
58 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
59 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
60 },
61 [1] = {
62 .hw_muxsel = {
63 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
64 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
65 },
66 .hw_drive = {
67 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
68 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
69 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
70 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
71 },
72 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
73 .functions = { 0x0, 0x1, 0x2, 0x3 },
74 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
75
76 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
77 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
78 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
79 .irq = IRQ_GPIO1,
80
81 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
82 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
83 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
84 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
85 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
86 },
87 [2] = {
88 .hw_muxsel = {
89 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
90 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
91 },
92 .hw_drive = {
93 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
94 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
95 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
96 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
97 },
98 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
99 .functions = { 0x0, 0x1, 0x2, 0x3 },
100 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
101
102 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
103 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
104 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
105 .irq = IRQ_GPIO2,
106
107 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
108 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
109 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
110 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
111 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
112 },
113 [3] = {
114 .hw_muxsel = {
115 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
116 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
117 },
118 .hw_drive = {
119 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
120 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
121 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
122 NULL,
123 },
124 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
125 .functions = {0x0, 0x1, 0x2, 0x3},
126 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
127 },
128};
129
130static inline struct stmp3xxx_pinmux_bank *
131stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
132{
133 unsigned b, p;
134
135 b = STMP3XXX_PINID_TO_BANK(id);
136 p = STMP3XXX_PINID_TO_PINNUM(id);
137 BUG_ON(b >= NR_BANKS);
138 if (bank)
139 *bank = b;
140 if (pin)
141 *pin = p;
142 return &pinmux_banks[b];
143}
144
145/* Check if requested pin is owned by caller */
146static int stmp3xxx_check_pin(unsigned id, const char *label)
147{
148 unsigned pin;
149 struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
150
151 if (!test_bit(pin, &pm->pin_map)) {
152 printk(KERN_WARNING
153 "%s: Accessing free pin %x, caller %s\n",
154 __func__, id, label);
155
156 return -EINVAL;
157 }
158
159 if (label && pm->pin_labels[pin] &&
160 strcmp(label, pm->pin_labels[pin])) {
161 printk(KERN_WARNING
162 "%s: Wrong pin owner %x, caller %s owner %s\n",
163 __func__, id, label, pm->pin_labels[pin]);
164
165 return -EINVAL;
166 }
167 return 0;
168}
169
170void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
171 const char *label)
172{
173 struct stmp3xxx_pinmux_bank *pbank;
174 void __iomem *hwdrive;
175 u32 shift, val;
176 u32 bank, pin;
177
178 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
179 pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
180 bank, pin, strength);
181
182 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
183 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
184 val = pbank->strengths[strength];
185 if (val == 0xff) {
186 printk(KERN_WARNING
187 "%s: strength is not supported for bank %d, caller %s",
188 __func__, bank, label);
189 return;
190 }
191
192 if (stmp3xxx_check_pin(id, label))
193 return;
194
195 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
196 val << shift, hwdrive);
197 stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
198 stmp3xxx_setl(val << shift, hwdrive);
199}
200
201void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
202 const char *label)
203{
204 struct stmp3xxx_pinmux_bank *pbank;
205 void __iomem *hwdrive;
206 u32 shift;
207 u32 bank, pin;
208
209 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
210 pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
211 bank, pin, voltage);
212
213 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
214 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
215
216 if (stmp3xxx_check_pin(id, label))
217 return;
218
219 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
220 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
221 if (voltage == PIN_1_8V)
222 stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
223 else
224 stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
225}
226
227void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
228{
229 struct stmp3xxx_pinmux_bank *pbank;
230 void __iomem *hwpull;
231 u32 bank, pin;
232
233 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
234 pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
235 bank, pin, enable);
236
237 hwpull = pbank->hw_pull;
238
239 if (stmp3xxx_check_pin(id, label))
240 return;
241
242 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
243 __func__, 1 << pin, hwpull);
244 if (enable)
245 stmp3xxx_setl(1 << pin, hwpull);
246 else
247 stmp3xxx_clearl(1 << pin, hwpull);
248}
249
250int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
251{
252 struct stmp3xxx_pinmux_bank *pbank;
253 u32 bank, pin;
254 int ret = 0;
255
256 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
257 pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
258 bank, pin, fun);
259
260 if (test_bit(pin, &pbank->pin_map)) {
261 printk(KERN_WARNING
262 "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
263 __func__, bank, pin, label, pbank->pin_labels[pin]);
264 return -EBUSY;
265 }
266
267 set_bit(pin, &pbank->pin_map);
268 pbank->pin_labels[pin] = label;
269
270 stmp3xxx_set_pin_type(id, fun);
271
272 return ret;
273}
274
275void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
276{
277 struct stmp3xxx_pinmux_bank *pbank;
278 void __iomem *hwmux;
279 u32 shift, val;
280 u32 bank, pin;
281
282 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
283
284 hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
285 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
286
287 val = pbank->functions[fun];
288 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
289 pr_debug("%s: writing 0x%x to 0x%p register\n",
290 __func__, val << shift, hwmux);
291 stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
292 stmp3xxx_setl(val << shift, hwmux);
293}
294
295void stmp3xxx_release_pin(unsigned id, const char *label)
296{
297 struct stmp3xxx_pinmux_bank *pbank;
298 u32 bank, pin;
299
300 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
301 pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
302
303 if (stmp3xxx_check_pin(id, label))
304 return;
305
306 clear_bit(pin, &pbank->pin_map);
307 pbank->pin_labels[pin] = NULL;
308}
309
310int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
311{
312 struct pin_desc *pin;
313 int p;
314 int err = 0;
315
316 /* Allocate and configure pins */
317 for (p = 0; p < pin_group->nr_pins; p++) {
318 pr_debug("%s: #%d\n", __func__, p);
319 pin = &pin_group->pins[p];
320
321 err = stmp3xxx_request_pin(pin->id, pin->fun, label);
322 if (err)
323 goto out_err;
324
325 stmp3xxx_pin_strength(pin->id, pin->strength, label);
326 stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
327 stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
328 }
329
330 return 0;
331
332out_err:
333 /* Release allocated pins in case of error */
334 while (--p >= 0) {
335 pr_debug("%s: releasing #%d\n", __func__, p);
336 stmp3xxx_release_pin(pin_group->pins[p].id, label);
337 }
338 return err;
339}
340EXPORT_SYMBOL(stmp3xxx_request_pin_group);
341
342void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
343{
344 struct pin_desc *pin;
345 int p;
346
347 for (p = 0; p < pin_group->nr_pins; p++) {
348 pin = &pin_group->pins[p];
349 stmp3xxx_release_pin(pin->id, label);
350 }
351}
352EXPORT_SYMBOL(stmp3xxx_release_pin_group);
353
354static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
355 struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
356{
357 struct stmp3xxx_pinmux_bank *pm;
358
359 for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
360 if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
361 *bank = pm;
362 *gpio = d->irq - pm->virq;
363 return 0;
364 }
365 return -ENOENT;
366}
367
368static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
369{
370 struct stmp3xxx_pinmux_bank *pm;
371 unsigned gpio;
372 int l, p;
373
374 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
375 switch (type) {
376 case IRQ_TYPE_EDGE_RISING:
377 l = 0; p = 1; break;
378 case IRQ_TYPE_EDGE_FALLING:
379 l = 0; p = 0; break;
380 case IRQ_TYPE_LEVEL_HIGH:
381 l = 1; p = 1; break;
382 case IRQ_TYPE_LEVEL_LOW:
383 l = 1; p = 0; break;
384 default:
385 pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
386 __func__, type);
387 return -ENXIO;
388 }
389
390 if (l)
391 stmp3xxx_setl(1 << gpio, pm->irqlevel);
392 else
393 stmp3xxx_clearl(1 << gpio, pm->irqlevel);
394 if (p)
395 stmp3xxx_setl(1 << gpio, pm->irqpolarity);
396 else
397 stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
398 return 0;
399}
400
401static void stmp3xxx_pin_ack_irq(struct irq_data *d)
402{
403 u32 stat;
404 struct stmp3xxx_pinmux_bank *pm;
405 unsigned gpio;
406
407 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
408 stat = __raw_readl(pm->irqstat) & (1 << gpio);
409 stmp3xxx_clearl(stat, pm->irqstat);
410}
411
412static void stmp3xxx_pin_mask_irq(struct irq_data *d)
413{
414 struct stmp3xxx_pinmux_bank *pm;
415 unsigned gpio;
416
417 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
418 stmp3xxx_clearl(1 << gpio, pm->irqen);
419 stmp3xxx_clearl(1 << gpio, pm->pin2irq);
420}
421
422static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
423{
424 struct stmp3xxx_pinmux_bank *pm;
425 unsigned gpio;
426
427 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
428 stmp3xxx_setl(1 << gpio, pm->irqen);
429 stmp3xxx_setl(1 << gpio, pm->pin2irq);
430}
431
432static inline
433struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
434{
435 return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
436}
437
438static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
439{
440 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
441 return pm->virq + offset;
442}
443
444static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
445{
446 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
447 unsigned v;
448
449 v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
450 return v ? 1 : 0;
451}
452
453static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
454{
455 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
456
457 if (v)
458 stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
459 else
460 stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
461}
462
463static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
464{
465 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
466
467 stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
468 stmp3xxx_gpio_set(chip, offset, v);
469 return 0;
470}
471
472static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
473{
474 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
475
476 stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
477 return 0;
478}
479
480static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
481{
482 return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
483}
484
485static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
486{
487 stmp3xxx_release_pin(chip->base + offset, "gpio");
488}
489
490static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
491{
492 struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
493 int gpio_irq = pm->virq;
494 u32 stat = __raw_readl(pm->irqstat);
495
496 while (stat) {
497 if (stat & 1)
498 generic_handle_irq(gpio_irq);
499 gpio_irq++;
500 stat >>= 1;
501 }
502}
503
504static struct irq_chip gpio_irq_chip = {
505 .irq_ack = stmp3xxx_pin_ack_irq,
506 .irq_mask = stmp3xxx_pin_mask_irq,
507 .irq_unmask = stmp3xxx_pin_unmask_irq,
508 .irq_set_type = stmp3xxx_set_irqtype,
509};
510
511int __init stmp3xxx_pinmux_init(int virtual_irq_start)
512{
513 int b, r = 0;
514 struct stmp3xxx_pinmux_bank *pm;
515 int virq;
516
517 for (b = 0; b < 3; b++) {
518 /* only banks 0,1,2 are allowed to GPIO */
519 pm = pinmux_banks + b;
520 pm->chip.base = 32 * b;
521 pm->chip.ngpio = 32;
522 pm->chip.owner = THIS_MODULE;
523 pm->chip.can_sleep = 1;
524 pm->chip.exported = 1;
525 pm->chip.to_irq = stmp3xxx_gpio_to_irq;
526 pm->chip.direction_input = stmp3xxx_gpio_input;
527 pm->chip.direction_output = stmp3xxx_gpio_output;
528 pm->chip.get = stmp3xxx_gpio_get;
529 pm->chip.set = stmp3xxx_gpio_set;
530 pm->chip.request = stmp3xxx_gpio_request;
531 pm->chip.free = stmp3xxx_gpio_free;
532 pm->virq = virtual_irq_start + b * 32;
533
534 for (virq = pm->virq; virq < pm->virq; virq++) {
535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
536 irq_set_chip_and_handler(virq, &gpio_irq_chip,
537 handle_level_irq);
538 set_irq_flags(virq, IRQF_VALID);
539 }
540 r = gpiochip_add(&pm->chip);
541 if (r < 0)
542 break;
543 irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
544 irq_set_handler_data(pm->irq, pm);
545 }
546 return r;
547}
548
549MODULE_AUTHOR("Vladislav Buzov");
550MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
deleted file mode 100644
index c395630a6edc..000000000000
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * System timer for Freescale STMP37XX/STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26
27#include <asm/mach/time.h>
28#include <mach/stmp3xxx.h>
29#include <mach/platform.h>
30#include <mach/regs-timrot.h>
31
32static irqreturn_t
33stmp3xxx_timer_interrupt(int irq, void *dev_id)
34{
35 struct clock_event_device *c = dev_id;
36
37 /* timer 0 */
38 if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
39 BM_TIMROT_TIMCTRLn_IRQ) {
40 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
41 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
42 c->event_handler(c);
43 }
44
45 /* timer 1 */
46 else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
47 & BM_TIMROT_TIMCTRLn_IRQ) {
48 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
49 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
50 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
51 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
52 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
53 }
54
55 return IRQ_HANDLED;
56}
57
58static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
59{
60 return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
61 & 0xFFFF0000) >> 16);
62}
63
64static int
65stmp3xxx_timrot_set_next_event(unsigned long delta,
66 struct clock_event_device *dev)
67{
68 /* reload the timer */
69 __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
70 return 0;
71}
72
73static void
74stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
75 struct clock_event_device *dev)
76{
77}
78
79static struct clock_event_device ckevt_timrot = {
80 .name = "timrot",
81 .features = CLOCK_EVT_FEAT_ONESHOT,
82 .shift = 32,
83 .set_next_event = stmp3xxx_timrot_set_next_event,
84 .set_mode = stmp3xxx_timrot_set_mode,
85};
86
87static struct clocksource cksrc_stmp3xxx = {
88 .name = "cksrc_stmp3xxx",
89 .rating = 250,
90 .read = stmp3xxx_clock_read,
91 .mask = CLOCKSOURCE_MASK(16),
92 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
93};
94
95static struct irqaction stmp3xxx_timer_irq = {
96 .name = "stmp3xxx_timer",
97 .flags = IRQF_DISABLED | IRQF_TIMER,
98 .handler = stmp3xxx_timer_interrupt,
99 .dev_id = &ckevt_timrot,
100};
101
102
103/*
104 * Set up timer interrupt, and return the current time in seconds.
105 */
106static void __init stmp3xxx_init_timer(void)
107{
108 ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
109 ckevt_timrot.shift);
110 ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
111 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
112 ckevt_timrot.cpumask = cpumask_of(0);
113
114 stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
115
116 /* clear two timers */
117 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
118 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
119
120 /* configure them */
121 __raw_writel(
122 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
123 BM_TIMROT_TIMCTRLn_RELOAD |
124 BM_TIMROT_TIMCTRLn_UPDATE |
125 BM_TIMROT_TIMCTRLn_IRQ_EN,
126 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
127 __raw_writel(
128 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
129 BM_TIMROT_TIMCTRLn_RELOAD |
130 BM_TIMROT_TIMCTRLn_UPDATE |
131 BM_TIMROT_TIMCTRLn_IRQ_EN,
132 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
133
134 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
135 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
136 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
137
138 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
139
140 clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
141 clockevents_register_device(&ckevt_timrot);
142}
143
144#ifdef CONFIG_PM
145
146void stmp3xxx_suspend_timer(void)
147{
148 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
149 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
150 stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
151 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
152}
153
154void stmp3xxx_resume_timer(void)
155{
156 stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
157 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
158 __raw_writel(
159 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
160 BM_TIMROT_TIMCTRLn_RELOAD |
161 BM_TIMROT_TIMCTRLn_UPDATE |
162 BM_TIMROT_TIMCTRLn_IRQ_EN,
163 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
164 __raw_writel(
165 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
166 BM_TIMROT_TIMCTRLn_RELOAD |
167 BM_TIMROT_TIMCTRLn_UPDATE |
168 BM_TIMROT_TIMCTRLn_IRQ_EN,
169 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
170 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
171 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
172 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
173}
174
175#else
176
177#define stmp3xxx_suspend_timer NULL
178#define stmp3xxx_resume_timer NULL
179
180#endif /* CONFIG_PM */
181
182struct sys_timer stmp3xxx_timer = {
183 .init = stmp3xxx_init_timer,
184 .suspend = stmp3xxx_suspend_timer,
185 .resume = stmp3xxx_resume_timer,
186};
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 07:16:36 -0400