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-rw-r--r--drivers/gpu/drm/bridge/dw_hdmi.c14
-rw-r--r--drivers/gpu/drm/imx/dw_hdmi-imx.c24
-rw-r--r--drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c14
-rw-r--r--include/drm/bridge/dw_hdmi.h5
4 files changed, 29 insertions, 28 deletions
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 7943cedd63ce..49cafb61d290 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.c
+++ b/drivers/gpu/drm/bridge/dw_hdmi.c
@@ -758,7 +758,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
758 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 758 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
759 const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg; 759 const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg;
760 const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr; 760 const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr;
761 const struct dw_hdmi_sym_term *sym_term = plat_data->sym_term; 761 const struct dw_hdmi_phy_config *phy_config = plat_data->phy_config;
762 762
763 if (prep) 763 if (prep)
764 return -EINVAL; 764 return -EINVAL;
@@ -829,18 +829,18 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
829 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ 829 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
830 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); 830 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
831 831
832 for (i = 0; sym_term[i].mpixelclock != (~0UL); i++) 832 for (i = 0; phy_config[i].mpixelclock != (~0UL); i++)
833 if (hdmi->hdmi_data.video_mode.mpixelclock <= 833 if (hdmi->hdmi_data.video_mode.mpixelclock <=
834 sym_term[i].mpixelclock) 834 phy_config[i].mpixelclock)
835 break; 835 break;
836 836
837 /* RESISTANCE TERM 133Ohm Cfg */ 837 /* RESISTANCE TERM 133Ohm Cfg */
838 hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */ 838 hdmi_phy_i2c_write(hdmi, phy_config[i].term, 0x19); /* TXTERM */
839 /* PREEMP Cgf 0.00 */ 839 /* PREEMP Cgf 0.00 */
840 hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */ 840 hdmi_phy_i2c_write(hdmi, phy_config[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
841
842 /* TX/CK LVL 10 */ 841 /* TX/CK LVL 10 */
843 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */ 842 hdmi_phy_i2c_write(hdmi, phy_config[i].vlev_ctr, 0x0E); /* VLEVCTRL */
843
844 /* REMOVE CLK TERM */ 844 /* REMOVE CLK TERM */
845 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */ 845 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
846 846
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 121d30ca2d44..1032c07773e3 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -73,10 +73,10 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
73 } 73 }
74}; 74};
75 75
76static const struct dw_hdmi_sym_term imx_sym_term[] = { 76static const struct dw_hdmi_phy_config imx_phy_config[] = {
77 /*pixelclk symbol term*/ 77 /*pixelclk symbol term vlev */
78 { 148500000, 0x800d, 0x0005 }, 78 { 148500000, 0x800d, 0x0005, 0x01ad},
79 { ~0UL, 0x0000, 0x0000 } 79 { ~0UL, 0x0000, 0x0000, 0x0000}
80}; 80};
81 81
82static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi) 82static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
@@ -137,17 +137,17 @@ static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
137}; 137};
138 138
139static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { 139static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
140 .mpll_cfg = imx_mpll_cfg, 140 .mpll_cfg = imx_mpll_cfg,
141 .cur_ctr = imx_cur_ctr, 141 .cur_ctr = imx_cur_ctr,
142 .sym_term = imx_sym_term, 142 .phy_config = imx_phy_config,
143 .dev_type = IMX6Q_HDMI, 143 .dev_type = IMX6Q_HDMI,
144}; 144};
145 145
146static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { 146static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
147 .mpll_cfg = imx_mpll_cfg, 147 .mpll_cfg = imx_mpll_cfg,
148 .cur_ctr = imx_cur_ctr, 148 .cur_ctr = imx_cur_ctr,
149 .sym_term = imx_sym_term, 149 .phy_config = imx_phy_config,
150 .dev_type = IMX6DL_HDMI, 150 .dev_type = IMX6DL_HDMI,
151}; 151};
152 152
153static const struct of_device_id dw_hdmi_imx_dt_ids[] = { 153static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index d236faa05b19..65b0f7bf5b52 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -133,12 +133,12 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
133 } 133 }
134}; 134};
135 135
136static const struct dw_hdmi_sym_term rockchip_sym_term[] = { 136static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
137 /*pixelclk symbol term*/ 137 /*pixelclk symbol term vlev*/
138 { 74250000, 0x8009, 0x0004 }, 138 { 74250000, 0x8009, 0x0004, 0x01ad},
139 { 148500000, 0x8029, 0x0004 }, 139 { 148500000, 0x8029, 0x0004, 0x01ad},
140 { 297000000, 0x8039, 0x0005 }, 140 { 297000000, 0x8039, 0x0005, 0x01ad},
141 { ~0UL, 0x0000, 0x0000 } 141 { ~0UL, 0x0000, 0x0000, 0x0000}
142}; 142};
143 143
144static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) 144static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
@@ -230,7 +230,7 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
230 .mode_valid = dw_hdmi_rockchip_mode_valid, 230 .mode_valid = dw_hdmi_rockchip_mode_valid,
231 .mpll_cfg = rockchip_mpll_cfg, 231 .mpll_cfg = rockchip_mpll_cfg,
232 .cur_ctr = rockchip_cur_ctr, 232 .cur_ctr = rockchip_cur_ctr,
233 .sym_term = rockchip_sym_term, 233 .phy_config = rockchip_phy_config,
234 .dev_type = RK3288_HDMI, 234 .dev_type = RK3288_HDMI,
235}; 235};
236 236
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 5a4f49005169..de13bfc35634 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -38,17 +38,18 @@ struct dw_hdmi_curr_ctrl {
38 u16 curr[DW_HDMI_RES_MAX]; 38 u16 curr[DW_HDMI_RES_MAX];
39}; 39};
40 40
41struct dw_hdmi_sym_term { 41struct dw_hdmi_phy_config {
42 unsigned long mpixelclock; 42 unsigned long mpixelclock;
43 u16 sym_ctr; /*clock symbol and transmitter control*/ 43 u16 sym_ctr; /*clock symbol and transmitter control*/
44 u16 term; /*transmission termination value*/ 44 u16 term; /*transmission termination value*/
45 u16 vlev_ctr; /* voltage level control */
45}; 46};
46 47
47struct dw_hdmi_plat_data { 48struct dw_hdmi_plat_data {
48 enum dw_hdmi_devtype dev_type; 49 enum dw_hdmi_devtype dev_type;
49 const struct dw_hdmi_mpll_config *mpll_cfg; 50 const struct dw_hdmi_mpll_config *mpll_cfg;
50 const struct dw_hdmi_curr_ctrl *cur_ctr; 51 const struct dw_hdmi_curr_ctrl *cur_ctr;
51 const struct dw_hdmi_sym_term *sym_term; 52 const struct dw_hdmi_phy_config *phy_config;
52 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, 53 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
53 struct drm_display_mode *mode); 54 struct drm_display_mode *mode);
54}; 55};