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-rw-r--r--arch/arm/mach-bcm/Makefile2
-rw-r--r--arch/arm/mach-bcm/brcmstb.h19
-rw-r--r--arch/arm/mach-bcm/headsmp-brcmstb.S33
-rw-r--r--arch/arm/mach-bcm/platsmp-brcmstb.c4
-rw-r--r--arch/arm/mach-berlin/headsmp.S6
-rw-r--r--arch/arm/mach-berlin/platsmp.c3
-rw-r--r--arch/arm/mach-hisi/Makefile2
-rw-r--r--arch/arm/mach-hisi/core.h1
-rw-r--r--arch/arm/mach-hisi/headsmp.S16
-rw-r--r--arch/arm/mach-hisi/platsmp.c4
-rw-r--r--arch/arm/mach-imx/headsmp.S1
-rw-r--r--arch/arm/mach-mvebu/headsmp-a9.S1
-rw-r--r--arch/arm/mach-prima2/headsmp.S1
-rw-r--r--arch/arm/mach-rockchip/core.h1
-rw-r--r--arch/arm/mach-rockchip/headsmp.S8
-rw-r--r--arch/arm/mach-rockchip/platsmp.c5
-rw-r--r--arch/arm/mach-shmobile/common.h1
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S4
-rw-r--r--arch/arm/mach-shmobile/headsmp.S7
-rw-r--r--arch/arm/mach-shmobile/platsmp-apmu.c2
-rw-r--r--arch/arm/mach-socfpga/core.h1
-rw-r--r--arch/arm/mach-socfpga/headsmp.S5
-rw-r--r--arch/arm/mach-socfpga/platsmp.c2
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/headsmp.S12
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/reset.h1
-rw-r--r--arch/arm/mach-zynq/common.h2
-rw-r--r--arch/arm/mach-zynq/headsmp.S5
-rw-r--r--arch/arm/mach-zynq/platsmp.c5
-rw-r--r--arch/arm/mm/proc-v7.S2
31 files changed, 17 insertions, 143 deletions
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 4c38674c73ec..54d274da7ccb 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
43ifeq ($(CONFIG_ARCH_BRCMSTB),y) 43ifeq ($(CONFIG_ARCH_BRCMSTB),y)
44CFLAGS_platsmp-brcmstb.o += -march=armv7-a 44CFLAGS_platsmp-brcmstb.o += -march=armv7-a
45obj-y += brcmstb.o 45obj-y += brcmstb.o
46obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o 46obj-$(CONFIG_SMP) += platsmp-brcmstb.o
47endif 47endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index ec0c3d112b36..000000000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2013-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __BRCMSTB_H__
15#define __BRCMSTB_H__
16
17void brcmstb_secondary_startup(void);
18
19#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea58248..000000000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * SMP boot code for secondary CPUs
3 * Based on arch/arm/mach-tegra/headsmp.S
4 *
5 * Copyright (C) 2010 NVIDIA, Inc.
6 * Copyright (C) 2013-2014 Broadcom Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <asm/assembler.h>
19#include <linux/linkage.h>
20#include <linux/init.h>
21
22 .section ".text.head", "ax"
23
24ENTRY(brcmstb_secondary_startup)
25 /*
26 * Ensure CPU is in a sane state by disabling all IRQs and switching
27 * into SVC mode.
28 */
29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
30
31 bl v7_invalidate_l1
32 b secondary_startup
33ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index e209e6fc7caf..44d6bddf7a4e 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -30,8 +30,6 @@
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31#include <asm/smp_plat.h> 31#include <asm/smp_plat.h>
32 32
33#include "brcmstb.h"
34
35enum { 33enum {
36 ZONE_MAN_CLKEN_MASK = BIT(0), 34 ZONE_MAN_CLKEN_MASK = BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK = BIT(1), 35 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
153 * Set the reset vector to point to the secondary_startup 151 * Set the reset vector to point to the secondary_startup
154 * routine 152 * routine
155 */ 153 */
156 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); 154 cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
157 155
158 /* Unhalt the cpu */ 156 /* Unhalt the cpu */
159 cpu_rst_cfg_set(cpu, 0); 157 cpu_rst_cfg_set(cpu, 0);
diff --git a/arch/arm/mach-berlin/headsmp.S b/arch/arm/mach-berlin/headsmp.S
index 4a4c56a58ad3..dc82a3486b05 100644
--- a/arch/arm/mach-berlin/headsmp.S
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -12,12 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14 14
15ENTRY(berlin_secondary_startup)
16 ARM_BE8(setend be)
17 bl v7_invalidate_l1
18 b secondary_startup
19ENDPROC(berlin_secondary_startup)
20
21/* 15/*
22 * If the following instruction is set in the reset exception vector, CPUs 16 * If the following instruction is set in the reset exception vector, CPUs
23 * will fetch the value of the software reset address vector when being 17 * will fetch the value of the software reset address vector when being
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 702e7982015a..34a3753e7356 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -22,7 +22,6 @@
22#define RESET_VECT 0x00 22#define RESET_VECT 0x00
23#define SW_RESET_ADDR 0x94 23#define SW_RESET_ADDR 0x94
24 24
25extern void berlin_secondary_startup(void);
26extern u32 boot_inst; 25extern u32 boot_inst;
27 26
28static void __iomem *cpu_ctrl; 27static void __iomem *cpu_ctrl;
@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
85 * Write the secondary startup address into the SW reset address 84 * Write the secondary startup address into the SW reset address
86 * vector. This is used by boot_inst. 85 * vector. This is used by boot_inst.
87 */ 86 */
88 writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR); 87 writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
89 88
90 iounmap(vectors_base); 89 iounmap(vectors_base);
91unmap_scu: 90unmap_scu:
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index 6b7b3033de0b..659db1933ed3 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
6 6
7obj-y += hisilicon.o 7obj-y += hisilicon.o
8obj-$(CONFIG_MCPM) += platmcpm.o 8obj-$(CONFIG_MCPM) += platmcpm.o
9obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 92a682d8e939..c7648ef1825c 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
12extern int hi3xxx_cpu_kill(unsigned int cpu); 12extern int hi3xxx_cpu_kill(unsigned int cpu);
13extern void hi3xxx_set_cpu(int cpu, bool enable); 13extern void hi3xxx_set_cpu(int cpu, bool enable);
14 14
15extern void hisi_secondary_startup(void);
16extern struct smp_operations hix5hd2_smp_ops; 15extern struct smp_operations hix5hd2_smp_ops;
17extern void hix5hd2_set_cpu(int cpu, bool enable); 16extern void hix5hd2_set_cpu(int cpu, bool enable);
18extern void hix5hd2_cpu_die(unsigned int cpu); 17extern void hix5hd2_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
deleted file mode 100644
index 81e35b159e75..000000000000
--- a/arch/arm/mach-hisi/headsmp.S
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (c) 2014 Hisilicon Limited.
3 * Copyright (c) 2014 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/linkage.h>
10#include <linux/init.h>
11
12 __CPUINIT
13
14ENTRY(hisi_secondary_startup)
15 bl v7_invalidate_l1
16 b secondary_startup
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 8880c8e8b296..51744127db66 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
118{ 118{
119 phys_addr_t jumpaddr; 119 phys_addr_t jumpaddr;
120 120
121 jumpaddr = virt_to_phys(hisi_secondary_startup); 121 jumpaddr = virt_to_phys(secondary_startup);
122 hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); 122 hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
123 hix5hd2_set_cpu(cpu, true); 123 hix5hd2_set_cpu(cpu, true);
124 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 124 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
156 struct device_node *node; 156 struct device_node *node;
157 157
158 158
159 jumpaddr = virt_to_phys(hisi_secondary_startup); 159 jumpaddr = virt_to_phys(secondary_startup);
160 hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr); 160 hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
161 161
162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); 162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index de5047c8a6c8..b5e976816b63 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -25,7 +25,6 @@ diag_reg_offset:
25 .endm 25 .endm
26 26
27ENTRY(v7_secondary_startup) 27ENTRY(v7_secondary_startup)
28 bl v7_invalidate_l1
29 set_diag_reg 28 set_diag_reg
30 b secondary_startup 29 b secondary_startup
31ENDPROC(v7_secondary_startup) 30ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 08d5ed46b996..48e4c4b3cd1c 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -21,7 +21,6 @@
21 21
22ENTRY(mvebu_cortex_a9_secondary_startup) 22ENTRY(mvebu_cortex_a9_secondary_startup)
23ARM_BE8(setend be) 23ARM_BE8(setend be)
24 bl v7_invalidate_l1
25 bl armada_38x_scu_power_up 24 bl armada_38x_scu_power_up
26 b secondary_startup 25 b secondary_startup
27ENDPROC(mvebu_cortex_a9_secondary_startup) 26ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index d86fe33c5f53..209d9fc5c16c 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -15,7 +15,6 @@
15 * ready for them to initialise. 15 * ready for them to initialise.
16 */ 16 */
17ENTRY(sirfsoc_secondary_startup) 17ENTRY(sirfsoc_secondary_startup)
18 bl v7_invalidate_l1
19 mrc p15, 0, r0, c0, c0, 5 18 mrc p15, 0, r0, c0, c0, 5
20 and r0, r0, #15 19 and r0, r0, #15
21 adr r4, 1f 20 adr r4, 1f
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index 39bca96b555a..492c048813da 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
17extern char rockchip_secondary_trampoline_end; 17extern char rockchip_secondary_trampoline_end;
18 18
19extern unsigned long rockchip_boot_fn; 19extern unsigned long rockchip_boot_fn;
20extern void rockchip_secondary_startup(void);
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 46c22dedf632..d69708b07282 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -15,14 +15,6 @@
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18ENTRY(rockchip_secondary_startup)
19 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
20 ldr r1, =0x00000c09 @ Cortex-A9 primary part number
21 teq r0, r1
22 beq v7_invalidate_l1
23 b secondary_startup
24ENDPROC(rockchip_secondary_startup)
25
26ENTRY(rockchip_secondary_trampoline) 18ENTRY(rockchip_secondary_trampoline)
27 ldr pc, 1f 19 ldr pc, 1f
28ENDPROC(rockchip_secondary_trampoline) 20ENDPROC(rockchip_secondary_trampoline)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5b4ca3c3c879..2e6ab67e2284 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
149 * sram_base_addr + 8: start address for pc 149 * sram_base_addr + 8: start address for pc
150 * */ 150 * */
151 udelay(10); 151 udelay(10);
152 writel(virt_to_phys(rockchip_secondary_startup), 152 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
153 sram_base_addr + 8);
154 writel(0xDEADBEAF, sram_base_addr + 4); 153 writel(0xDEADBEAF, sram_base_addr + 4);
155 dsb_sev(); 154 dsb_sev();
156 } 155 }
@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
189 } 188 }
190 189
191 /* set the boot function for the sram code */ 190 /* set the boot function for the sram code */
192 rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); 191 rockchip_boot_fn = virt_to_phys(secondary_startup);
193 192
194 /* copy the trampoline to sram, that runs during startup of the core */ 193 /* copy the trampoline to sram, that runs during startup of the core */
195 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); 194 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index afc60bad6fd6..476092b86c6e 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
14extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, 14extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
15 unsigned long arg); 15 unsigned long arg);
16extern int shmobile_smp_cpu_disable(unsigned int cpu); 16extern int shmobile_smp_cpu_disable(unsigned int cpu);
17extern void shmobile_invalidate_start(void);
18extern void shmobile_boot_scu(void); 17extern void shmobile_boot_scu(void);
19extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); 18extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
20extern void shmobile_smp_scu_cpu_die(unsigned int cpu); 19extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 69df8bfac167..fa5248c52399 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -22,7 +22,7 @@
22 * Boot code for secondary CPUs. 22 * Boot code for secondary CPUs.
23 * 23 *
24 * First we turn on L1 cache coherency for our CPU. Then we jump to 24 * First we turn on L1 cache coherency for our CPU. Then we jump to
25 * shmobile_invalidate_start that invalidates the cache and hands over control 25 * secondary_startup that invalidates the cache and hands over control
26 * to the common ARM startup code. 26 * to the common ARM startup code.
27 */ 27 */
28ENTRY(shmobile_boot_scu) 28ENTRY(shmobile_boot_scu)
@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
37 str r2, [r0, #8] @ write back 37 str r2, [r0, #8] @ write back
38 38
39 b shmobile_invalidate_start 39 b secondary_startup
40ENDPROC(shmobile_boot_scu) 40ENDPROC(shmobile_boot_scu)
41 41
42 .text 42 .text
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 50c491567e11..330c1fc63197 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,13 +16,6 @@
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/memory.h> 17#include <asm/memory.h>
18 18
19#ifdef CONFIG_SMP
20ENTRY(shmobile_invalidate_start)
21 bl v7_invalidate_l1
22 b secondary_startup
23ENDPROC(shmobile_invalidate_start)
24#endif
25
26/* 19/*
27 * Reset vector for secondary CPUs. 20 * Reset vector for secondary CPUs.
28 * This will be mapped at address 0 by SBAR register. 21 * This will be mapped at address 0 by SBAR register.
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index f483b560b066..b0790fc32282 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
133int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) 133int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
134{ 134{
135 /* For this particular CPU register boot vector */ 135 /* For this particular CPU register boot vector */
136 shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); 136 shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
137 137
138 return apmu_wrap(cpu, apmu_power_on); 138 return apmu_wrap(cpu, apmu_power_on);
139} 139}
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index a0f3b1cd497c..767c09e954a0 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -31,7 +31,6 @@
31 31
32#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 32#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
33 33
34extern void socfpga_secondary_startup(void);
35extern void __iomem *socfpga_scu_base_addr; 34extern void __iomem *socfpga_scu_base_addr;
36 35
37extern void socfpga_init_clocks(void); 36extern void socfpga_init_clocks(void);
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f65ea0af4af3..5bb016427107 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
301: .long . 301: .long .
31 .long socfpga_cpu1start_addr 31 .long socfpga_cpu1start_addr
32ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
33
34ENTRY(socfpga_secondary_startup)
35 bl v7_invalidate_l1
36 b secondary_startup
37ENDPROC(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index c64d89b7c0ca..79c5336c569f 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
40 40
41 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 41 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
42 42
43 writel(virt_to_phys(socfpga_secondary_startup), 43 writel(virt_to_phys(secondary_startup),
44 sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); 44 sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
45 45
46 flush_cache_all(); 46 flush_cache_all();
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e48a74458c25..fffad2426ee4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
19ifeq ($(CONFIG_CPU_IDLE),y) 19ifeq ($(CONFIG_CPU_IDLE),y)
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o 20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
21endif 21endif
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 22obj-$(CONFIG_SMP) += platsmp.o
23obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 23obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
24 24
25obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o 25obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
deleted file mode 100644
index 2072e7322c39..000000000000
--- a/arch/arm/mach-tegra/headsmp.S
+++ /dev/null
@@ -1,12 +0,0 @@
1#include <linux/linkage.h>
2#include <linux/init.h>
3
4#include "sleep.h"
5
6 .section ".text.head", "ax"
7
8ENTRY(tegra_secondary_startup)
9 check_cpu_part_num 0xc09, r8, r9
10 bleq v7_invalidate_l1
11 b secondary_startup
12ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 894c5c472184..6fd9db54887e 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
95 *((u32 *)cpu_possible_mask); 95 *((u32 *)cpu_possible_mask);
96 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 96 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
97 virt_to_phys((void *)tegra_secondary_startup); 97 virt_to_phys((void *)secondary_startup);
98#endif 98#endif
99 99
100#ifdef CONFIG_PM_SLEEP 100#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index 76a93434c6ee..0aee0129f8d7 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
36void __tegra_cpu_reset_handler_start(void); 36void __tegra_cpu_reset_handler_start(void);
37void __tegra_cpu_reset_handler(void); 37void __tegra_cpu_reset_handler(void);
38void __tegra_cpu_reset_handler_end(void); 38void __tegra_cpu_reset_handler_end(void);
39void tegra_secondary_startup(void);
40 39
41#ifdef CONFIG_PM_SLEEP 40#ifdef CONFIG_PM_SLEEP
42#define tegra_cpu_lp1_mask \ 41#define tegra_cpu_lp1_mask \
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 382c60e9aa16..7038cae95ddc 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
17#ifndef __MACH_ZYNQ_COMMON_H__ 17#ifndef __MACH_ZYNQ_COMMON_H__
18#define __MACH_ZYNQ_COMMON_H__ 18#define __MACH_ZYNQ_COMMON_H__
19 19
20void zynq_secondary_startup(void);
21
22extern int zynq_slcr_init(void); 20extern int zynq_slcr_init(void);
23extern int zynq_early_slcr_init(void); 21extern int zynq_early_slcr_init(void);
24extern void zynq_slcr_system_reset(void); 22extern void zynq_slcr_system_reset(void);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index dd8c071941e7..045c72720a4d 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
22.globl zynq_secondary_trampoline_end 22.globl zynq_secondary_trampoline_end
23zynq_secondary_trampoline_end: 23zynq_secondary_trampoline_end:
24ENDPROC(zynq_secondary_trampoline) 24ENDPROC(zynq_secondary_trampoline)
25
26ENTRY(zynq_secondary_startup)
27 bl v7_invalidate_l1
28 b secondary_startup
29ENDPROC(zynq_secondary_startup)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 52d768ff7857..f66816c49186 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
87} 87}
88EXPORT_SYMBOL(zynq_cpun_start); 88EXPORT_SYMBOL(zynq_cpun_start);
89 89
90static int zynq_boot_secondary(unsigned int cpu, 90static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
91 struct task_struct *idle)
92{ 91{
93 return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); 92 return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
94} 93}
95 94
96/* 95/*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3d1054f11a8a..75ae72160099 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -336,7 +336,7 @@ __v7_pj4b_setup:
336__v7_setup: 336__v7_setup:
337 adr r12, __v7_setup_stack @ the local stack 337 adr r12, __v7_setup_stack @ the local stack
338 stmia r12, {r0-r5, r7, r9, r11, lr} 338 stmia r12, {r0-r5, r7, r9, r11, lr}
339 bl v7_flush_dcache_louis 339 bl v7_invalidate_l1
340 ldmia r12, {r0-r5, r7, r9, r11, lr} 340 ldmia r12, {r0-r5, r7, r9, r11, lr}
341 341
342 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 342 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 15:12:00 -0400