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-rw-r--r--drivers/clk/renesas/r7s9210-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a774a1-cpg-mssr.c18
-rw-r--r--drivers/clk/renesas/r8a774c0-cpg-mssr.c7
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c41
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c35
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c33
-rw-r--r--drivers/clk/renesas/r8a77980-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c25
-rw-r--r--drivers/clk/renesas/r8a77995-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c1
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c70
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h5
-rw-r--r--include/linux/math64.h13
13 files changed, 137 insertions, 118 deletions
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 57c49fe88295..cf65d4e0e116 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -11,6 +11,7 @@
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/io.h>
14#include <dt-bindings/clock/r7s9210-cpg-mssr.h> 15#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
15#include "renesas-cpg-mssr.h" 16#include "renesas-cpg-mssr.h"
16 17
@@ -119,7 +120,7 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk,
119 if (clk_get_rate(extal_clk) > 12000000) 120 if (clk_get_rate(extal_clk) > 12000000)
120 cpg_mode = 1; 121 cpg_mode = 1;
121 122
122 frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF; 123 frqcr = readl(base + CPG_FRQCR) & 0xFFF;
123 if (frqcr == 0x012) 124 if (frqcr == 0x012)
124 index = 0; 125 index = 0;
125 else if (frqcr == 0x112) 126 else if (frqcr == 0x112)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 4d92b27a6153..76ed7d1bae36 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72 72
73 /* Core Clock Outputs */ 73 /* Core Clock Outputs */
74 DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 74 DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
75 DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 75 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
76 DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 76 DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
77 DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 77 DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
78 DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 78 DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
123 DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO), 123 DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
124 DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO), 124 DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
125 DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO), 125 DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
126 DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3), 126 DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1),
127 DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3), 127 DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1),
128 DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3), 128 DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
129 DEF_MOD("cmt3", 300, R8A774A1_CLK_R), 129 DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
130 DEF_MOD("cmt2", 301, R8A774A1_CLK_R), 130 DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
143 DEF_MOD("rwdt", 402, R8A774A1_CLK_R), 143 DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
144 DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP), 144 DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
145 DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3), 145 DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
146 DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3), 146 DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2),
147 DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3), 147 DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2),
148 DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1), 148 DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
149 DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1), 149 DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
150 DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1), 150 DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
@@ -165,9 +165,9 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
165 DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2), 165 DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
166 DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1), 166 DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
167 DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1), 167 DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
168 DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4), 168 DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
169 DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4), 169 DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
170 DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4), 170 DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D2),
171 DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0), 171 DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
172 DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0), 172 DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
173 DEF_MOD("du2", 722, R8A774A1_CLK_S2D1), 173 DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 34e274f2a273..f91e7a484753 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
81 /* Core Clock Outputs */ 81 /* Core Clock Outputs */
82 DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), 82 DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
83 DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), 83 DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
84 DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
84 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), 85 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
85 DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), 86 DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
86 DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), 87 DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
@@ -157,7 +158,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
157 DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP), 158 DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
158 DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3), 159 DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
159 160
160 DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4), 161 DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
161 DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C), 162 DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
162 DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C), 163 DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
163 DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C), 164 DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
@@ -177,8 +178,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
177 DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1), 178 DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
178 DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1), 179 DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
179 180
180 DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4), 181 DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
181 DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4), 182 DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
182 DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0), 183 DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
183 DEF_MOD("du1", 723, R8A774C0_CLK_S1D1), 184 DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
184 DEF_MOD("du0", 724, R8A774C0_CLK_S1D1), 185 DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 86842c9fd314..9e9a6f2c31e8 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -3,6 +3,7 @@
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
4 * 4 *
5 * Copyright (C) 2015 Glider bvba 5 * Copyright (C) 2015 Glider bvba
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 * 7 *
7 * Based on clk-rcar-gen3.c 8 * Based on clk-rcar-gen3.c
8 * 9 *
@@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
73 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 74 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74 75
75 /* Core Clock Outputs */ 76 /* Core Clock Outputs */
76 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 77 DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
77 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 78 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
78 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 79 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
79 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 80 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
80 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 81 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -129,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
129 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 130 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
130 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 131 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
131 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 132 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
132 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), 133 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
133 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), 134 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
134 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), 135 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
135 DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR), 136 DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
136 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 137 DEF_MOD("cmt3", 300, R8A7795_CLK_R),
@@ -153,16 +154,16 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
153 DEF_MOD("rwdt", 402, R8A7795_CLK_R), 154 DEF_MOD("rwdt", 402, R8A7795_CLK_R),
154 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 155 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
155 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3), 156 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
156 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), 157 DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
157 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), 158 DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
158 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 159 DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
159 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), 160 DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
160 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), 161 DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
161 DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), 162 DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
162 DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), 163 DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
163 DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), 164 DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
164 DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), 165 DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
165 DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), 166 DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
166 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 167 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
167 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 168 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
168 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 169 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
@@ -194,12 +195,12 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
194 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ 195 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
195 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), 196 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
196 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), 197 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
197 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), 198 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
198 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 199 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
199 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 200 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
200 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 201 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
201 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 202 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
202 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), 203 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
203 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ 204 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
204 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 205 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
205 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 206 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 12c455859f2c..d8e9af5d9ae9 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -3,6 +3,7 @@
3 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
4 * 4 *
5 * Copyright (C) 2016 Glider bvba 5 * Copyright (C) 2016 Glider bvba
6 * Copyright (C) 2018 Renesas Electronics Corp.
6 * 7 *
7 * Based on r8a7795-cpg-mssr.c 8 * Based on r8a7795-cpg-mssr.c
8 * 9 *
@@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
73 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 74 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74 75
75 /* Core Clock Outputs */ 76 /* Core Clock Outputs */
76 DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 77 DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
77 DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 78 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
78 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 79 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
79 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 80 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
80 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 81 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -126,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
126 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), 127 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
127 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), 128 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
128 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), 129 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
129 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), 130 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
130 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), 131 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
131 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), 132 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
132 DEF_MOD("cmt3", 300, R8A7796_CLK_R), 133 DEF_MOD("cmt3", 300, R8A7796_CLK_R),
133 DEF_MOD("cmt2", 301, R8A7796_CLK_R), 134 DEF_MOD("cmt2", 301, R8A7796_CLK_R),
@@ -146,16 +147,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
146 DEF_MOD("rwdt", 402, R8A7796_CLK_R), 147 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
147 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), 148 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
148 DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3), 149 DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
149 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), 150 DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
150 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), 151 DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
151 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), 152 DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
152 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), 153 DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
153 DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), 154 DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
154 DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), 155 DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
155 DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), 156 DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
156 DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), 157 DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
157 DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), 158 DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
158 DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), 159 DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
159 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), 160 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
160 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), 161 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
161 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), 162 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
@@ -176,9 +177,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
176 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), 177 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
177 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), 178 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
178 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), 179 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
179 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), 180 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
180 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), 181 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
181 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), 182 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
182 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), 183 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
183 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), 184 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
184 DEF_MOD("du2", 722, R8A7796_CLK_S2D1), 185 DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index eb1cca58a1e1..8f87e314d949 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -3,6 +3,7 @@
3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
4 * 4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2019 Renesas Electronics Corp.
6 * 7 *
7 * Based on r8a7795-cpg-mssr.c 8 * Based on r8a7795-cpg-mssr.c
8 * 9 *
@@ -71,7 +72,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 72 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72 73
73 /* Core Clock Outputs */ 74 /* Core Clock Outputs */
74 DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 75 DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
75 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 76 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
76 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 77 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
77 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 78 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,8 +124,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
123 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO), 124 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
124 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO), 125 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
125 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO), 126 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
126 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), 127 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
127 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), 128 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
128 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), 129 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
129 130
130 DEF_MOD("cmt3", 300, R8A77965_CLK_R), 131 DEF_MOD("cmt3", 300, R8A77965_CLK_R),
@@ -146,16 +147,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
146 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), 147 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
147 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3), 148 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
148 149
149 DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3), 150 DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
150 DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3), 151 DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
151 DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), 152 DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
152 DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), 153 DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
153 DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), 154 DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
154 DEF_MOD("drif4", 511, R8A77965_CLK_S3D2), 155 DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
155 DEF_MOD("drif3", 512, R8A77965_CLK_S3D2), 156 DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
156 DEF_MOD("drif2", 513, R8A77965_CLK_S3D2), 157 DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
157 DEF_MOD("drif1", 514, R8A77965_CLK_S3D2), 158 DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
158 DEF_MOD("drif0", 515, R8A77965_CLK_S3D2), 159 DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
159 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1), 160 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
160 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1), 161 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
161 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1), 162 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
@@ -175,9 +176,9 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
175 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1), 176 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
176 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1), 177 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
177 178
178 DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), 179 DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
179 DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), 180 DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
180 DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), 181 DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
181 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), 182 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
182 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), 183 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
183 DEF_MOD("du3", 721, R8A77965_CLK_S2D1), 184 DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index f9e07fcc0d96..7227f675e61f 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
171 DEF_MOD("gpio1", 911, R8A77980_CLK_CP), 171 DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
172 DEF_MOD("gpio0", 912, R8A77980_CLK_CP), 172 DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
173 DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), 173 DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
174 DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC), 174 DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
175 DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), 175 DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
176 DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), 176 DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
177 DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), 177 DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9a278c75c918..9570404baa58 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -2,7 +2,7 @@
2/* 2/*
3 * r8a77990 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp. 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 * 6 *
7 * Based on r8a7795-cpg-mssr.c 7 * Based on r8a7795-cpg-mssr.c
8 * 8 *
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
81 /* Core Clock Outputs */ 81 /* Core Clock Outputs */
82 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), 82 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
83 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), 83 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
84 DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
84 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), 85 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
85 DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), 86 DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
86 DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), 87 DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
@@ -152,15 +153,15 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
152 DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), 153 DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
153 DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3), 154 DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
154 155
155 DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), 156 DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
156 DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), 157 DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
157 DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), 158 DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
158 DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), 159 DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
159 DEF_MOD("drif4", 511, R8A77990_CLK_S3D2), 160 DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
160 DEF_MOD("drif3", 512, R8A77990_CLK_S3D2), 161 DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
161 DEF_MOD("drif2", 513, R8A77990_CLK_S3D2), 162 DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
162 DEF_MOD("drif1", 514, R8A77990_CLK_S3D2), 163 DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
163 DEF_MOD("drif0", 515, R8A77990_CLK_S3D2), 164 DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
164 DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C), 165 DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
165 DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C), 166 DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
166 DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C), 167 DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
@@ -180,8 +181,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
180 DEF_MOD("vspb", 626, R8A77990_CLK_S0D1), 181 DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
181 DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1), 182 DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
182 183
183 DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), 184 DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
184 DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), 185 DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
185 DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), 186 DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
186 DEF_MOD("du1", 723, R8A77990_CLK_S1D1), 187 DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
187 DEF_MOD("du0", 724, R8A77990_CLK_S1D1), 188 DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index eee3874865a9..68707277b17b 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
133 DEF_MOD("rwdt", 402, R8A77995_CLK_R), 133 DEF_MOD("rwdt", 402, R8A77995_CLK_R),
134 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), 134 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
135 DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2), 135 DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
136 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), 136 DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
137 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), 137 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
138 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), 138 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
139 DEF_MOD("thermal", 522, R8A77995_CLK_CP), 139 DEF_MOD("thermal", 522, R8A77995_CLK_CP),
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 658cb11b6f55..97c72477cd54 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -170,6 +170,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
170 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), 170 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
171 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), 171 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
172 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), 172 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
173 D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
173 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), 174 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
174 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), 175 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
175 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0), 176 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 9a8071a8114d..dc62ed0dadc2 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -3,6 +3,7 @@
3 * R-Car Gen3 Clock Pulse Generator 3 * R-Car Gen3 Clock Pulse Generator
4 * 4 *
5 * Copyright (C) 2015-2018 Glider bvba 5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2019 Renesas Electronics Corp.
6 * 7 *
7 * Based on clk-rcar-gen3.c 8 * Based on clk-rcar-gen3.c
8 * 9 *
@@ -88,14 +89,13 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
88#define CPG_FRQCRB 0x00000004 89#define CPG_FRQCRB 0x00000004
89#define CPG_FRQCRB_KICK BIT(31) 90#define CPG_FRQCRB_KICK BIT(31)
90#define CPG_FRQCRC 0x000000e0 91#define CPG_FRQCRC 0x000000e0
91#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
92#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
93 92
94struct cpg_z_clk { 93struct cpg_z_clk {
95 struct clk_hw hw; 94 struct clk_hw hw;
96 void __iomem *reg; 95 void __iomem *reg;
97 void __iomem *kick_reg; 96 void __iomem *kick_reg;
98 unsigned long mask; 97 unsigned long mask;
98 unsigned int fixed_div;
99}; 99};
100 100
101#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 101#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
@@ -110,17 +110,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
110 val = readl(zclk->reg) & zclk->mask; 110 val = readl(zclk->reg) & zclk->mask;
111 mult = 32 - (val >> __ffs(zclk->mask)); 111 mult = 32 - (val >> __ffs(zclk->mask));
112 112
113 /* Factor of 2 is for fixed divider */ 113 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
114 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); 114 32 * zclk->fixed_div);
115} 115}
116 116
117static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, 117static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
118 unsigned long *parent_rate) 118 unsigned long *parent_rate)
119{ 119{
120 /* Factor of 2 is for fixed divider */ 120 struct cpg_z_clk *zclk = to_z_clk(hw);
121 unsigned long prate = *parent_rate / 2; 121 unsigned long prate;
122 unsigned int mult; 122 unsigned int mult;
123 123
124 prate = *parent_rate / zclk->fixed_div;
124 mult = div_u64(rate * 32ULL, prate); 125 mult = div_u64(rate * 32ULL, prate);
125 mult = clamp(mult, 1U, 32U); 126 mult = clamp(mult, 1U, 32U);
126 127
@@ -134,8 +135,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
134 unsigned int mult; 135 unsigned int mult;
135 unsigned int i; 136 unsigned int i;
136 137
137 /* Factor of 2 is for fixed divider */ 138 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
138 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); 139 parent_rate);
139 mult = clamp(mult, 1U, 32U); 140 mult = clamp(mult, 1U, 32U);
140 141
141 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 142 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
@@ -178,7 +179,8 @@ static const struct clk_ops cpg_z_clk_ops = {
178static struct clk * __init cpg_z_clk_register(const char *name, 179static struct clk * __init cpg_z_clk_register(const char *name,
179 const char *parent_name, 180 const char *parent_name,
180 void __iomem *reg, 181 void __iomem *reg,
181 unsigned long mask) 182 unsigned int div,
183 unsigned int offset)
182{ 184{
183 struct clk_init_data init; 185 struct clk_init_data init;
184 struct cpg_z_clk *zclk; 186 struct cpg_z_clk *zclk;
@@ -197,7 +199,8 @@ static struct clk * __init cpg_z_clk_register(const char *name,
197 zclk->reg = reg + CPG_FRQCRC; 199 zclk->reg = reg + CPG_FRQCRC;
198 zclk->kick_reg = reg + CPG_FRQCRB; 200 zclk->kick_reg = reg + CPG_FRQCRB;
199 zclk->hw.init = &init; 201 zclk->hw.init = &init;
200 zclk->mask = mask; 202 zclk->mask = GENMASK(offset + 4, offset);
203 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
201 204
202 clk = clk_register(NULL, &zclk->hw); 205 clk = clk_register(NULL, &zclk->hw);
203 if (IS_ERR(clk)) 206 if (IS_ERR(clk))
@@ -234,8 +237,6 @@ struct sd_clock {
234 const struct sd_div_table *div_table; 237 const struct sd_div_table *div_table;
235 struct cpg_simple_notifier csn; 238 struct cpg_simple_notifier csn;
236 unsigned int div_num; 239 unsigned int div_num;
237 unsigned int div_min;
238 unsigned int div_max;
239 unsigned int cur_div_idx; 240 unsigned int cur_div_idx;
240}; 241};
241 242
@@ -312,14 +313,20 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
312 unsigned long rate, 313 unsigned long rate,
313 unsigned long parent_rate) 314 unsigned long parent_rate)
314{ 315{
315 unsigned int div; 316 unsigned long calc_rate, diff, diff_min = ULONG_MAX;
316 317 unsigned int i, best_div = 0;
317 if (!rate) 318
318 rate = 1; 319 for (i = 0; i < clock->div_num; i++) {
319 320 calc_rate = DIV_ROUND_CLOSEST(parent_rate,
320 div = DIV_ROUND_CLOSEST(parent_rate, rate); 321 clock->div_table[i].div);
322 diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
323 if (diff < diff_min) {
324 best_div = clock->div_table[i].div;
325 diff_min = diff;
326 }
327 }
321 328
322 return clamp_t(unsigned int, div, clock->div_min, clock->div_max); 329 return best_div;
323} 330}
324 331
325static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, 332static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -369,8 +376,8 @@ static u32 cpg_quirks __initdata;
369#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ 376#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
370#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ 377#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
371 378
372static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 379static struct clk * __init cpg_sd_clk_register(const char *name,
373 void __iomem *base, const char *parent_name, 380 void __iomem *base, unsigned int offset, const char *parent_name,
374 struct raw_notifier_head *notifiers) 381 struct raw_notifier_head *notifiers)
375{ 382{
376 struct clk_init_data init; 383 struct clk_init_data init;
@@ -383,13 +390,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
383 if (!clock) 390 if (!clock)
384 return ERR_PTR(-ENOMEM); 391 return ERR_PTR(-ENOMEM);
385 392
386 init.name = core->name; 393 init.name = name;
387 init.ops = &cpg_sd_clock_ops; 394 init.ops = &cpg_sd_clock_ops;
388 init.flags = CLK_SET_RATE_PARENT; 395 init.flags = CLK_SET_RATE_PARENT;
389 init.parent_names = &parent_name; 396 init.parent_names = &parent_name;
390 init.num_parents = 1; 397 init.num_parents = 1;
391 398
392 clock->csn.reg = base + core->offset; 399 clock->csn.reg = base + offset;
393 clock->hw.init = &init; 400 clock->hw.init = &init;
394 clock->div_table = cpg_sd_div_table; 401 clock->div_table = cpg_sd_div_table;
395 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 402 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
@@ -403,13 +410,6 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
403 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); 410 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
404 writel(val, clock->csn.reg); 411 writel(val, clock->csn.reg);
405 412
406 clock->div_max = clock->div_table[0].div;
407 clock->div_min = clock->div_max;
408 for (i = 1; i < clock->div_num; i++) {
409 clock->div_max = max(clock->div_max, clock->div_table[i].div);
410 clock->div_min = min(clock->div_min, clock->div_table[i].div);
411 }
412
413 clk = clk_register(NULL, &clock->hw); 413 clk = clk_register(NULL, &clock->hw);
414 if (IS_ERR(clk)) 414 if (IS_ERR(clk))
415 goto free_clock; 415 goto free_clock;
@@ -606,8 +606,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
606 break; 606 break;
607 607
608 case CLK_TYPE_GEN3_SD: 608 case CLK_TYPE_GEN3_SD:
609 return cpg_sd_clk_register(core, base, __clk_get_name(parent), 609 return cpg_sd_clk_register(core->name, base, core->offset,
610 notifiers); 610 __clk_get_name(parent), notifiers);
611 611
612 case CLK_TYPE_GEN3_R: 612 case CLK_TYPE_GEN3_R:
613 if (cpg_quirks & RCKCR_CKSEL) { 613 if (cpg_quirks & RCKCR_CKSEL) {
@@ -658,11 +658,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
658 658
659 case CLK_TYPE_GEN3_Z: 659 case CLK_TYPE_GEN3_Z:
660 return cpg_z_clk_register(core->name, __clk_get_name(parent), 660 return cpg_z_clk_register(core->name, __clk_get_name(parent),
661 base, CPG_FRQCRC_ZFC_MASK); 661 base, core->div, core->offset);
662
663 case CLK_TYPE_GEN3_Z2:
664 return cpg_z_clk_register(core->name, __clk_get_name(parent),
665 base, CPG_FRQCRC_Z2FC_MASK);
666 662
667 case CLK_TYPE_GEN3_OSC: 663 case CLK_TYPE_GEN3_OSC:
668 /* 664 /*
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index eac1b057455a..15700d219a05 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -3,6 +3,7 @@
3 * R-Car Gen3 Clock Pulse Generator 3 * R-Car Gen3 Clock Pulse Generator
4 * 4 *
5 * Copyright (C) 2015-2018 Glider bvba 5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2018 Renesas Electronics Corp.
6 * 7 *
7 */ 8 */
8 9
@@ -20,7 +21,6 @@ enum rcar_gen3_clk_types {
20 CLK_TYPE_GEN3_R, 21 CLK_TYPE_GEN3_R,
21 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 22 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
22 CLK_TYPE_GEN3_Z, 23 CLK_TYPE_GEN3_Z,
23 CLK_TYPE_GEN3_Z2,
24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
26 CLK_TYPE_GEN3_RPCSRC, 26 CLK_TYPE_GEN3_RPCSRC,
@@ -51,6 +51,9 @@ enum rcar_gen3_clk_types {
51 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 51 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
52 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 52 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
53 53
54#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
55 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
56
54struct rcar_gen3_cpg_pll_config { 57struct rcar_gen3_cpg_pll_config {
55 u8 extal_div; 58 u8 extal_div;
56 u8 pll1_mult; 59 u8 pll1_mult;
diff --git a/include/linux/math64.h b/include/linux/math64.h
index bb2c84afb80c..65bef21cdddb 100644
--- a/include/linux/math64.h
+++ b/include/linux/math64.h
@@ -284,4 +284,17 @@ static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor)
284#define DIV64_U64_ROUND_UP(ll, d) \ 284#define DIV64_U64_ROUND_UP(ll, d) \
285 ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) 285 ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
286 286
287/**
288 * DIV64_U64_ROUND_CLOSEST - unsigned 64bit divide with 64bit divisor rounded to nearest integer
289 * @dividend: unsigned 64bit dividend
290 * @divisor: unsigned 64bit divisor
291 *
292 * Divide unsigned 64bit dividend by unsigned 64bit divisor
293 * and round to closest integer.
294 *
295 * Return: dividend / divisor rounded to nearest integer
296 */
297#define DIV64_U64_ROUND_CLOSEST(dividend, divisor) \
298 ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); })
299
287#endif /* _LINUX_MATH64_H */ 300#endif /* _LINUX_MATH64_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 06:36:48 -0500