KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR

Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.

This patch provides implementations for both GICv2 and GICv3.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

2 files changed, 33 insertions, 4 deletions

diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c
index f9b9c7c51372..8d7b04db8471 100644
--- a/virt/kvm/arm/vgic-v2.c
+++ b/virt/kvm/arm/vgic-v2.c
@@ -48,6 +48,10 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
                 lr_desc.state |= LR_STATE_ACTIVE;
         if (val & GICH_LR_EOI)
                 lr_desc.state |= LR_EOI_INT;
+        if (val & GICH_LR_HW) {
+                lr_desc.state |= LR_HW;
+                lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
+        }
 
         return lr_desc;
 }
@@ -55,7 +59,9 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
 static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
                            struct vgic_lr lr_desc)
 {
-        u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;
+        u32 lr_val;
+
+        lr_val = lr_desc.irq;
 
         if (lr_desc.state & LR_STATE_PENDING)
                 lr_val |= GICH_LR_PENDING_BIT;
@@ -64,6 +70,14 @@ static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
         if (lr_desc.state & LR_EOI_INT)
                 lr_val |= GICH_LR_EOI;
 
+        if (lr_desc.state & LR_HW) {
+                lr_val |= GICH_LR_HW;
+                lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
+        }
+
+        if (lr_desc.irq < VGIC_NR_SGIS)
+                lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);
+
         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
 }
 
diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c
index dff06021e748..afbf925b00f4 100644
--- a/virt/kvm/arm/vgic-v3.c
+++ b/virt/kvm/arm/vgic-v3.c
@@ -67,6 +67,10 @@ static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
                 lr_desc.state |= LR_STATE_ACTIVE;
         if (val & ICH_LR_EOI)
                 lr_desc.state |= LR_EOI_INT;
+        if (val & ICH_LR_HW) {
+                lr_desc.state |= LR_HW;
+                lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
+        }
 
         return lr_desc;
 }
@@ -84,10 +88,17 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
          * Eventually we want to make this configurable, so we may revisit
          * this in the future.
          */
-        if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
+        switch (vcpu->kvm->arch.vgic.vgic_model) {
+        case KVM_DEV_TYPE_ARM_VGIC_V3:
                 lr_val |= ICH_LR_GROUP;
-        else
-                lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
+                break;
+        case  KVM_DEV_TYPE_ARM_VGIC_V2:
+                if (lr_desc.irq < VGIC_NR_SGIS)
+                        lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
+                break;
+        default:
+                BUG();
+        }
 
         if (lr_desc.state & LR_STATE_PENDING)
                 lr_val |= ICH_LR_PENDING_BIT;
@@ -95,6 +106,10 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
                 lr_val |= ICH_LR_ACTIVE_BIT;
         if (lr_desc.state & LR_EOI_INT)
                 lr_val |= ICH_LR_EOI;
+        if (lr_desc.state & LR_HW) {
+                lr_val |= ICH_LR_HW;
+                lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
+        }
 
         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;
 }