diff options
author | Arnaldo Carvalho de Melo <acme@redhat.com> | 2018-02-02 15:22:12 -0500 |
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committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2018-02-02 15:22:12 -0500 |
commit | 4053717aa55697c33631b596f3cc4dd69464e625 (patch) | |
tree | 60cb14af5ffdb42f28f3297b26ebd26e0bfbdd43 /tools | |
parent | 7a16c7e15f4a3859ca9933d124cdabe51940eb5c (diff) |
tools headers: Synchoronize x86 features UAPI headers
Sync tools/arch/x86/include/asm/{cpu,disabled-,required-}features.h with
the changes in:
2961298efe1e ("x86/cpufeatures: Clean up Spectre v2 related CPUID flags")
20ffa1caecca ("x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support")
5d10cbc91d9e ("x86/cpufeatures: Add AMD feature bits for Speculation Control")
fc67dd70adb7 ("x86/cpufeatures: Add Intel feature bits for Speculation Control")
95ca0ee86360 ("x86/cpufeatures: Add CPUID_7_EDX CPUID leaf")
a511e7935378 ("x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature")
4fdec2034b75 ("x86/cpufeature: Move processor tracing out of scattered features")
c995efd5a740 ("x86/retpoline: Fill RSB on context switch for affected CPUs")
76b043848fd2 ("x86/retpoline: Add initial retpoline support")
99c6fa2511d8 ("x86/cpufeatures: Add X86_BUG_SPECTRE_V[12]")
de791821c295 ("x86/pti: Rename BUG_CPU_INSECURE to BUG_CPU_MELTDOWN")
6cff64b86aaa ("x86/mm: Use INVPCID for __native_flush_tlb_single()")
None will entail changes in the tools/perf/, synchronizing to elliminate
these perf build warnings:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h'
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/required-features.h' differs from latest version at 'arch/x86/include/asm/required-features.h'
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Wang Nan <wangnan0@huawei.com>
Link: https://lkml.kernel.org/n/tip-dbdjack1k92xar5ccuq4el1h@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools')
-rw-r--r-- | tools/arch/x86/include/asm/cpufeatures.h | 24 | ||||
-rw-r--r-- | tools/arch/x86/include/asm/disabled-features.h | 3 | ||||
-rw-r--r-- | tools/arch/x86/include/asm/required-features.h | 3 |
3 files changed, 24 insertions, 6 deletions
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 21ac898df2d8..1d9199e1c2ad 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h | |||
@@ -13,7 +13,7 @@ | |||
13 | /* | 13 | /* |
14 | * Defines x86 CPU feature bits | 14 | * Defines x86 CPU feature bits |
15 | */ | 15 | */ |
16 | #define NCAPINTS 18 /* N 32-bit words worth of info */ | 16 | #define NCAPINTS 19 /* N 32-bit words worth of info */ |
17 | #define NBUGINTS 1 /* N 32-bit bug flags */ | 17 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
18 | 18 | ||
19 | /* | 19 | /* |
@@ -203,12 +203,15 @@ | |||
203 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | 203 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
204 | #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ | 204 | #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ |
205 | #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ | 205 | #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ |
206 | #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ | ||
207 | #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */ | ||
206 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | 208 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
207 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | 209 | #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ |
208 | #define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */ | ||
209 | #define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | ||
210 | 210 | ||
211 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | 211 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ |
212 | #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ | ||
213 | |||
214 | #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ | ||
212 | 215 | ||
213 | /* Virtualization flags: Linux defined, word 8 */ | 216 | /* Virtualization flags: Linux defined, word 8 */ |
214 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | 217 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
@@ -243,6 +246,7 @@ | |||
243 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | 246 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ |
244 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | 247 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
245 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | 248 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ |
249 | #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ | ||
246 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | 250 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
247 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | 251 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ |
248 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | 252 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ |
@@ -268,6 +272,9 @@ | |||
268 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ | 272 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ |
269 | #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ | 273 | #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ |
270 | #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ | 274 | #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ |
275 | #define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ | ||
276 | #define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */ | ||
277 | #define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */ | ||
271 | 278 | ||
272 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ | 279 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
273 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | 280 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
@@ -316,6 +323,13 @@ | |||
316 | #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ | 323 | #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ |
317 | #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ | 324 | #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ |
318 | 325 | ||
326 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ | ||
327 | #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ | ||
328 | #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ | ||
329 | #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ | ||
330 | #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ | ||
331 | #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ | ||
332 | |||
319 | /* | 333 | /* |
320 | * BUG word(s) | 334 | * BUG word(s) |
321 | */ | 335 | */ |
@@ -342,5 +356,7 @@ | |||
342 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | 356 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ |
343 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | 357 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ |
344 | #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ | 358 | #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ |
359 | #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ | ||
360 | #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ | ||
345 | 361 | ||
346 | #endif /* _ASM_X86_CPUFEATURES_H */ | 362 | #endif /* _ASM_X86_CPUFEATURES_H */ |
diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h index b027633e7300..33833d1909af 100644 --- a/tools/arch/x86/include/asm/disabled-features.h +++ b/tools/arch/x86/include/asm/disabled-features.h | |||
@@ -77,6 +77,7 @@ | |||
77 | #define DISABLED_MASK15 0 | 77 | #define DISABLED_MASK15 0 |
78 | #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) | 78 | #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) |
79 | #define DISABLED_MASK17 0 | 79 | #define DISABLED_MASK17 0 |
80 | #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) | 80 | #define DISABLED_MASK18 0 |
81 | #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) | ||
81 | 82 | ||
82 | #endif /* _ASM_X86_DISABLED_FEATURES_H */ | 83 | #endif /* _ASM_X86_DISABLED_FEATURES_H */ |
diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x86/include/asm/required-features.h index d91ba04dd007..fb3a6de7440b 100644 --- a/tools/arch/x86/include/asm/required-features.h +++ b/tools/arch/x86/include/asm/required-features.h | |||
@@ -106,6 +106,7 @@ | |||
106 | #define REQUIRED_MASK15 0 | 106 | #define REQUIRED_MASK15 0 |
107 | #define REQUIRED_MASK16 (NEED_LA57) | 107 | #define REQUIRED_MASK16 (NEED_LA57) |
108 | #define REQUIRED_MASK17 0 | 108 | #define REQUIRED_MASK17 0 |
109 | #define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) | 109 | #define REQUIRED_MASK18 0 |
110 | #define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) | ||
110 | 111 | ||
111 | #endif /* _ASM_X86_REQUIRED_FEATURES_H */ | 112 | #endif /* _ASM_X86_REQUIRED_FEATURES_H */ |