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authorNaveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>2018-10-23 04:04:56 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2018-10-30 08:11:04 -0400
commita95ecac5cb2fc8a8ee606991384d33ee121df00c (patch)
tree5800835c357eb44f584c16c572b0b9ab16e489ef /tools/testing
parent3b9672fff747b31a2204003cab9fe082321edc1b (diff)
selftests/powerpc: Relax L1d miss targets for rfi_flush test
When running the rfi_flush test, if the system is loaded, we see two issues: 1. The L1d misses when rfi_flush is disabled increase significantly due to other workloads interfering with the cache. 2. The L1d misses when rfi_flush is enabled sometimes goes slightly below the expected number of misses. To address these, let's relax the expected number of L1d misses: 1. When rfi_flush is disabled, we allow upto half the expected number of the misses for when rfi_flush is enabled. 2. When rfi_flush is enabled, we allow ~1% lower number of cache misses. Reported-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/testing')
-rw-r--r--tools/testing/selftests/powerpc/security/rfi_flush.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/tools/testing/selftests/powerpc/security/rfi_flush.c b/tools/testing/selftests/powerpc/security/rfi_flush.c
index 564ed45bbf73..0a7d0afb26b8 100644
--- a/tools/testing/selftests/powerpc/security/rfi_flush.c
+++ b/tools/testing/selftests/powerpc/security/rfi_flush.c
@@ -49,6 +49,7 @@ int rfi_flush_test(void)
49 struct perf_event_read v; 49 struct perf_event_read v;
50 __u64 l1d_misses_total = 0; 50 __u64 l1d_misses_total = 0;
51 unsigned long iterations = 100000, zero_size = 24 * 1024; 51 unsigned long iterations = 100000, zero_size = 24 * 1024;
52 unsigned long l1d_misses_expected;
52 int rfi_flush_org, rfi_flush; 53 int rfi_flush_org, rfi_flush;
53 54
54 SKIP_IF(geteuid() != 0); 55 SKIP_IF(geteuid() != 0);
@@ -71,6 +72,12 @@ int rfi_flush_test(void)
71 72
72 iter = repetitions; 73 iter = repetitions;
73 74
75 /*
76 * We expect to see l1d miss for each cacheline access when rfi_flush
77 * is set. Allow a small variation on this.
78 */
79 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2);
80
74again: 81again:
75 FAIL_IF(perf_event_reset(fd)); 82 FAIL_IF(perf_event_reset(fd));
76 83
@@ -78,10 +85,9 @@ again:
78 85
79 FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v)); 86 FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v));
80 87
81 /* Expect at least zero_size/CACHELINE_SIZE misses per iteration */ 88 if (rfi_flush && v.l1d_misses >= l1d_misses_expected)
82 if (v.l1d_misses >= (iterations * zero_size / CACHELINE_SIZE) && rfi_flush)
83 passes++; 89 passes++;
84 else if (v.l1d_misses < iterations && !rfi_flush) 90 else if (!rfi_flush && v.l1d_misses < (l1d_misses_expected / 2))
85 passes++; 91 passes++;
86 92
87 l1d_misses_total += v.l1d_misses; 93 l1d_misses_total += v.l1d_misses;
@@ -92,13 +98,15 @@ again:
92 if (passes < repetitions) { 98 if (passes < repetitions) {
93 printf("FAIL (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d failures]\n", 99 printf("FAIL (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d failures]\n",
94 rfi_flush, l1d_misses_total, rfi_flush ? '<' : '>', 100 rfi_flush, l1d_misses_total, rfi_flush ? '<' : '>',
95 rfi_flush ? (repetitions * iterations * zero_size / CACHELINE_SIZE) : iterations, 101 rfi_flush ? repetitions * l1d_misses_expected :
102 repetitions * l1d_misses_expected / 2,
96 repetitions - passes, repetitions); 103 repetitions - passes, repetitions);
97 rc = 1; 104 rc = 1;
98 } else 105 } else
99 printf("PASS (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d pass]\n", 106 printf("PASS (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d pass]\n",
100 rfi_flush, l1d_misses_total, rfi_flush ? '>' : '<', 107 rfi_flush, l1d_misses_total, rfi_flush ? '>' : '<',
101 rfi_flush ? (repetitions * iterations * zero_size / CACHELINE_SIZE) : iterations, 108 rfi_flush ? repetitions * l1d_misses_expected :
109 repetitions * l1d_misses_expected / 2,
102 passes, repetitions); 110 passes, repetitions);
103 111
104 if (rfi_flush == rfi_flush_org) { 112 if (rfi_flush == rfi_flush_org) {