diff options
| author | Rashmica Gupta <rashmicy@gmail.com> | 2015-12-23 00:49:51 -0500 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-11 07:54:12 -0400 |
| commit | da3ddc3b5fea695f7b2fa89c4ca17dfd529293d2 (patch) | |
| tree | 2a463c39e1567a184d24dc9c18e236adb62cc68f /tools/testing/selftests | |
| parent | 2d59b3b25659463a24f05df367574d90b3cd7145 (diff) | |
selftests/powerpc: Standardise TM calls
Currently tbegin, tend etc are written as opcodes or asm instructions. So
standardise these to asm instructions.
Signed-off-by: Rashmica Gupta <rashmicy@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/testing/selftests')
| -rw-r--r-- | tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | 16 | ||||
| -rw-r--r-- | tools/testing/selftests/powerpc/tm/tm-signal-stack.c | 4 |
2 files changed, 7 insertions, 13 deletions
diff --git a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c index 8fde93d6021f..d9c49f41515e 100644 --- a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c +++ b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | |||
| @@ -31,12 +31,6 @@ | |||
| 31 | #include "utils.h" | 31 | #include "utils.h" |
| 32 | #include "tm.h" | 32 | #include "tm.h" |
| 33 | 33 | ||
| 34 | #define TBEGIN ".long 0x7C00051D ;" | ||
| 35 | #define TEND ".long 0x7C00055D ;" | ||
| 36 | #define TCHECK ".long 0x7C00059C ;" | ||
| 37 | #define TSUSPEND ".long 0x7C0005DD ;" | ||
| 38 | #define TRESUME ".long 0x7C2005DD ;" | ||
| 39 | #define SPRN_TEXASR 0x82 | ||
| 40 | #define SPRN_DSCR 0x03 | 34 | #define SPRN_DSCR 0x03 |
| 41 | 35 | ||
| 42 | int test_body(void) | 36 | int test_body(void) |
| @@ -55,13 +49,13 @@ int test_body(void) | |||
| 55 | "mtspr %[sprn_dscr], 3;" | 49 | "mtspr %[sprn_dscr], 3;" |
| 56 | 50 | ||
| 57 | /* start and suspend a transaction */ | 51 | /* start and suspend a transaction */ |
| 58 | TBEGIN | 52 | "tbegin.;" |
| 59 | "beq 1f;" | 53 | "beq 1f;" |
| 60 | TSUSPEND | 54 | "tsuspend.;" |
| 61 | 55 | ||
| 62 | /* hard loop until the transaction becomes doomed */ | 56 | /* hard loop until the transaction becomes doomed */ |
| 63 | "2: ;" | 57 | "2: ;" |
| 64 | TCHECK | 58 | "tcheck 0;" |
| 65 | "bc 4, 0, 2b;" | 59 | "bc 4, 0, 2b;" |
| 66 | 60 | ||
| 67 | /* record DSCR and TEXASR */ | 61 | /* record DSCR and TEXASR */ |
| @@ -70,8 +64,8 @@ int test_body(void) | |||
| 70 | "mfspr 3, %[sprn_texasr];" | 64 | "mfspr 3, %[sprn_texasr];" |
| 71 | "std 3, %[texasr];" | 65 | "std 3, %[texasr];" |
| 72 | 66 | ||
| 73 | TRESUME | 67 | "tresume.;" |
| 74 | TEND | 68 | "tend.;" |
| 75 | "li %[rv], 0;" | 69 | "li %[rv], 0;" |
| 76 | "1: ;" | 70 | "1: ;" |
| 77 | : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr) | 71 | : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr) |
diff --git a/tools/testing/selftests/powerpc/tm/tm-signal-stack.c b/tools/testing/selftests/powerpc/tm/tm-signal-stack.c index e44a238c1d77..1f0eb567438d 100644 --- a/tools/testing/selftests/powerpc/tm/tm-signal-stack.c +++ b/tools/testing/selftests/powerpc/tm/tm-signal-stack.c | |||
| @@ -60,9 +60,9 @@ int tm_signal_stack() | |||
| 60 | exit(1); | 60 | exit(1); |
| 61 | asm volatile("li 1, 0 ;" /* stack ptr == NULL */ | 61 | asm volatile("li 1, 0 ;" /* stack ptr == NULL */ |
| 62 | "1:" | 62 | "1:" |
| 63 | ".long 0x7C00051D ;" /* tbegin */ | 63 | "tbegin.;" |
| 64 | "beq 1b ;" /* retry forever */ | 64 | "beq 1b ;" /* retry forever */ |
| 65 | ".long 0x7C0005DD ; ;" /* tsuspend */ | 65 | "tsuspend.;" |
| 66 | "ld 2, 0(1) ;" /* trigger segv" */ | 66 | "ld 2, 0(1) ;" /* trigger segv" */ |
| 67 | : : : "memory"); | 67 | : : : "memory"); |
| 68 | 68 | ||
