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| author | Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> | 2018-04-26 13:22:32 -0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-15 18:02:23 -0400 |
| commit | e76e56823a318ca580be4cfc5a6a9269bc70abea (patch) | |
| tree | ba82caea099972bae97ddcd24867f14a76cfc933 /tools/perf/scripts/python/syscall-counts.py | |
| parent | dcb899c47da9ff32e5156ddb9b2867f63ff7c4d0 (diff) | |
clk:aspeed: Fix reset bits for PCI/VGA and PECI
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions