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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-04-25 04:45:18 -0400 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-06-04 02:01:23 -0400 |
| commit | b21a9c3ee83ab26fd33c9a5f3bc2150c95eea975 (patch) | |
| tree | 866677c74841d0f5fecfdb45162f480a9b39a270 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f892b203525acb6af02bddcae95fbb547624a986 (diff) | |
arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk
We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.
This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock
node, which is only a gate clock, allowing the setting of the clock rate
to propagate to the PLL.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Acked-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions