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| author | Scott Telford <stelford@cadence.com> | 2016-09-15 11:26:45 -0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2016-09-19 14:51:32 -0400 |
| commit | bebbc4bcf36f015a5a051cc8817b11de209fbe8b (patch) | |
| tree | e0dd6dbdafc17293c491524ce1786a4df5ddc4da /tools/perf/scripts/python/stackcollapse.py | |
| parent | bf15f86b343ed894e74fb9c6c944cea1f8f9b654 (diff) | |
xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.
Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions