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| author | Thierry Reding <treding@nvidia.com> | 2017-06-26 11:37:09 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 07:15:42 -0500 |
| commit | 94e25dc3a2b55eb9732f6da41bd25b9dccd60b5a (patch) | |
| tree | 4555b6e7dfff6afacc25d3ddbc53c2c3f5d3ac44 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 029ab5eaf091ce5eaa1f3017f66fd1d10f431d61 (diff) | |
arm64: tegra: Add MISC registers on Tegra186
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions