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authorSylwester Nawrocki <s.nawrocki@samsung.com>2017-07-17 08:39:21 -0400
committerSylwester Nawrocki <s.nawrocki@samsung.com>2017-08-09 11:17:04 -0400
commit7df45a532c5ee3efe106e8a9042a3524b0b587b1 (patch)
tree138b08398b57f7cb900eb5f85ceaf0f66aa03c2a /tools/perf/scripts/python/stackcollapse.py
parent41097f25e9b2091d5d0a309cceb788704f21e1d2 (diff)
clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
This allows clk rate propagation up to the clock tree so EPLL can be reprogrammed indirectly when setting rate of the Audio Subsystem clocks. The advantage is that sound machine driver can operate only on the leaf clocks rather than explicitly re-configuring the root clock (EPLL). Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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