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| author | Dmitry Osipenko <digetx@gmail.com> | 2017-12-20 10:46:10 -0500 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-21 08:52:38 -0500 |
| commit | f68ba6912bd24088f067da2470880892abc2ac58 (patch) | |
| tree | 0178a29a889f4d36bdd20f368e81a635b7355b9d /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 39f55c61da49ba41bba4185043cba6f39229467f (diff) | |
drm/tegra: dc: Link DC1 to DC0 on Tegra20
Hardware reset isn't actually broken on Tegra20, but there is a
dependency on the first display controller to be taken out of reset for
the second to be enabled successfully. Model this dependency using a PM
device link.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: minor cleanups, extend commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions