diff options
| author | Andrew F. Davis <afd@ti.com> | 2017-12-12 17:43:06 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-12-13 07:27:48 -0500 |
| commit | 77bdb58795d86262e96ba37524489ba0969de253 (patch) | |
| tree | fb0c1a58198d843ffeb98ededc381a969819889f /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 4483521d81684764cb7f2569bf3e4b10d38ef9f7 (diff) | |
ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits
Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions