diff options
| author | Sekhar Nori <nsekhar@ti.com> | 2018-05-25 14:11:45 -0400 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2018-05-30 15:48:27 -0400 |
| commit | 7f02f18e7f87831747aaa2685f63d16fb2649c6a (patch) | |
| tree | adac6daea157c91d4db8fe86c582ebd4a9e26900 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 715478bb63ffd76cf90f6536be8592e3f6df9567 (diff) | |
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions