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authorAbhishek Sahu <absahu@codeaurora.org>2017-09-28 13:50:43 -0400
committerStephen Boyd <sboyd@codeaurora.org>2017-12-13 16:45:32 -0500
commit26945e0a2341523170aa5b6ff4cc35e9ce1f7cf4 (patch)
tree2be3f77a1a0809f4e9b7c21345848f444d30c871 /tools/perf/scripts/python/export-to-sqlite.py
parent1e859d3e03f0ac97d15e1952bddda4b29de1c71c (diff)
clk: qcom: flag for 64 bit CONFIG_CTL
Some of the Alpha PLLs (like Spark and Brammo) don't have a CONFIG_CTL_U register. Add logic to detect when PLLs don't have this second config register and skip programming it during PLL initialization. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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