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| author | Eric Anholt <eric@anholt.net> | 2016-02-15 20:31:41 -0500 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2016-02-26 20:42:47 -0500 |
| commit | a7c5047d1ce178dd2b1fa577fc8909ad663d56d5 (patch) | |
| tree | a817f72b9d1334c67e92392bf0e9d426c14aab81 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | c31806fbdda910d337b60896040afa708bdfa2bd (diff) | |
drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first. Without this, changing resolution never worked.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions