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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2016-04-08 03:31:50 -0400 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2016-04-27 10:39:54 -0400 |
| commit | 70896650732afd64c410f85c819281dbce8a0974 (patch) | |
| tree | 78d2a4348d00aa1c4162e148b1aaf7b70efde7ae /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
arm64: dts: hip05: fix its node without msi-cells
Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS
entries"), it forgets the property msi-cell, see arm,gic-v3.txt.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions