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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-02-26 16:29:32 -0500
committerDave Airlie <airlied@redhat.com>2016-03-02 02:50:17 -0500
commit2d02b8bdba322b527c5f5168ce1ca10c2d982a78 (patch)
tree562afede287656dae0c54d491c7b76a6c067080b /tools/perf/scripts/python/event_analyzing_sample.py
parentead8f34c701ec7bf3234118b8c746227f30dfd1a (diff)
drm/ast: Fix incorrect register check for DRAM width
During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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