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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-03-07 13:03:24 -0500
committerSimon Horman <horms+renesas@verge.net.au>2017-03-10 04:26:43 -0500
commita681e6d63285b879bb9bab0bd79e2021e6dcbda1 (patch)
tree14886e1a124ff05f6537df341bdf3497d7c00e3f /tools/perf/scripts/python/call-graph-from-postgresql.py
parent9fccf4d6103eeb5db88c1ae026d61b87f722414a (diff)
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Extracted from a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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