diff options
| author | Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> | 2018-05-18 09:43:37 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-05-18 13:54:48 -0400 |
| commit | d775f26b295a0a303f7a73d7da46e04296484fe7 (patch) | |
| tree | 6173edee4d7650284e93c23880791941a399428f /tools/perf/scripts/python/bin | |
| parent | 44a63b137f7b6e4c7bd6c9cc21615941cb36509d (diff) | |
cxgb4: fix offset in collecting TX rate limit info
Correct the indirect register offsets in collecting TX rate limit info
in UP CIM logs.
Also, T5 doesn't support these indirect register offsets, so remove
them from collection logic.
Fixes: be6e36d916b1 ("cxgb4: collect TX rate limit info in UP CIM logs")
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions