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| author | Peter Chen <peter.chen@freescale.com> | 2015-01-16 05:29:01 -0500 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2015-01-27 10:40:49 -0500 |
| commit | e235f7b86f33beea7e096b46db1802dbf5d7d22e (patch) | |
| tree | d7fb5e5b8949829c3b58a328ea0d4ebbf990647c /tools/perf/scripts/python/bin/export-to-postgresql-report | |
| parent | efdbd3a5d6e6108f1565ab4dc4c53e77aba6fe0a (diff) | |
usb: phy: mxs: add delay before set phyctrl.clkgate
There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phy's pwd register, otherwise,
the wakeup signal may can't wake up controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-postgresql-report')
0 files changed, 0 insertions, 0 deletions