diff options
author | Bard Liao <bardliao@realtek.com> | 2014-11-18 03:50:18 -0500 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2014-11-25 07:09:48 -0500 |
commit | 2d4e2d020516632288e8c8d1f8be2f3042d6b8de (patch) | |
tree | 03c53e6f15db3d4f3b6027f4d1f23213ac209ffe /sound/soc/codecs/rt5645.h | |
parent | 471f208af987a3741757c169c4e2ad984359000b (diff) |
ASoC: rt5645: multiple JD mode support
There are 3 JD modes in RT5645. This patch configure register
values according to platform data.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/rt5645.h')
-rw-r--r-- | sound/soc/codecs/rt5645.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h index c72220abdbc0..a815e36a2bdb 100644 --- a/sound/soc/codecs/rt5645.h +++ b/sound/soc/codecs/rt5645.h | |||
@@ -594,6 +594,7 @@ | |||
594 | #define RT5645_M_DAC1_HM_SFT 14 | 594 | #define RT5645_M_DAC1_HM_SFT 14 |
595 | #define RT5645_M_HPVOL_HM (0x1 << 13) | 595 | #define RT5645_M_HPVOL_HM (0x1 << 13) |
596 | #define RT5645_M_HPVOL_HM_SFT 13 | 596 | #define RT5645_M_HPVOL_HM_SFT 13 |
597 | #define RT5645_IRQ_PSV_MODE (0x1 << 12) | ||
597 | 598 | ||
598 | /* SPK Left Mixer Control (0x46) */ | 599 | /* SPK Left Mixer Control (0x46) */ |
599 | #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) | 600 | #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) |
@@ -1350,6 +1351,10 @@ | |||
1350 | #define RT5645_PWR_CLK25M_PU (0x1 << 4) | 1351 | #define RT5645_PWR_CLK25M_PU (0x1 << 4) |
1351 | #define RT5645_IRQ_CLK_MCLK (0x0 << 3) | 1352 | #define RT5645_IRQ_CLK_MCLK (0x0 << 3) |
1352 | #define RT5645_IRQ_CLK_INT (0x1 << 3) | 1353 | #define RT5645_IRQ_CLK_INT (0x1 << 3) |
1354 | #define RT5645_JD1_MODE_MASK (0x3 << 0) | ||
1355 | #define RT5645_JD1_MODE_0 (0x0 << 0) | ||
1356 | #define RT5645_JD1_MODE_1 (0x1 << 0) | ||
1357 | #define RT5645_JD1_MODE_2 (0x2 << 0) | ||
1353 | 1358 | ||
1354 | /* VAD Control 4 (0x9d) */ | 1359 | /* VAD Control 4 (0x9d) */ |
1355 | #define RT5645_VAD_SEL_MASK (0x3 << 8) | 1360 | #define RT5645_VAD_SEL_MASK (0x3 << 8) |
@@ -1638,6 +1643,7 @@ | |||
1638 | #define RT5645_OT_P_SFT 10 | 1643 | #define RT5645_OT_P_SFT 10 |
1639 | #define RT5645_OT_P_NOR (0x0 << 10) | 1644 | #define RT5645_OT_P_NOR (0x0 << 10) |
1640 | #define RT5645_OT_P_INV (0x1 << 10) | 1645 | #define RT5645_OT_P_INV (0x1 << 10) |
1646 | #define RT5645_IRQ_JD_1_1_EN (0x1 << 9) | ||
1641 | 1647 | ||
1642 | /* IRQ Control 2 (0xbe) */ | 1648 | /* IRQ Control 2 (0xbe) */ |
1643 | #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) | 1649 | #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) |
@@ -2120,6 +2126,7 @@ enum { | |||
2120 | #define RT5645_RXDP2_SEL_SFT (3) | 2126 | #define RT5645_RXDP2_SEL_SFT (3) |
2121 | 2127 | ||
2122 | /* General Control3 (0xfc) */ | 2128 | /* General Control3 (0xfc) */ |
2129 | #define RT5645_JD_PSV_MODE (0x1 << 12) | ||
2123 | #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) | 2130 | #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) |
2124 | #define RT5645_MICINDET_MANU (0x1 << 7) | 2131 | #define RT5645_MICINDET_MANU (0x1 << 7) |
2125 | 2132 | ||