diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2019-03-26 14:22:57 -0400 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-04-03 05:09:50 -0400 |
| commit | 639eb92531166a17bdb459437fbadf97459c5370 (patch) | |
| tree | e8b93f27b6541399ba9b8023c405f84a58c749e7 /scripts/gdb/linux/timerlist.py | |
| parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) | |
clk: imx5: Fix i.MX50 mainbus clock registers
i.MX50 does not have a periph_apm clock. Instead, the main bus clock
(a.k.a. periph_clk) comes directly from a MUX between pll1_sw, pll2_sw,
pll3_sw, and lp_apm.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions