litmus-rt-ext-res.git - LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20

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author	Thomas Gleixner <tglx@linutronix.de>	2019-05-27 02:55:06 -0400
committer	Greg Kroah-Hartman <gregkh@linuxfoundation.org>	2019-05-30 14:26:37 -0400
commit	c942fddf8793b2013be8c901b47d0a8dc02bf99f (patch)
tree	c5874834a85a5f23db1fec94d1098f2757cb47f5 /scripts/coccinelle/misc/boolconv.cocci
parent	1a59d1b8e05ea6ab45f7e18897de1ef0e6bc3da6 (diff)

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Diffstat (limited to 'scripts/coccinelle/misc/boolconv.cocci')

0 files changed, 0 insertions, 0 deletions

/* * This file contains code to reset and initialize USB host controllers. * Some of it includes work-arounds for PCI hardware and BIOS quirks. * It may need to run early during booting -- before USB would normally * initialize -- to ensure that Linux doesn't use any legacy modes. * * Copyright (c) 1999 Martin Mares <mj@ucw.cz> * (and others) */ #include <linux/types.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/export.h> #include <linux/acpi.h> #include <linux/dmi.h> #include "pci-quirks.h" #include "xhci-ext-caps.h" #define UHCI_USBLEGSUP 0xc0 /* legacy support */ #define UHCI_USBCMD 0 /* command register */ #define UHCI_USBINTR 4 /* interrupt register */ #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ #define OHCI_CONTROL 0x04 #define OHCI_CMDSTATUS 0x08 #define OHCI_INTRSTATUS 0x0c #define OHCI_INTRENABLE 0x10 #define OHCI_INTRDISABLE 0x14 #define OHCI_FMINTERVAL 0x34 #define OHCI_HCFS (3 << 6) /* hc functional state */ #define OHCI_HCR (1 << 0) /* host controller reset */ #define OHCI_OCR (1 << 3) /* ownership change request */ #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ #define OHCI_INTR_OC (1 << 30) /* ownership change */ #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ #define EHCI_USBCMD 0 /* command register */ #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ #define EHCI_USBSTS 4 /* status register */ #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ #define EHCI_USBINTR 8 /* interrupt register */ #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ #define EHCI_USBLEGSUP 0 /* legacy support register */ #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ /* AMD quirk use */ #define AB_REG_BAR_LOW 0xe0 #define AB_REG_BAR_HIGH 0xe1 #define AB_REG_BAR_SB700 0xf0 #define AB_INDX(addr) ((addr) + 0x00) #define AB_DATA(addr) ((addr) + 0x04) #define AX_INDXC 0x30 #define AX_DATAC 0x34 #define NB_PCIE_INDX_ADDR 0xe0 #define NB_PCIE_INDX_DATA 0xe4 #define PCIE_P_CNTL 0x10040 #define BIF_NB 0x10002 #define NB_PIF0_PWRDOWN_0 0x01100012 #define NB_PIF0_PWRDOWN_1 0x01100013 #define USB_INTEL_XUSB2PR 0xD0 #define USB_INTEL_USB3_PSSEN 0xD8 static struct amd_chipset_info { struct pci_dev *nb_dev; struct pci_dev *smbus_dev; int nb_type; int sb_type; int isoc_reqs; int probe_count; int probe_result; } amd_chipset; static DEFINE_SPINLOCK(amd_lock); int usb_amd_find_chipset_info(void) { u8 rev = 0; unsigned long flags; struct amd_chipset_info info; int ret; spin_lock_irqsave(&amd_lock, flags); /* probe only once */ if (amd_chipset.probe_count > 0) { amd_chipset.probe_count++; spin_unlock_irqrestore(&amd_lock, flags); return amd_chipset.probe_result; } memset(&info, 0, sizeof(info)); spin_unlock_irqrestore(&amd_lock, flags); info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL); if (info.smbus_dev) { rev = info.smbus_dev->revision; if (rev >= 0x40) info.sb_type = 1; else if (rev >= 0x30 && rev <= 0x3b) info.sb_type = 3; } else { info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL); if (!info.smbus_dev) { ret = 0; goto commit; } rev = info.smbus_dev->revision; if (rev >= 0x11 && rev <= 0x18) info.sb_type = 2; } if (info.sb_type == 0) { if (info.smbus_dev) { pci_dev_put(info.smbus_dev); info.smbus_dev = NULL; } ret = 0; goto commit; } info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); if (info.nb_dev) { info.nb_type = 1; } else { info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); if (info.nb_dev) { info.nb_type = 2; } else { info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL); if (info.nb_dev) info.nb_type = 3; } } ret = info.probe_result = 1; printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); commit: spin_lock_irqsave(&amd_lock, flags); if (amd_chipset.probe_count > 0) { /* race - someone else was faster - drop devices */ /* Mark that we where here */ amd_chipset.probe_count++; ret = amd_chipset.probe_result; spin_unlock_irqrestore(&amd_lock, flags); if (info.nb_dev) pci_dev_put(info.nb_dev); if (info.smbus_dev) pci_dev_put(info.smbus_dev); } else { /* no race - commit the result */ info.probe_count++; amd_chipset = info; spin_unlock_irqrestore(&amd_lock, flags); } return ret; } EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); /* * The hardware normally enables the A-link power management feature, which * lets the system lower the power consumption in idle states. * * This USB quirk prevents the link going into that lower power state * during isochronous transfers. * * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of * some AMD platforms may stutter or have breaks occasionally. */ static void usb_amd_quirk_pll(int disable) { u32 addr, addr_low, addr_high, val; u32 bit = disable ? 0 : 1; unsigned long flags; spin_lock_irqsave(&amd_lock, flags); if (disable) { amd_chipset.isoc_reqs++; if (amd_chipset.isoc_reqs > 1) { spin_unlock_irqrestore(&amd_lock, flags); return; } } else { amd_chipset.isoc_reqs--; if (amd_chipset.isoc_reqs > 0) { spin_unlock_irqrestore(&amd_lock, flags); return; } } if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) { outb_p(AB_REG_BAR_LOW, 0xcd6); addr_low = inb_p(0xcd7); outb_p(AB_REG_BAR_HIGH, 0xcd6); addr_high = inb_p(0xcd7); addr = addr_high << 8 | addr_low; outl_p(0x30, AB_INDX(addr)); outl_p(0x40, AB_DATA(addr)); outl_p(0x34, AB_INDX(addr)); val = inl_p(AB_DATA(addr)); } else if (amd_chipset.sb_type == 3) { pci_read_config_dword(amd_chipset.smbus_dev, AB_REG_BAR_SB700, &addr); outl(AX_INDXC, AB_INDX(addr)); outl(0x40, AB_DATA(addr)); outl(AX_DATAC, AB_INDX(addr)); val = inl(AB_DATA(addr)); } else { spin_unlock_irqrestore(&amd_lock, flags); return; } if (disable) { val &= ~0x08; val |= (1 << 4) | (1 << 9); } else { val |= 0x08; val &= ~((1 << 4) | (1 << 9)); } outl_p(val, AB_DATA(addr)); if (!amd_chipset.nb_dev) { spin_unlock_irqrestore(&amd_lock, flags); return; } if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { addr = PCIE_P_CNTL; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_ADDR, addr); pci_read_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, &val); val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); val |= bit | (bit << 3) | (bit << 12); val |= ((!bit) << 4) | ((!bit) << 9); pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, val); addr = BIF_NB; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_ADDR, addr); pci_read_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, &val); val &= ~(1 << 8); val |= bit << 8; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, val); } else if (amd_chipset.nb_type == 2) { addr = NB_PIF0_PWRDOWN_0; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_ADDR, addr); pci_read_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, &val); if (disable) val &= ~(0x3f << 7); else val |= 0x3f << 7; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, val); addr = NB_PIF0_PWRDOWN_1; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_ADDR, addr); pci_read_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, &val); if (disable) val &= ~(0x3f << 7); else val |= 0x3f << 7; pci_write_config_dword(amd_chipset.nb_dev, NB_PCIE_INDX_DATA, val); } spin_unlock_irqrestore(&amd_lock, flags); return; } void usb_amd_quirk_pll_disable(void) { usb_amd_quirk_pll(1); } EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); void usb_amd_quirk_pll_enable(void) { usb_amd_quirk_pll(0); } EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); void usb_amd_dev_put(void) { struct pci_dev *nb, *smbus; unsigned long flags; spin_lock_irqsave(&amd_lock, flags); amd_chipset.probe_count--; if (amd_chipset.probe_count > 0) { spin_unlock_irqrestore(&amd_lock, flags); return; } /* save them to pci_dev_put outside of spinlock */ nb = amd_chipset.nb_dev; smbus = amd_chipset.smbus_dev; amd_chipset.nb_dev = NULL; amd_chipset.smbus_dev = NULL; amd_chipset.nb_type = 0; amd_chipset.sb_type = 0; amd_chipset.isoc_reqs = 0; amd_chipset.probe_result = 0; spin_unlock_irqrestore(&amd_lock, flags); if (nb) pci_dev_put(nb); if (smbus) pci_dev_put(smbus); } EXPORT_SYMBOL_GPL(usb_amd_dev_put); /* * Make sure the controller is completely inactive, unable to * generate interrupts or do DMA. */ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) { /* Turn off PIRQ enable and SMI enable. (This also turns off the * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. */ pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); /* Reset the HC - this will force us to get a * new notification of any already connected * ports due to the virtual disconnect that it * implies. */ outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); mb(); udelay(5); if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); /* Just to be safe, disable interrupt requests and * make sure the controller is stopped. */ outw(0, base + UHCI_USBINTR); outw(0, base + UHCI_USBCMD); } EXPORT_SYMBOL_GPL(uhci_reset_hc); /* * Initialize a controller that was newly discovered or has just been * resumed. In either case we can't be sure of its previous state. * * Returns: 1 if the controller was reset, 0 otherwise. */ int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) { u16 legsup; unsigned int cmd, intr; /* * When restarting a suspended controller, we expect all the * settings to be the same as we left them: * * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; * Controller is stopped and configured with EGSM set; * No interrupts enabled except possibly Resume Detect. * * If any of these conditions are violated we do a complete reset. */ pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", __func__, legsup); goto reset_needed; } cmd = inw(base + UHCI_USBCMD); if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || !(cmd & UHCI_USBCMD_EGSM)) { dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", __func__, cmd); goto reset_needed; } intr = inw(base + UHCI_USBINTR); if (intr & (~UHCI_USBINTR_RESUME)) { dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", __func__, intr); goto reset_needed; } return 0; reset_needed: dev_dbg(&pdev->dev, "Performing full reset\n"); uhci_reset_hc(pdev, base); return 1; } EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) { u16 cmd; return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); } #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) { unsigned long base = 0; int i; if (!pio_enabled(pdev)) return; for (i = 0; i < PCI_ROM_RESOURCE; i++) if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { base = pci_resource_start(pdev, i); break; } if (base) uhci_check_and_reset_hc(pdev, base); } static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) { return pci_resource_start(pdev, idx) && mmio_enabled(pdev); } static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) { void __iomem *base; u32 control; u32 fminterval; int cnt; if (!mmio_resource_enabled(pdev, 0)) return; base = pci_ioremap_bar(pdev, 0); if (base == NULL) return; control = readl(base + OHCI_CONTROL); /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ #ifdef __hppa__ #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) #else #define OHCI_CTRL_MASK OHCI_CTRL_RWC if (control & OHCI_CTRL_IR) { int wait_time = 500; /* arbitrary; 5 seconds */


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