diff options
| author | Thinh Nguyen <Thinh.Nguyen@synopsys.com> | 2018-03-16 18:33:48 -0400 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-03-22 04:48:46 -0400 |
| commit | fab3833338779e1e668bd58d1f76d601657304b8 (patch) | |
| tree | a7071ba2b0f8b27bfadc3600040378fdf2b5bd65 /net/lapb/lapb_timer.c | |
| parent | cabdf83dadfb3d83eec31e0f0638a92dbd716435 (diff) | |
usb: dwc3: Add SoftReset PHY synchonization delay
From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions