Merge tag 'irqchip-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier

- Core pseudo-NMI handling code
- Allow the default irq domain to be retrieved
- A new interrupt controller for the Loongson LS1X platform
- Affinity support for the SiFive PLIC
- Better support for the iMX irqsteer driver
- NUMA aware memory allocations for GICv3
- A handful of other fixes (i8259, GICv3, PLIC)

1 files changed, 4 insertions, 2 deletions

diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c
index bbd783a83409..516c00a5e867 100644
--- a/kernel/irq/debugfs.c
+++ b/kernel/irq/debugfs.c
@@ -56,6 +56,7 @@ static const struct irq_bit_descr irqchip_flags[] = {
         BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE),
         BIT_MASK_DESCR(IRQCHIP_EOI_THREADED),
         BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI),
+        BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI),
 };
 
 static void
@@ -140,6 +141,7 @@ static const struct irq_bit_descr irqdesc_istates[] = {
         BIT_MASK_DESCR(IRQS_WAITING),
         BIT_MASK_DESCR(IRQS_PENDING),
         BIT_MASK_DESCR(IRQS_SUSPENDED),
+        BIT_MASK_DESCR(IRQS_NMI),
 };
 
 
@@ -203,8 +205,8 @@ static ssize_t irq_debug_write(struct file *file, const char __user *user_buf,
                 chip_bus_lock(desc);
                 raw_spin_lock_irqsave(&desc->lock, flags);
 
-                if (irq_settings_is_level(desc)) {
-                        /* Can't do level, sorry */
+                if (irq_settings_is_level(desc) || desc->istate & IRQS_NMI) {
+                        /* Can't do level nor NMIs, sorry */
                         err = -EINVAL;
                 } else {
                         desc->istate |= IRQS_PENDING;