Merge tag 'irqchip-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier

- Core pseudo-NMI handling code
- Allow the default irq domain to be retrieved
- A new interrupt controller for the Loongson LS1X platform
- Affinity support for the SiFive PLIC
- Better support for the iMX irqsteer driver
- NUMA aware memory allocations for GICv3
- A handful of other fixes (i8259, GICv3, PLIC)

1 files changed, 54 insertions, 0 deletions

diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index e960c4f46ee0..99b7dd6982a4 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -730,6 +730,37 @@ out:
 EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
 
 /**
+ *      handle_fasteoi_nmi - irq handler for NMI interrupt lines
+ *      @desc:  the interrupt description structure for this irq
+ *
+ *      A simple NMI-safe handler, considering the restrictions
+ *      from request_nmi.
+ *
+ *      Only a single callback will be issued to the chip: an ->eoi()
+ *      call when the interrupt has been serviced. This enables support
+ *      for modern forms of interrupt handlers, which handle the flow
+ *      details in hardware, transparently.
+ */
+void handle_fasteoi_nmi(struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct irqaction *action = desc->action;
+        unsigned int irq = irq_desc_get_irq(desc);
+        irqreturn_t res;
+
+        trace_irq_handler_entry(irq, action);
+        /*
+         * NMIs cannot be shared, there is only one action.
+         */
+        res = action->handler(irq, action->dev_id);
+        trace_irq_handler_exit(irq, action, res);
+
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+}
+EXPORT_SYMBOL_GPL(handle_fasteoi_nmi);
+
+/**
  *      handle_edge_irq - edge type IRQ handler
  *      @desc:  the interrupt description structure for this irq
  *
@@ -916,6 +947,29 @@ void handle_percpu_devid_irq(struct irq_desc *desc)
                 chip->irq_eoi(&desc->irq_data);
 }
 
+/**
+ * handle_percpu_devid_fasteoi_nmi - Per CPU local NMI handler with per cpu
+ *                                   dev ids
+ * @desc:       the interrupt description structure for this irq
+ *
+ * Similar to handle_fasteoi_nmi, but handling the dev_id cookie
+ * as a percpu pointer.
+ */
+void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct irqaction *action = desc->action;
+        unsigned int irq = irq_desc_get_irq(desc);
+        irqreturn_t res;
+
+        trace_irq_handler_entry(irq, action);
+        res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
+        trace_irq_handler_exit(irq, action, res);
+
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+}
+
 static void
 __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
                      int is_chained, const char *name)