Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The large diff this time around is from the addition of a new clk
  driver for the TI Davinci family of SoCs. So far those clks have been
  supported with a custom implementation of the clk API in the arch port
  instead of in the CCF. With this driver merged we're one step closer
  to having a single clk API implementation.

  The other large diff is from the Amlogic clk driver that underwent
  some major surgery to use regmap. Beyond that, the biggest hitter is
  Samsung which needed some reworks to properly handle clk provider
  power domains and a bunch of PLL rate updates.

  The core framework was fairly quiet this round, just getting some
  cleanups and small fixes for some of the more esoteric features. And
  the usual set of driver non-critical fixes, cleanups, and minor
  additions are here as well.

  Core:
   - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops
   - debugfs ops macroized to shave some lines of boilerplate code
   - Always calculate the phase instead of caching it in clk_get_phase()
   - More __must_check on bulk clk APIs

  New Drivers:
   - TI's Davinci family of SoCs
   - Intel's Stratix10 SoC
   - stm32mp157 SoC
   - Allwinner H6 CCU
   - Silicon Labs SI544 clock generator chip
   - Renesas R-Car M3-N and V3H SoCs
   - i.MX6SLL SoCs

  Removed Drivers:
   - ST-Ericsson AB8540/9540

  Updates:
   - Mediatek MT2701 and MT7622 audsys support and MT2712 updates
   - STM32F469 DSI and STM32F769 sdmmc2 support
   - GPIO clks can sleep now
   - Spreadtrum SC9860 RTC clks
   - Nvidia Tegra MBIST workarounds and various minor fixes
   - Rockchip phase handling fixes and a memory leak plugged
   - Renesas drivers switch to readl/writel from clk_readl/clk_writel
   - Renesas gained CPU (Z/Z2) and watchdog support
   - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support
   - Qualcomm PM8921 PMIC XO buffers
   - Amlogic migrates to regmap APIs
   - TI Keystone clk latching support
   - Allwinner H3 and H5 video clk fixes
   - Broadcom BCM2835 PLLs needed another bit to enable
   - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix
   - i.MX6UL/ULL epdc_podf support
   - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits)
  clk: davinci: add a reset lookup table for psc0
  clk: imx: add clock driver for imx6sll
  dt-bindings: imx: update clock doc for imx6sll
  clk: imx: add new gate/gate2 wrapper funtion
  clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
  clk: cs2000: set pm_ops in hibernate-compatible way
  clk: bcm2835: De-assert/assert PLL reset signal when appropriate
  clk: imx7d: Move clks_init_on before any clock operations
  clk: imx7d: Correct ahb clk parent select
  clk: imx7d: Correct dram pll type
  clk: imx7d: Add USB clock information
  clk: socfpga: stratix10: add clock driver for Stratix10 platform
  dt-bindings: documentation: add clock bindings information for Stratix10
  clk: ti: fix flag space conflict with clkctrl clocks
  clk: uniphier: add additional ethernet clock lines for Pro4
  clk: uniphier: add SATA clock control support
  clk: uniphier: add PCIe clock control support
  clk: Add driver for the si544 clock generator chip
  clk: davinci: Remove redundant dev_err calls
  clk: uniphier: add ethernet clock control support for PXs3
  ...

24 files changed, 1001 insertions, 46 deletions

diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 941ac70e7f30..555937a25504 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -67,5 +67,6 @@
 #define CLKID_AO_I2C                            58
 #define CLKID_SD_EMMC_B_CLK0                    59
 #define CLKID_SD_EMMC_C_CLK0                    60
+#define CLKID_HIFI_PLL                          69
 
 #endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 067f5e501b0c..fab30b3f78b2 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -22,18 +22,18 @@
 #define HISTB_OSC_CLK                   0
 #define HISTB_APB_CLK                   1
 #define HISTB_AHB_CLK                   2
-#define HISTB_UART1_CLK         3
-#define HISTB_UART2_CLK         4
-#define HISTB_UART3_CLK         5
-#define HISTB_I2C0_CLK          6
-#define HISTB_I2C1_CLK          7
-#define HISTB_I2C2_CLK          8
-#define HISTB_I2C3_CLK          9
-#define HISTB_I2C4_CLK          10
-#define HISTB_I2C5_CLK          11
-#define HISTB_SPI0_CLK          12
-#define HISTB_SPI1_CLK          13
-#define HISTB_SPI2_CLK          14
+#define HISTB_UART1_CLK                 3
+#define HISTB_UART2_CLK                 4
+#define HISTB_UART3_CLK                 5
+#define HISTB_I2C0_CLK                  6
+#define HISTB_I2C1_CLK                  7
+#define HISTB_I2C2_CLK                  8
+#define HISTB_I2C3_CLK                  9
+#define HISTB_I2C4_CLK                  10
+#define HISTB_I2C5_CLK                  11
+#define HISTB_SPI0_CLK                  12
+#define HISTB_SPI1_CLK                  13
+#define HISTB_SPI2_CLK                  14
 #define HISTB_SCI_CLK                   15
 #define HISTB_FMC_CLK                   16
 #define HISTB_MMC_BIU_CLK               17
@@ -43,7 +43,7 @@
 #define HISTB_SDIO0_BIU_CLK             21
 #define HISTB_SDIO0_CIU_CLK             22
 #define HISTB_SDIO0_DRV_CLK             23
-#define HISTB_SDIO0_SAMPLE_CLK  24
+#define HISTB_SDIO0_SAMPLE_CLK          24
 #define HISTB_PCIE_AUX_CLK              25
 #define HISTB_PCIE_PIPE_CLK             26
 #define HISTB_PCIE_SYS_CLK              27
@@ -53,21 +53,22 @@
 #define HISTB_ETH1_MAC_CLK              31
 #define HISTB_ETH1_MACIF_CLK            32
 #define HISTB_COMBPHY1_CLK              33
-#define HISTB_USB2_BUS_CLK      34
-#define HISTB_USB2_PHY_CLK      35
-#define HISTB_USB2_UTMI_CLK     36
-#define HISTB_USB2_12M_CLK      37
-#define HISTB_USB2_48M_CLK      38
-#define HISTB_USB2_OTG_UTMI_CLK 39
-#define HISTB_USB2_PHY1_REF_CLK 40
-#define HISTB_USB2_PHY2_REF_CLK 41
+#define HISTB_USB2_BUS_CLK              34
+#define HISTB_USB2_PHY_CLK              35
+#define HISTB_USB2_UTMI_CLK             36
+#define HISTB_USB2_12M_CLK              37
+#define HISTB_USB2_48M_CLK              38
+#define HISTB_USB2_OTG_UTMI_CLK         39
+#define HISTB_USB2_PHY1_REF_CLK         40
+#define HISTB_USB2_PHY2_REF_CLK         41
+#define HISTB_COMBPHY0_CLK              42
 
 /* clocks provided by mcu CRG */
-#define HISTB_MCE_CLK   1
-#define HISTB_IR_CLK    2
-#define HISTB_TIMER01_CLK       3
-#define HISTB_LEDC_CLK  4
-#define HISTB_UART0_CLK 5
-#define HISTB_LSADC_CLK 6
+#define HISTB_MCE_CLK                   1
+#define HISTB_IR_CLK                    2
+#define HISTB_TIMER01_CLK               3
+#define HISTB_LEDC_CLK                  4
+#define HISTB_UART0_CLK                 5
+#define HISTB_LSADC_CLK                 6
 
 #endif  /* __DTS_HISTB_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 000000000000..151111e68f4f
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY               0
+#define IMX6SLL_CLK_CKIL                1
+#define IMX6SLL_CLK_OSC                 2
+#define IMX6SLL_PLL1_BYPASS_SRC         3
+#define IMX6SLL_PLL2_BYPASS_SRC         4
+#define IMX6SLL_PLL3_BYPASS_SRC         5
+#define IMX6SLL_PLL4_BYPASS_SRC         6
+#define IMX6SLL_PLL5_BYPASS_SRC         7
+#define IMX6SLL_PLL6_BYPASS_SRC         8
+#define IMX6SLL_PLL7_BYPASS_SRC         9
+#define IMX6SLL_CLK_PLL1                10
+#define IMX6SLL_CLK_PLL2                11
+#define IMX6SLL_CLK_PLL3                12
+#define IMX6SLL_CLK_PLL4                13
+#define IMX6SLL_CLK_PLL5                14
+#define IMX6SLL_CLK_PLL6                15
+#define IMX6SLL_CLK_PLL7                16
+#define IMX6SLL_PLL1_BYPASS             17
+#define IMX6SLL_PLL2_BYPASS             18
+#define IMX6SLL_PLL3_BYPASS             19
+#define IMX6SLL_PLL4_BYPASS             20
+#define IMX6SLL_PLL5_BYPASS             21
+#define IMX6SLL_PLL6_BYPASS             22
+#define IMX6SLL_PLL7_BYPASS             23
+#define IMX6SLL_CLK_PLL1_SYS            24
+#define IMX6SLL_CLK_PLL2_BUS            25
+#define IMX6SLL_CLK_PLL3_USB_OTG        26
+#define IMX6SLL_CLK_PLL4_AUDIO          27
+#define IMX6SLL_CLK_PLL5_VIDEO          28
+#define IMX6SLL_CLK_PLL6_ENET           29
+#define IMX6SLL_CLK_PLL7_USB_HOST       30
+#define IMX6SLL_CLK_USBPHY1             31
+#define IMX6SLL_CLK_USBPHY2             32
+#define IMX6SLL_CLK_USBPHY1_GATE        33
+#define IMX6SLL_CLK_USBPHY2_GATE        34
+#define IMX6SLL_CLK_PLL2_PFD0           35
+#define IMX6SLL_CLK_PLL2_PFD1           36
+#define IMX6SLL_CLK_PLL2_PFD2           37
+#define IMX6SLL_CLK_PLL2_PFD3           38
+#define IMX6SLL_CLK_PLL3_PFD0           39
+#define IMX6SLL_CLK_PLL3_PFD1           40
+#define IMX6SLL_CLK_PLL3_PFD2           41
+#define IMX6SLL_CLK_PLL3_PFD3           42
+#define IMX6SLL_CLK_PLL4_POST_DIV       43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV      44
+#define IMX6SLL_CLK_PLL5_POST_DIV       45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV      46
+#define IMX6SLL_CLK_PLL2_198M           47
+#define IMX6SLL_CLK_PLL3_120M           48
+#define IMX6SLL_CLK_PLL3_80M            49
+#define IMX6SLL_CLK_PLL3_60M            50
+#define IMX6SLL_CLK_STEP                51
+#define IMX6SLL_CLK_PLL1_SW             52
+#define IMX6SLL_CLK_AXI_ALT_SEL         53
+#define IMX6SLL_CLK_AXI_SEL             54
+#define IMX6SLL_CLK_PERIPH_PRE          55
+#define IMX6SLL_CLK_PERIPH2_PRE         56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL     57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL    58
+#define IMX6SLL_CLK_PERCLK_SEL          59
+#define IMX6SLL_CLK_USDHC1_SEL          60
+#define IMX6SLL_CLK_USDHC2_SEL          61
+#define IMX6SLL_CLK_USDHC3_SEL          62
+#define IMX6SLL_CLK_SSI1_SEL            63
+#define IMX6SLL_CLK_SSI2_SEL            64
+#define IMX6SLL_CLK_SSI3_SEL            65
+#define IMX6SLL_CLK_PXP_SEL             66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL       67
+#define IMX6SLL_CLK_LCDIF_SEL           68
+#define IMX6SLL_CLK_EPDC_PRE_SEL        69
+#define IMX6SLL_CLK_SPDIF_SEL           70
+#define IMX6SLL_CLK_ECSPI_SEL           71
+#define IMX6SLL_CLK_UART_SEL            72
+#define IMX6SLL_CLK_ARM                 73
+#define IMX6SLL_CLK_PERIPH              74
+#define IMX6SLL_CLK_PERIPH2             75
+#define IMX6SLL_CLK_PERIPH2_CLK2        76
+#define IMX6SLL_CLK_PERIPH_CLK2         77
+#define IMX6SLL_CLK_MMDC_PODF           78
+#define IMX6SLL_CLK_AXI_PODF            79
+#define IMX6SLL_CLK_AHB                 80
+#define IMX6SLL_CLK_IPG                 81
+#define IMX6SLL_CLK_PERCLK              82
+#define IMX6SLL_CLK_USDHC1_PODF         83
+#define IMX6SLL_CLK_USDHC2_PODF         84
+#define IMX6SLL_CLK_USDHC3_PODF         85
+#define IMX6SLL_CLK_SSI1_PRED           86
+#define IMX6SLL_CLK_SSI2_PRED           87
+#define IMX6SLL_CLK_SSI3_PRED           88
+#define IMX6SLL_CLK_SSI1_PODF           89
+#define IMX6SLL_CLK_SSI2_PODF           90
+#define IMX6SLL_CLK_SSI3_PODF           91
+#define IMX6SLL_CLK_PXP_PODF            92
+#define IMX6SLL_CLK_LCDIF_PRED          93
+#define IMX6SLL_CLK_LCDIF_PODF          94
+#define IMX6SLL_CLK_EPDC_SEL            95
+#define IMX6SLL_CLK_EPDC_PODF           96
+#define IMX6SLL_CLK_SPDIF_PRED          97
+#define IMX6SLL_CLK_SPDIF_PODF          98
+#define IMX6SLL_CLK_ECSPI_PODF          99
+#define IMX6SLL_CLK_UART_PODF           100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1             101
+#define IMX6SLL_CLK_AIPSTZ2             102
+#define IMX6SLL_CLK_DCP                 103
+#define IMX6SLL_CLK_UART2_IPG           104
+#define IMX6SLL_CLK_UART2_SERIAL        105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1              106
+#define IMX6SLL_CLK_ECSPI2              107
+#define IMX6SLL_CLK_ECSPI3              108
+#define IMX6SLL_CLK_ECSPI4              109
+#define IMX6SLL_CLK_UART3_IPG           110
+#define IMX6SLL_CLK_UART3_SERIAL        111
+#define IMX6SLL_CLK_UART4_IPG           112
+#define IMX6SLL_CLK_UART4_SERIAL        113
+#define IMX6SLL_CLK_EPIT1               114
+#define IMX6SLL_CLK_EPIT2               115
+#define IMX6SLL_CLK_GPT_BUS             116
+#define IMX6SLL_CLK_GPT_SERIAL          117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI                 118
+#define IMX6SLL_CLK_I2C1                119
+#define IMX6SLL_CLK_I2C2                120
+#define IMX6SLL_CLK_I2C3                121
+#define IMX6SLL_CLK_OCOTP               122
+#define IMX6SLL_CLK_LCDIF_APB           123
+#define IMX6SLL_CLK_PXP                 124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG           125
+#define IMX6SLL_CLK_UART5_SERIAL        126
+#define IMX6SLL_CLK_EPDC_AXI            127
+#define IMX6SLL_CLK_EPDC_PIX            128
+#define IMX6SLL_CLK_LCDIF_PIX           129
+#define IMX6SLL_CLK_WDOG1               130
+#define IMX6SLL_CLK_MMDC_P0_FAST        131
+#define IMX6SLL_CLK_MMDC_P0_IPG         132
+#define IMX6SLL_CLK_OCRAM               133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1                134
+#define IMX6SLL_CLK_PWM2                135
+#define IMX6SLL_CLK_PWM3                136
+#define IMX6SLL_CLK_PWM4                137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM                 138
+#define IMX6SLL_CLK_SDMA                139
+#define IMX6SLL_CLK_KPP                 140
+#define IMX6SLL_CLK_WDOG2               141
+#define IMX6SLL_CLK_SPBA                142
+#define IMX6SLL_CLK_SPDIF               143
+#define IMX6SLL_CLK_SPDIF_GCLK          144
+#define IMX6SLL_CLK_SSI1                145
+#define IMX6SLL_CLK_SSI1_IPG            146
+#define IMX6SLL_CLK_SSI2                147
+#define IMX6SLL_CLK_SSI2_IPG            148
+#define IMX6SLL_CLK_SSI3                149
+#define IMX6SLL_CLK_SSI3_IPG            150
+#define IMX6SLL_CLK_UART1_IPG           151
+#define IMX6SLL_CLK_UART1_SERIAL        152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3              153
+#define IMX6SLL_CLK_USDHC1              154
+#define IMX6SLL_CLK_USDHC2              155
+#define IMX6SLL_CLK_USDHC3              156
+
+#define IMX6SLL_CLK_IPP_DI0             157
+#define IMX6SLL_CLK_IPP_DI1             158
+#define IMX6SLL_CLK_LDB_DI0_SEL         159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5     160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7       161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL     162
+#define IMX6SLL_CLK_LDB_DI0             163
+#define IMX6SLL_CLK_LDB_DI1_SEL         164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5     165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7       166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL     167
+#define IMX6SLL_CLK_LDB_DI1             168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL    169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED   170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
+#define IMX6SLL_CLK_EXTERN_AUDIO        172
+
+#define IMX6SLL_CLK_END                 173
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 551f7600ab58..24e93dfcee9f 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -176,7 +176,8 @@
 #define CLK_TOP_AUD_EXT1                        156
 #define CLK_TOP_AUD_EXT2                        157
 #define CLK_TOP_NFI1X_PAD                       158
-#define CLK_TOP_NR                              159
+#define CLK_TOP_AXISEL_D4                       159
+#define CLK_TOP_NR                              160
 
 /* APMIXEDSYS */
 
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 48a8e797a617..76265836a1e1 100644
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -222,7 +222,13 @@
 #define CLK_TOP_APLL_DIV_PDN5           183
 #define CLK_TOP_APLL_DIV_PDN6           184
 #define CLK_TOP_APLL_DIV_PDN7           185
-#define CLK_TOP_NR_CLK                  186
+#define CLK_TOP_APLL1_D3                186
+#define CLK_TOP_APLL1_REF_SEL           187
+#define CLK_TOP_APLL2_REF_SEL           188
+#define CLK_TOP_NFI2X_EN                189
+#define CLK_TOP_NFIECC_EN               190
+#define CLK_TOP_NFI1X_CK_EN             191
+#define CLK_TOP_NR_CLK                  192
 
 /* INFRACFG */
 
@@ -281,7 +287,9 @@
 #define CLK_PERI_MSDC30_3_EN            41
 #define CLK_PERI_MSDC50_0_HCLK_EN       42
 #define CLK_PERI_MSDC50_3_HCLK_EN       43
-#define CLK_PERI_NR_CLK                 44
+#define CLK_PERI_MSDC30_0_QTR_EN        44
+#define CLK_PERI_MSDC30_3_QTR_EN        45
+#define CLK_PERI_NR_CLK                 46
 
 /* MCUCFG */
 
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 3e514ed51d15..e9d77f0e8bce 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -235,7 +235,8 @@
 #define CLK_AUDIO_MEM_ASRC3             43
 #define CLK_AUDIO_MEM_ASRC4             44
 #define CLK_AUDIO_MEM_ASRC5             45
-#define CLK_AUDIO_NR_CLK                46
+#define CLK_AUDIO_AFE_CONN              46
+#define CLK_AUDIO_NR_CLK                47
 
 /* SSUSBSYS */
 
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index b8337a5fa347..c585b82b9c05 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -40,6 +40,11 @@
 #define RPM_SMI_CLK                             22
 #define RPM_SMI_A_CLK                           23
 #define RPM_PLL4_CLK                            24
+#define RPM_XO_D0                               25
+#define RPM_XO_D1                               26
+#define RPM_XO_A0                               27
+#define RPM_XO_A1                               28
+#define RPM_XO_A2                               29
 
 /* SMD RPM clocks */
 #define RPM_SMD_XO_CLK_SRC                              0
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
new file mode 100644
index 000000000000..6d3b5a9a6084
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77965 CPG Core Clocks */
+#define R8A77965_CLK_Z                  0
+#define R8A77965_CLK_ZR                 1
+#define R8A77965_CLK_ZG                 2
+#define R8A77965_CLK_ZTR                3
+#define R8A77965_CLK_ZTRD2              4
+#define R8A77965_CLK_ZT                 5
+#define R8A77965_CLK_ZX                 6
+#define R8A77965_CLK_S0D1               7
+#define R8A77965_CLK_S0D2               8
+#define R8A77965_CLK_S0D3               9
+#define R8A77965_CLK_S0D4               10
+#define R8A77965_CLK_S0D6               11
+#define R8A77965_CLK_S0D8               12
+#define R8A77965_CLK_S0D12              13
+#define R8A77965_CLK_S1D1               14
+#define R8A77965_CLK_S1D2               15
+#define R8A77965_CLK_S1D4               16
+#define R8A77965_CLK_S2D1               17
+#define R8A77965_CLK_S2D2               18
+#define R8A77965_CLK_S2D4               19
+#define R8A77965_CLK_S3D1               20
+#define R8A77965_CLK_S3D2               21
+#define R8A77965_CLK_S3D4               22
+#define R8A77965_CLK_LB                 23
+#define R8A77965_CLK_CL                 24
+#define R8A77965_CLK_ZB3                25
+#define R8A77965_CLK_ZB3D2              26
+#define R8A77965_CLK_CR                 27
+#define R8A77965_CLK_CRD2               28
+#define R8A77965_CLK_SD0H               29
+#define R8A77965_CLK_SD0                30
+#define R8A77965_CLK_SD1H               31
+#define R8A77965_CLK_SD1                32
+#define R8A77965_CLK_SD2H               33
+#define R8A77965_CLK_SD2                34
+#define R8A77965_CLK_SD3H               35
+#define R8A77965_CLK_SD3                36
+#define R8A77965_CLK_SSP2               37
+#define R8A77965_CLK_SSP1               38
+#define R8A77965_CLK_SSPRS              39
+#define R8A77965_CLK_RPC                40
+#define R8A77965_CLK_RPCD2              41
+#define R8A77965_CLK_MSO                42
+#define R8A77965_CLK_CANFD              43
+#define R8A77965_CLK_HDMI               44
+#define R8A77965_CLK_CSI0               45
+#define R8A77965_CLK_CP                 46
+#define R8A77965_CLK_CPEX               47
+#define R8A77965_CLK_R                  48
+#define R8A77965_CLK_OSC                49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
new file mode 100644
index 000000000000..a4c0d76c392e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2                 0
+#define R8A77980_CLK_ZR                 1
+#define R8A77980_CLK_ZTR                2
+#define R8A77980_CLK_ZTRD2              3
+#define R8A77980_CLK_ZT                 4
+#define R8A77980_CLK_ZX                 5
+#define R8A77980_CLK_S0D1               6
+#define R8A77980_CLK_S0D2               7
+#define R8A77980_CLK_S0D3               8
+#define R8A77980_CLK_S0D4               9
+#define R8A77980_CLK_S0D6               10
+#define R8A77980_CLK_S0D12              11
+#define R8A77980_CLK_S0D24              12
+#define R8A77980_CLK_S1D1               13
+#define R8A77980_CLK_S1D2               14
+#define R8A77980_CLK_S1D4               15
+#define R8A77980_CLK_S2D1               16
+#define R8A77980_CLK_S2D2               17
+#define R8A77980_CLK_S2D4               18
+#define R8A77980_CLK_S3D1               19
+#define R8A77980_CLK_S3D2               20
+#define R8A77980_CLK_S3D4               21
+#define R8A77980_CLK_LB                 22
+#define R8A77980_CLK_CL                 23
+#define R8A77980_CLK_ZB3                24
+#define R8A77980_CLK_ZB3D2              25
+#define R8A77980_CLK_ZB3D4              26
+#define R8A77980_CLK_SD0H               27
+#define R8A77980_CLK_SD0                28
+#define R8A77980_CLK_RPC                29
+#define R8A77980_CLK_RPCD2              30
+#define R8A77980_CLK_MSO                31
+#define R8A77980_CLK_CANFD              32
+#define R8A77980_CLK_CSI0               33
+#define R8A77980_CLK_CP                 34
+#define R8A77980_CLK_CPEX               35
+#define R8A77980_CLK_R                  36
+#define R8A77980_CLK_OSC                37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index d2b26a4b43eb..a82a0109faff 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -193,7 +193,6 @@
 #define HCLK_VPU_PRE            324
 #define HCLK_VIO_PRE            325
 #define HCLK_VPU                326
-#define HCLK_VIO                327
 #define HCLK_BUS_PRE            328
 #define HCLK_PERI_PRE           329
 #define HCLK_H264               330
diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h
index 4cb202f090c2..f2ab4631df0d 100644
--- a/include/dt-bindings/clock/sprd,sc9860-clk.h
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -229,7 +229,26 @@
 #define CLK_SDIO1_2X_EN         65
 #define CLK_SDIO2_2X_EN         66
 #define CLK_EMMC_2X_EN          67
-#define CLK_AON_GATE_NUM        (CLK_EMMC_2X_EN + 1)
+#define CLK_ARCH_RTC_EB         68
+#define CLK_KPB_RTC_EB          69
+#define CLK_AON_SYST_RTC_EB     70
+#define CLK_AP_SYST_RTC_EB      71
+#define CLK_AON_TMR_RTC_EB      72
+#define CLK_AP_TMR0_RTC_EB      73
+#define CLK_EIC_RTC_EB          74
+#define CLK_EIC_RTCDV5_EB       75
+#define CLK_AP_WDG_RTC_EB       76
+#define CLK_AP_TMR1_RTC_EB      77
+#define CLK_AP_TMR2_RTC_EB      78
+#define CLK_DCXO_TMR_RTC_EB     79
+#define CLK_BB_CAL_RTC_EB       80
+#define CLK_AVS_BIG_RTC_EB      81
+#define CLK_AVS_LIT_RTC_EB      82
+#define CLK_AVS_GPU0_RTC_EB     83
+#define CLK_AVS_GPU1_RTC_EB     84
+#define CLK_GPU_TS_EB           85
+#define CLK_RTCDV10_EB          86
+#define CLK_AON_GATE_NUM        (CLK_RTCDV10_EB + 1)
 
 #define CLK_LIT_MCU             0
 #define CLK_BIG_MCU             1
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c203e5c..58d8b515be55 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,12 @@
 #define CLK_SAI2                11
 #define CLK_I2SQ_PDIV           12
 #define CLK_SAIQ_PDIV           13
-
-#define END_PRIMARY_CLK         14
-
 #define CLK_HSI                 14
 #define CLK_SYSCLK              15
+#define CLK_F469_DSI            16
+
+#define END_PRIMARY_CLK         17
+
 #define CLK_HDMI_CEC            16
 #define CLK_SPDIF               17
 #define CLK_USART1              18
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 000000000000..86e3ec662ef4
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
+#define _DT_BINDINGS_STM32MP1_CLKS_H_
+
+/* OSCILLATOR clocks */
+#define CK_HSE          0
+#define CK_CSI          1
+#define CK_LSI          2
+#define CK_LSE          3
+#define CK_HSI          4
+#define CK_HSE_DIV2     5
+
+/* Bus clocks */
+#define TIM2            6
+#define TIM3            7
+#define TIM4            8
+#define TIM5            9
+#define TIM6            10
+#define TIM7            11
+#define TIM12           12
+#define TIM13           13
+#define TIM14           14
+#define LPTIM1          15
+#define SPI2            16
+#define SPI3            17
+#define USART2          18
+#define USART3          19
+#define UART4           20
+#define UART5           21
+#define UART7           22
+#define UART8           23
+#define I2C1            24
+#define I2C2            25
+#define I2C3            26
+#define I2C5            27
+#define SPDIF           28
+#define CEC             29
+#define DAC12           30
+#define MDIO            31
+#define TIM1            32
+#define TIM8            33
+#define TIM15           34
+#define TIM16           35
+#define TIM17           36
+#define SPI1            37
+#define SPI4            38
+#define SPI5            39
+#define USART6          40
+#define SAI1            41
+#define SAI2            42
+#define SAI3            43
+#define DFSDM           44
+#define FDCAN           45
+#define LPTIM2          46
+#define LPTIM3          47
+#define LPTIM4          48
+#define LPTIM5          49
+#define SAI4            50
+#define SYSCFG          51
+#define VREF            52
+#define TMPSENS         53
+#define PMBCTRL         54
+#define HDP             55
+#define LTDC            56
+#define DSI             57
+#define IWDG2           58
+#define USBPHY          59
+#define STGENRO         60
+#define SPI6            61
+#define I2C4            62
+#define I2C6            63
+#define USART1          64
+#define RTCAPB          65
+#define TZC             66
+#define TZPC            67
+#define IWDG1           68
+#define BSEC            69
+#define STGEN           70
+#define DMA1            71
+#define DMA2            72
+#define DMAMUX          73
+#define ADC12           74
+#define USBO            75
+#define SDMMC3          76
+#define DCMI            77
+#define CRYP2           78
+#define HASH2           79
+#define RNG2            80
+#define CRC2            81
+#define HSEM            82
+#define IPCC            83
+#define GPIOA           84
+#define GPIOB           85
+#define GPIOC           86
+#define GPIOD           87
+#define GPIOE           88
+#define GPIOF           89
+#define GPIOG           90
+#define GPIOH           91
+#define GPIOI           92
+#define GPIOJ           93
+#define GPIOK           94
+#define GPIOZ           95
+#define CRYP1           96
+#define HASH1           97
+#define RNG1            98
+#define BKPSRAM         99
+#define MDMA            100
+#define GPU             101
+#define ETHCK           102
+#define ETHTX           103
+#define ETHRX           104
+#define ETHMAC          105
+#define FMC             106
+#define QSPI            107
+#define SDMMC1          108
+#define SDMMC2          109
+#define CRC1            110
+#define USBH            111
+#define ETHSTP          112
+
+/* Kernel clocks */
+#define SDMMC1_K        118
+#define SDMMC2_K        119
+#define SDMMC3_K        120
+#define FMC_K           121
+#define QSPI_K          122
+#define ETHCK_K         123
+#define RNG1_K          124
+#define RNG2_K          125
+#define GPU_K           126
+#define USBPHY_K        127
+#define STGEN_K         128
+#define SPDIF_K         129
+#define SPI1_K          130
+#define SPI2_K          131
+#define SPI3_K          132
+#define SPI4_K          133
+#define SPI5_K          134
+#define SPI6_K          135
+#define CEC_K           136
+#define I2C1_K          137
+#define I2C2_K          138
+#define I2C3_K          139
+#define I2C4_K          140
+#define I2C5_K          141
+#define I2C6_K          142
+#define LPTIM1_K        143
+#define LPTIM2_K        144
+#define LPTIM3_K        145
+#define LPTIM4_K        146
+#define LPTIM5_K        147
+#define USART1_K        148
+#define USART2_K        149
+#define USART3_K        150
+#define UART4_K         151
+#define UART5_K         152
+#define USART6_K        153
+#define UART7_K         154
+#define UART8_K         155
+#define DFSDM_K         156
+#define FDCAN_K         157
+#define SAI1_K          158
+#define SAI2_K          159
+#define SAI3_K          160
+#define SAI4_K          161
+#define ADC12_K         162
+#define DSI_K           163
+#define DSI_PX          164
+#define ADFSDM_K        165
+#define USBO_K          166
+#define LTDC_PX         167
+#define DAC12_K         168
+#define ETHPTP_K        169
+
+/* PLL */
+#define PLL1            176
+#define PLL2            177
+#define PLL3            178
+#define PLL4            179
+
+/* ODF */
+#define PLL1_P          180
+#define PLL1_Q          181
+#define PLL1_R          182
+#define PLL2_P          183
+#define PLL2_Q          184
+#define PLL2_R          185
+#define PLL3_P          186
+#define PLL3_Q          187
+#define PLL3_R          188
+#define PLL4_P          189
+#define PLL4_Q          190
+#define PLL4_R          191
+
+/* AUX */
+#define RTC             192
+
+/* MCLK */
+#define CK_PER          193
+#define CK_MPU          194
+#define CK_AXI          195
+#define CK_MCU          196
+
+/* Time base */
+#define TIM2_K          197
+#define TIM3_K          198
+#define TIM4_K          199
+#define TIM5_K          200
+#define TIM6_K          201
+#define TIM7_K          202
+#define TIM12_K         203
+#define TIM13_K         204
+#define TIM14_K         205
+#define TIM1_K          206
+#define TIM8_K          207
+#define TIM15_K         208
+#define TIM16_K         209
+#define TIM17_K         210
+
+/* MCO clocks */
+#define CK_MCO1         211
+#define CK_MCO2         212
+
+/* TRACE & DEBUG clocks */
+#define DBG             213
+#define CK_DBG          214
+#define CK_TRACE        215
+
+/* DDR */
+#define DDRC1           220
+#define DDRC1LP         221
+#define DDRC2           222
+#define DDRC2LP         223
+#define DDRPHYC         224
+#define DDRPHYCLP       225
+#define DDRCAPB         226
+#define DDRCAPBLP       227
+#define AXIDCG          228
+#define DDRPHYCAPB      229
+#define DDRPHYCAPBLP    230
+#define DDRPERFM        231
+
+#define STM32MP1_LAST_CLK 232
+
+#define LTDC_K          LTDC_PX
+#define ETHMAC_K        ETHCK_K
+
+#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h
new file mode 100644
index 000000000000..0ac1c90a18bf
--- /dev/null
+++ b/include/dt-bindings/clock/stratix10-clock.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier:     GPL-2.0 */
+/*
+ * Copyright (C) 2017, Intel Corporation
+ */
+
+#ifndef __STRATIX10_CLOCK_H
+#define __STRATIX10_CLOCK_H
+
+/* fixed rate clocks */
+#define STRATIX10_OSC1                  0
+#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1
+#define STRATIX10_CB_INTOSC_LS_CLK      2
+#define STRATIX10_F2S_FREE_CLK          3
+
+/* fixed factor clocks */
+#define STRATIX10_L4_SYS_FREE_CLK       4
+#define STRATIX10_MPU_PERIPH_CLK        5
+#define STRATIX10_MPU_L2RAM_CLK         6
+#define STRATIX10_SDMMC_CIU_CLK         7
+
+/* PLL clocks */
+#define STRATIX10_MAIN_PLL_CLK          8
+#define STRATIX10_PERIPH_PLL_CLK        9
+#define STRATIX10_BOOT_CLK              10
+
+/* Periph clocks */
+#define STRATIX10_MAIN_MPU_BASE_CLK     11
+#define STRATIX10_MAIN_NOC_BASE_CLK     12
+#define STRATIX10_MAIN_EMACA_CLK        13
+#define STRATIX10_MAIN_EMACB_CLK        14
+#define STRATIX10_MAIN_EMAC_PTP_CLK     15
+#define STRATIX10_MAIN_GPIO_DB_CLK      16
+#define STRATIX10_MAIN_SDMMC_CLK        17
+#define STRATIX10_MAIN_S2F_USR0_CLK     18
+#define STRATIX10_MAIN_S2F_USR1_CLK     19
+#define STRATIX10_MAIN_PSI_REF_CLK      20
+
+#define STRATIX10_PERI_MPU_BASE_CLK     21
+#define STRATIX10_PERI_NOC_BASE_CLK     22
+#define STRATIX10_PERI_EMACA_CLK        23
+#define STRATIX10_PERI_EMACB_CLK        24
+#define STRATIX10_PERI_EMAC_PTP_CLK     25
+#define STRATIX10_PERI_GPIO_DB_CLK      26
+#define STRATIX10_PERI_SDMMC_CLK        27
+#define STRATIX10_PERI_S2F_USR0_CLK     28
+#define STRATIX10_PERI_S2F_USR1_CLK     29
+#define STRATIX10_PERI_PSI_REF_CLK      30
+
+#define STRATIX10_MPU_FREE_CLK          31
+#define STRATIX10_NOC_FREE_CLK          32
+#define STRATIX10_S2F_USR0_CLK          33
+#define STRATIX10_NOC_CLK               34
+#define STRATIX10_EMAC_A_FREE_CLK       35
+#define STRATIX10_EMAC_B_FREE_CLK       36
+#define STRATIX10_EMAC_PTP_FREE_CLK     37
+#define STRATIX10_GPIO_DB_FREE_CLK      38
+#define STRATIX10_SDMMC_FREE_CLK        39
+#define STRATIX10_S2F_USER1_FREE_CLK    40
+#define STRATIX10_PSI_REF_FREE_CLK      41
+
+/* Gate clocks */
+#define STRATIX10_MPU_CLK               42
+#define STRATIX10_L4_MAIN_CLK           43
+#define STRATIX10_L4_MP_CLK             44
+#define STRATIX10_L4_SP_CLK             45
+#define STRATIX10_CS_AT_CLK             46
+#define STRATIX10_CS_TRACE_CLK          47
+#define STRATIX10_CS_PDBG_CLK           48
+#define STRATIX10_CS_TIMER_CLK          49
+#define STRATIX10_S2F_USER0_CLK         50
+#define STRATIX10_S2F_USER1_CLK         51
+#define STRATIX10_EMAC0_CLK             52
+#define STRATIX10_EMAC1_CLK             53
+#define STRATIX10_EMAC2_CLK             54
+#define STRATIX10_EMAC_PTP_CLK          55
+#define STRATIX10_GPIO_DB_CLK           56
+#define STRATIX10_SDMMC_CLK             57
+#define STRATIX10_PSI_REF_CLK           58
+#define STRATIX10_USB_CLK               59
+#define STRATIX10_SPI_M_CLK             60
+#define STRATIX10_NAND_CLK              61
+#define STRATIX10_NUM_CLKS              62
+
+#endif  /* __STRATIX10_CLOCK_H */
diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h
new file mode 100644
index 000000000000..a1545cd60e75
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-ccu.h
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_H_
+
+#define CLK_PLL_PERIPH0         3
+
+#define CLK_CPUX                21
+
+#define CLK_APB1                26
+
+#define CLK_DE                  29
+#define CLK_BUS_DE              30
+#define CLK_DEINTERLACE         31
+#define CLK_BUS_DEINTERLACE     32
+#define CLK_GPU                 33
+#define CLK_BUS_GPU             34
+#define CLK_CE                  35
+#define CLK_BUS_CE              36
+#define CLK_VE                  37
+#define CLK_BUS_VE              38
+#define CLK_EMCE                39
+#define CLK_BUS_EMCE            40
+#define CLK_VP9                 41
+#define CLK_BUS_VP9             42
+#define CLK_BUS_DMA             43
+#define CLK_BUS_MSGBOX          44
+#define CLK_BUS_SPINLOCK        45
+#define CLK_BUS_HSTIMER         46
+#define CLK_AVS                 47
+#define CLK_BUS_DBG             48
+#define CLK_BUS_PSI             49
+#define CLK_BUS_PWM             50
+#define CLK_BUS_IOMMU           51
+
+#define CLK_MBUS_DMA            53
+#define CLK_MBUS_VE             54
+#define CLK_MBUS_CE             55
+#define CLK_MBUS_TS             56
+#define CLK_MBUS_NAND           57
+#define CLK_MBUS_CSI            58
+#define CLK_MBUS_DEINTERLACE    59
+
+#define CLK_NAND0               61
+#define CLK_NAND1               62
+#define CLK_BUS_NAND            63
+#define CLK_MMC0                64
+#define CLK_MMC1                65
+#define CLK_MMC2                66
+#define CLK_BUS_MMC0            67
+#define CLK_BUS_MMC1            68
+#define CLK_BUS_MMC2            69
+#define CLK_BUS_UART0           70
+#define CLK_BUS_UART1           71
+#define CLK_BUS_UART2           72
+#define CLK_BUS_UART3           73
+#define CLK_BUS_I2C0            74
+#define CLK_BUS_I2C1            75
+#define CLK_BUS_I2C2            76
+#define CLK_BUS_I2C3            77
+#define CLK_BUS_SCR0            78
+#define CLK_BUS_SCR1            79
+#define CLK_SPI0                80
+#define CLK_SPI1                81
+#define CLK_BUS_SPI0            82
+#define CLK_BUS_SPI1            83
+#define CLK_BUS_EMAC            84
+#define CLK_TS                  85
+#define CLK_BUS_TS              86
+#define CLK_IR_TX               87
+#define CLK_BUS_IR_TX           88
+#define CLK_BUS_THS             89
+#define CLK_I2S3                90
+#define CLK_I2S0                91
+#define CLK_I2S1                92
+#define CLK_I2S2                93
+#define CLK_BUS_I2S0            94
+#define CLK_BUS_I2S1            95
+#define CLK_BUS_I2S2            96
+#define CLK_BUS_I2S3            97
+#define CLK_SPDIF               98
+#define CLK_BUS_SPDIF           99
+#define CLK_DMIC                100
+#define CLK_BUS_DMIC            101
+#define CLK_AUDIO_HUB           102
+#define CLK_BUS_AUDIO_HUB       103
+#define CLK_USB_OHCI0           104
+#define CLK_USB_PHY0            105
+#define CLK_USB_PHY1            106
+#define CLK_USB_OHCI3           107
+#define CLK_USB_PHY3            108
+#define CLK_USB_HSIC_12M        109
+#define CLK_USB_HSIC            110
+#define CLK_BUS_OHCI0           111
+#define CLK_BUS_OHCI3           112
+#define CLK_BUS_EHCI0           113
+#define CLK_BUS_XHCI            114
+#define CLK_BUS_EHCI3           115
+#define CLK_BUS_OTG             116
+#define CLK_PCIE_REF_100M       117
+#define CLK_PCIE_REF            118
+#define CLK_PCIE_REF_OUT        119
+#define CLK_PCIE_MAXI           120
+#define CLK_PCIE_AUX            121
+#define CLK_BUS_PCIE            122
+#define CLK_HDMI                123
+#define CLK_HDMI_SLOW           124
+#define CLK_HDMI_CEC            125
+#define CLK_BUS_HDMI            126
+#define CLK_BUS_TCON_TOP        127
+#define CLK_TCON_LCD0           128
+#define CLK_BUS_TCON_LCD0       129
+#define CLK_TCON_TV0            130
+#define CLK_BUS_TCON_TV0        131
+#define CLK_CSI_CCI             132
+#define CLK_CSI_TOP             133
+#define CLK_CSI_MCLK            134
+#define CLK_BUS_CSI             135
+#define CLK_HDCP                136
+#define CLK_BUS_HDCP            137
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index e139fe5c62ec..c5f7e9a70968 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -43,6 +43,8 @@
 #ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
 #define _DT_BINDINGS_CLK_SUN8I_H3_H_
 
+#define CLK_PLL_VIDEO           6
+
 #define CLK_PLL_PERIPH0         9
 
 #define CLK_CPUX                14
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 6422314e46eb..6b77e721f6b1 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -95,7 +95,7 @@
 #define TEGRA210_CLK_CSITE 73
 /* 74 */
 /* 75 */
-/* 76 */
+#define TEGRA210_CLK_LA 76
 /* 77 */
 #define TEGRA210_CLK_SOC_THERM 78
 #define TEGRA210_CLK_DTV 79
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h
new file mode 100644
index 000000000000..81106f455097
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-ccu.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
+#define _DT_BINDINGS_RESET_SUN50I_H6_H_
+
+#define RST_MBUS                0
+#define RST_BUS_DE              1
+#define RST_BUS_DEINTERLACE     2
+#define RST_BUS_GPU             3
+#define RST_BUS_CE              4
+#define RST_BUS_VE              5
+#define RST_BUS_EMCE            6
+#define RST_BUS_VP9             7
+#define RST_BUS_DMA             8
+#define RST_BUS_MSGBOX          9
+#define RST_BUS_SPINLOCK        10
+#define RST_BUS_HSTIMER         11
+#define RST_BUS_DBG             12
+#define RST_BUS_PSI             13
+#define RST_BUS_PWM             14
+#define RST_BUS_IOMMU           15
+#define RST_BUS_DRAM            16
+#define RST_BUS_NAND            17
+#define RST_BUS_MMC0            18
+#define RST_BUS_MMC1            19
+#define RST_BUS_MMC2            20
+#define RST_BUS_UART0           21
+#define RST_BUS_UART1           22
+#define RST_BUS_UART2           23
+#define RST_BUS_UART3           24
+#define RST_BUS_I2C0            25
+#define RST_BUS_I2C1            26
+#define RST_BUS_I2C2            27
+#define RST_BUS_I2C3            28
+#define RST_BUS_SCR0            29
+#define RST_BUS_SCR1            30
+#define RST_BUS_SPI0            31
+#define RST_BUS_SPI1            32
+#define RST_BUS_EMAC            33
+#define RST_BUS_TS              34
+#define RST_BUS_IR_TX           35
+#define RST_BUS_THS             36
+#define RST_BUS_I2S0            37
+#define RST_BUS_I2S1            38
+#define RST_BUS_I2S2            39
+#define RST_BUS_I2S3            40
+#define RST_BUS_SPDIF           41
+#define RST_BUS_DMIC            42
+#define RST_BUS_AUDIO_HUB       43
+#define RST_USB_PHY0            44
+#define RST_USB_PHY1            45
+#define RST_USB_PHY3            46
+#define RST_USB_HSIC            47
+#define RST_BUS_OHCI0           48
+#define RST_BUS_OHCI3           49
+#define RST_BUS_EHCI0           50
+#define RST_BUS_XHCI            51
+#define RST_BUS_EHCI3           52
+#define RST_BUS_OTG             53
+#define RST_BUS_PCIE            54
+#define RST_PCIE_POWERUP        55
+#define RST_BUS_HDMI            56
+#define RST_BUS_HDMI_SUB        57
+#define RST_BUS_TCON_TOP        58
+#define RST_BUS_TCON_LCD0       59
+#define RST_BUS_TCON_TV0        60
+#define RST_BUS_CSI             61
+#define RST_BUS_HDCP            62
+
+#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f711be6e8c44..210a890008f9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -399,6 +399,7 @@ struct clk_divider {
         spinlock_t      *lock;
 };
 
+#define clk_div_mask(width)     ((1 << (width)) - 1)
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define CLK_DIVIDER_ONE_BASED           BIT(0)
@@ -419,6 +420,10 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
                                unsigned long rate, unsigned long *prate,
                                const struct clk_div_table *table,
                                u8 width, unsigned long flags);
+long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+                                  unsigned long rate, unsigned long *prate,
+                                  const struct clk_div_table *table, u8 width,
+                                  unsigned long flags, unsigned int val);
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
                 const struct clk_div_table *table, u8 width,
                 unsigned long flags);
@@ -449,8 +454,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
  *
  * @hw:         handle between common and hardware-specific interfaces
  * @reg:        register controlling multiplexer
+ * @table:      array of register values corresponding to the parent index
  * @shift:      shift to multiplexer bit field
- * @width:      width of mutliplexer bit field
+ * @mask:       mask of mutliplexer bit field
  * @flags:      hardware-specific flags
  * @lock:       register lock
  *
@@ -510,6 +516,10 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
                 void __iomem *reg, u8 shift, u32 mask,
                 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 
+int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
+                         unsigned int val);
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
 void clk_unregister_mux(struct clk *clk);
 void clk_hw_unregister_mux(struct clk_hw *hw);
 
@@ -774,6 +784,17 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
                                          rate, prate, table, width, flags);
 }
 
+static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *prate,
+                                         const struct clk_div_table *table,
+                                         u8 width, unsigned long flags,
+                                         unsigned int val)
+{
+        return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
+                                            rate, prate, table, width, flags,
+                                            val);
+}
+
 /*
  * FIXME clock api without lock protection
  */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 4c4ef9f34db3..0dbd0885b2c2 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -209,7 +209,7 @@ static inline int clk_prepare(struct clk *clk)
         return 0;
 }
 
-static inline int clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
 {
         might_sleep();
         return 0;
@@ -603,8 +603,8 @@ static inline struct clk *clk_get(struct device *dev, const char *id)
         return NULL;
 }
 
-static inline int clk_bulk_get(struct device *dev, int num_clks,
-                               struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_get(struct device *dev, int num_clks,
+                                            struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -614,8 +614,8 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id)
         return NULL;
 }
 
-static inline int devm_clk_bulk_get(struct device *dev, int num_clks,
-                                    struct clk_bulk_data *clks)
+static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
+                                                 struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -645,7 +645,7 @@ static inline int clk_enable(struct clk *clk)
         return 0;
 }
 
-static inline int clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -719,8 +719,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
         clk_unprepare(clk);
 }
 
-static inline int clk_bulk_prepare_enable(int num_clks,
-                                          struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_prepare_enable(int num_clks,
+                                        struct clk_bulk_data *clks)
 {
         int ret;
 
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index d23c9cf26993..afb9edfa5d58 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -128,5 +128,6 @@ extern void tegra210_sata_pll_hw_sequence_start(void);
 extern void tegra210_set_sata_pll_seq_sw(bool state);
 extern void tegra210_put_utmipll_in_iddq(void);
 extern void tegra210_put_utmipll_out_iddq(void);
+extern int tegra210_clk_handle_mbist_war(unsigned int id);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 7e3bceee3489..a8faa38b1ed6 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -212,6 +212,7 @@ enum {
  * struct ti_clk_ll_ops - low-level ops for clocks
  * @clk_readl: pointer to register read function
  * @clk_writel: pointer to register write function
+ * @clk_rmw: pointer to register read-modify-write function
  * @clkdm_clk_enable: pointer to clockdomain enable function
  * @clkdm_clk_disable: pointer to clockdomain disable function
  * @clkdm_lookup: pointer to clockdomain lookup function
@@ -227,6 +228,7 @@ enum {
 struct ti_clk_ll_ops {
         u32     (*clk_readl)(const struct clk_omap_reg *reg);
         void    (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
+        void    (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
         int     (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
         int     (*clkdm_clk_disable)(struct clockdomain *clkdm,
                                      struct clk *clk);
diff --git a/include/linux/platform_data/clk-da8xx-cfgchip.h b/include/linux/platform_data/clk-da8xx-cfgchip.h
new file mode 100644
index 000000000000..de0f77d38669
--- /dev/null
+++ b/include/linux/platform_data/clk-da8xx-cfgchip.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver
+ *
+ * Copyright (C) 2018 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
+#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
+
+#include <linux/regmap.h>
+
+/**
+ * da8xx_cfgchip_clk_platform_data
+ * @cfgchip: CFGCHIP syscon regmap
+ */
+struct da8xx_cfgchip_clk_platform_data {
+        struct regmap *cfgchip;
+};
+
+#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */
diff --git a/include/linux/platform_data/clk-davinci-pll.h b/include/linux/platform_data/clk-davinci-pll.h
new file mode 100644
index 000000000000..e55dab1d578b
--- /dev/null
+++ b/include/linux/platform_data/clk-davinci-pll.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock driver for TI Davinci SoCs
+ *
+ * Copyright (C) 2018 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__
+#define __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__
+
+#include <linux/regmap.h>
+
+/**
+ * davinci_pll_platform_data
+ * @cfgchip: CFGCHIP syscon regmap
+ */
+struct davinci_pll_platform_data {
+        struct regmap *cfgchip;
+};
+
+#endif /* __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ */