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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:35:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:35:03 -0400
commitad363e0916423b2e6cdfcdc30ae707ec709f0a65 (patch)
treec47cc9062f7adc0ceb27f634b63b8548b733f01c /include
parented0795aa12129df9f3d2cc81ee579a9e54e12885 (diff)
parent1032fbfd792f2b384ac16a63993b8fae5eea9083 (diff)
Merge branch 'for-torvalds' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson
* 'for-torvalds' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: mach-ux500: voltage domain regulators for DB8500 cpufreq: make DB8500 cpufreq driver compile cpufreq: update DB8500 cpufreq driver mach-ux500: move CPUfreq driver to cpufreq subsystem mfd: add DB5500 PRCMU driver mfd: update DB8500 PRCMU driver mach-ux500: move the DB8500 PRCMU driver to MFD mach-ux500: make PRCMU base address dynamic mach-ux500: rename PRCMU driver per SoC mach-ux500: update ASIC version detection mach-ux500: update SoC and board IRQ handling mach-ux500: update the DB5500 register file mach-ux500: update the DB8500 register file
Diffstat (limited to 'include')
-rw-r--r--include/linux/mfd/db5500-prcmu.h45
-rw-r--r--include/linux/mfd/db8500-prcmu.h978
-rw-r--r--include/linux/regulator/db8500-prcmu.h45
3 files changed, 1068 insertions, 0 deletions
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
new file mode 100644
index 000000000000..f0977986402c
--- /dev/null
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MACH_PRCMU_U5500_H
9#define __MACH_PRCMU_U5500_H
10
11#ifdef CONFIG_UX500_SOC_DB5500
12
13void db5500_prcmu_early_init(void);
14
15int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
16int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
17
18#else /* !CONFIG_UX500_SOC_DB5500 */
19
20static inline void db5500_prcmu_early_init(void)
21{
22}
23
24static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
25{
26 return -ENOSYS;
27}
28
29static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
30{
31 return -ENOSYS;
32}
33
34#endif /* CONFIG_UX500_SOC_DB5500 */
35
36static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
37{
38#ifdef CONFIG_MACH_U5500_SIMULATOR
39 return 0;
40#else
41 return -1;
42#endif
43}
44
45#endif /* __MACH_PRCMU_U5500_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
new file mode 100644
index 000000000000..917dbcab701c
--- /dev/null
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -0,0 +1,978 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 *
8 * PRCMU f/w APIs
9 */
10#ifndef __MFD_DB8500_PRCMU_H
11#define __MFD_DB8500_PRCMU_H
12
13#include <linux/interrupt.h>
14#include <linux/notifier.h>
15
16/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
17
18/**
19 * enum state - ON/OFF state definition
20 * @OFF: State is ON
21 * @ON: State is OFF
22 *
23 */
24enum state {
25 OFF = 0x0,
26 ON = 0x1,
27};
28
29/**
30 * enum ret_state - general purpose On/Off/Retention states
31 *
32 */
33enum ret_state {
34 OFFST = 0,
35 ONST = 1,
36 RETST = 2
37};
38
39/**
40 * enum clk_arm - ARM Cortex A9 clock schemes
41 * @A9_OFF:
42 * @A9_BOOT:
43 * @A9_OPPT1:
44 * @A9_OPPT2:
45 * @A9_EXTCLK:
46 */
47enum clk_arm {
48 A9_OFF,
49 A9_BOOT,
50 A9_OPPT1,
51 A9_OPPT2,
52 A9_EXTCLK
53};
54
55/**
56 * enum clk_gen - GEN#0/GEN#1 clock schemes
57 * @GEN_OFF:
58 * @GEN_BOOT:
59 * @GEN_OPPT1:
60 */
61enum clk_gen {
62 GEN_OFF,
63 GEN_BOOT,
64 GEN_OPPT1,
65};
66
67/* some information between arm and xp70 */
68
69/**
70 * enum romcode_write - Romcode message written by A9 AND read by XP70
71 * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
72 * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
73 * romcode. The xp70 will go into self-reset
74 */
75enum romcode_write {
76 RDY_2_DS = 0x09,
77 RDY_2_XP70_RST = 0x10
78};
79
80/**
81 * enum romcode_read - Romcode message written by XP70 and read by A9
82 * @INIT: Init value when romcode field is not used
83 * @FS_2_DS: Value set when power state is going from ApExecute to
84 * ApDeepSleep
85 * @END_DS: Value set when ApDeepSleep power state is reached coming from
86 * ApExecute state
87 * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
88 * ApExecute
89 * @END_FS: Value set when ApExecute power state is reached coming from
90 * ApDeepSleep state
91 * @SWR: Value set when power state is going to ApReset
92 * @END_SWR: Value set when the xp70 finished executing ApReset actions and
93 * waits for romcode acknowledgment to go to self-reset
94 */
95enum romcode_read {
96 INIT = 0x00,
97 FS_2_DS = 0x0A,
98 END_DS = 0x0B,
99 DS_TO_FS = 0x0C,
100 END_FS = 0x0D,
101 SWR = 0x0E,
102 END_SWR = 0x0F
103};
104
105/**
106 * enum ap_pwrst - current power states defined in PRCMU firmware
107 * @NO_PWRST: Current power state init
108 * @AP_BOOT: Current power state is apBoot
109 * @AP_EXECUTE: Current power state is apExecute
110 * @AP_DEEP_SLEEP: Current power state is apDeepSleep
111 * @AP_SLEEP: Current power state is apSleep
112 * @AP_IDLE: Current power state is apIdle
113 * @AP_RESET: Current power state is apReset
114 */
115enum ap_pwrst {
116 NO_PWRST = 0x00,
117 AP_BOOT = 0x01,
118 AP_EXECUTE = 0x02,
119 AP_DEEP_SLEEP = 0x03,
120 AP_SLEEP = 0x04,
121 AP_IDLE = 0x05,
122 AP_RESET = 0x06
123};
124
125/**
126 * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
127 * @NO_TRANSITION: No power state transition
128 * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
129 * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
130 * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
131 * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
132 * ApDeepSleep
133 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
134 */
135enum ap_pwrst_trans {
136 NO_TRANSITION = 0x00,
137 APEXECUTE_TO_APSLEEP = 0x01,
138 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
139 PRCMU_AP_SLEEP = 0x01,
140 APBOOT_TO_APEXECUTE = 0x03,
141 APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
142 PRCMU_AP_DEEP_SLEEP = 0x04,
143 APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
144 PRCMU_AP_IDLE = 0x05,
145 PRCMU_AP_DEEP_IDLE = 0x07,
146};
147
148/**
149 * enum ddr_pwrst - DDR power states definition
150 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
151 * @DDR_PWR_STATE_ON:
152 * @DDR_PWR_STATE_OFFLOWLAT:
153 * @DDR_PWR_STATE_OFFHIGHLAT:
154 */
155enum ddr_pwrst {
156 DDR_PWR_STATE_UNCHANGED = 0x00,
157 DDR_PWR_STATE_ON = 0x01,
158 DDR_PWR_STATE_OFFLOWLAT = 0x02,
159 DDR_PWR_STATE_OFFHIGHLAT = 0x03
160};
161
162/**
163 * enum arm_opp - ARM OPP states definition
164 * @ARM_OPP_INIT:
165 * @ARM_NO_CHANGE: The ARM operating point is unchanged
166 * @ARM_100_OPP: The new ARM operating point is arm100opp
167 * @ARM_50_OPP: The new ARM operating point is arm50opp
168 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
169 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
170 * @ARM_EXTCLK: The new ARM operating point is armExtClk
171 */
172enum arm_opp {
173 ARM_OPP_INIT = 0x00,
174 ARM_NO_CHANGE = 0x01,
175 ARM_100_OPP = 0x02,
176 ARM_50_OPP = 0x03,
177 ARM_MAX_OPP = 0x04,
178 ARM_MAX_FREQ100OPP = 0x05,
179 ARM_EXTCLK = 0x07
180};
181
182/**
183 * enum ape_opp - APE OPP states definition
184 * @APE_OPP_INIT:
185 * @APE_NO_CHANGE: The APE operating point is unchanged
186 * @APE_100_OPP: The new APE operating point is ape100opp
187 * @APE_50_OPP: 50%
188 */
189enum ape_opp {
190 APE_OPP_INIT = 0x00,
191 APE_NO_CHANGE = 0x01,
192 APE_100_OPP = 0x02,
193 APE_50_OPP = 0x03
194};
195
196/**
197 * enum hw_acc_state - State definition for hardware accelerator
198 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
199 * @HW_OFF: The hardware accelerator must be switched off
200 * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
201 * internal RAM in retention
202 * @HW_ON: The hwa hardware accelerator hwa must be switched on
203 *
204 * NOTE! Deprecated, to be removed when all users switched over to use the
205 * regulator API.
206 */
207enum hw_acc_state {
208 HW_NO_CHANGE = 0x00,
209 HW_OFF = 0x01,
210 HW_OFF_RAMRET = 0x02,
211 HW_ON = 0x04
212};
213
214/**
215 * enum mbox_2_arm_stat - Status messages definition for mbox_arm
216 * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
217 * completed
218 * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
219 * completed
220 * @SLEEPOK: The apExecute to apSleep state transition has been completed
221 * @IDLEOK: The apExecute to apIdle state transition has been completed
222 * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
223 * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
224 * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
225 * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
226 * going
227 * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
228 * going
229 * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
230 * been completed
231 * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
232 * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
233 * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
234 * completed
235 * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
236 * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
237 * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
238 * completed
239 * @INIT_STATUS: Status init
240 */
241enum ap_pwrsttr_status {
242 BOOT_TO_EXECUTEOK = 0xFF,
243 DEEPSLEEPOK = 0xFE,
244 SLEEPOK = 0xFD,
245 IDLEOK = 0xFC,
246 SOFTRESETOK = 0xFB,
247 SOFTRESETGO = 0xFA,
248 BOOT_TO_EXECUTE = 0xF9,
249 EXECUTE_TO_DEEPSLEEP = 0xF8,
250 DEEPSLEEP_TO_EXECUTE = 0xF7,
251 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
252 EXECUTE_TO_SLEEP = 0xF5,
253 SLEEP_TO_EXECUTE = 0xF4,
254 SLEEP_TO_EXECUTEOK = 0xF3,
255 EXECUTE_TO_IDLE = 0xF2,
256 IDLE_TO_EXECUTE = 0xF1,
257 IDLE_TO_EXECUTEOK = 0xF0,
258 RDYTODS_RETURNTOEXE = 0xEF,
259 NORDYTODS_RETURNTOEXE = 0xEE,
260 EXETOSLEEP_RETURNTOEXE = 0xED,
261 EXETOIDLE_RETURNTOEXE = 0xEC,
262 INIT_STATUS = 0xEB,
263
264 /*error messages */
265 INITERROR = 0x00,
266 PLLARMLOCKP_ER = 0x01,
267 PLLDDRLOCKP_ER = 0x02,
268 PLLSOCLOCKP_ER = 0x03,
269 PLLSOCK1LOCKP_ER = 0x04,
270 ARMWFI_ER = 0x05,
271 SYSCLKOK_ER = 0x06,
272 I2C_NACK_DATA_ER = 0x07,
273 BOOT_ER = 0x08,
274 I2C_STATUS_ALWAYS_1 = 0x0A,
275 I2C_NACK_REG_ADDR_ER = 0x0B,
276 I2C_NACK_DATA0123_ER = 0x1B,
277 I2C_NACK_ADDR_ER = 0x1F,
278 CURAPPWRSTISNOT_BOOT = 0x20,
279 CURAPPWRSTISNOT_EXECUTE = 0x21,
280 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
281 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
282 FIFO4500WUISNOT_WUPEVENT = 0x24,
283 PLL32KLOCKP_ER = 0x29,
284 DDRDEEPSLEEPOK_ER = 0x2A,
285 ROMCODEREADY_ER = 0x50,
286 WUPBEFOREDS = 0x51,
287 DDRCONFIG_ER = 0x52,
288 WUPBEFORESLEEP = 0x53,
289 WUPBEFOREIDLE = 0x54
290}; /* earlier called as mbox_2_arm_stat */
291
292/**
293 * enum dvfs_stat - DVFS status messages definition
294 * @DVFS_GO: A state transition DVFS is on going
295 * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
296 * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
297 * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
298 * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
299 * NOCHGCLK
300 * @DVFS_INITSTATUS: Value init
301 */
302enum dvfs_stat {
303 DVFS_GO = 0xFF,
304 DVFS_ARM100OPPOK = 0xFE,
305 DVFS_ARM50OPPOK = 0xFD,
306 DVFS_ARMEXTCLKOK = 0xFC,
307 DVFS_NOCHGTCLKOK = 0xFB,
308 DVFS_INITSTATUS = 0x00
309};
310
311/**
312 * enum sva_mmdsp_stat - SVA MMDSP status messages
313 * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
314 * @SVA_MMDSP_INIT: Status init
315 */
316enum sva_mmdsp_stat {
317 SVA_MMDSP_GO = 0xFF,
318 SVA_MMDSP_INIT = 0x00
319};
320
321/**
322 * enum sia_mmdsp_stat - SIA MMDSP status messages
323 * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
324 * @SIA_MMDSP_INIT: Status init
325 */
326enum sia_mmdsp_stat {
327 SIA_MMDSP_GO = 0xFF,
328 SIA_MMDSP_INIT = 0x00
329};
330
331/**
332 * enum mbox_to_arm_err - Error messages definition
333 * @INIT_ERR: Init value
334 * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
335 * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
336 * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
337 * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
338 * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
339 * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
340 * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
341 * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
342 * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
343 * through I2C has not been correctly executed in the given time
344 * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
345 * through I2C has not been correctly executed in the given time
346 * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
347 * I2C has not been correctly executed in the given time
348 * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
349 * through I2C has not been correctly executed in the given time
350 * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
351 * I2C has not been correctly executed in the given time
352 * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
353 * through I2C has not been correctly executed in the given time
354 * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
355 * I2C has not been correctly executed in the given time
356 * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
357 * has not been correctly executed in the given time
358 * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
359 * not been correctly executed in the given time
360 * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
361 * not been correctly executed in the given time
362 * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
363 * I2C has not been correctly executed in the given time
364 * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
365 * I2C has not been correctly executed in the given time
366 * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
367 * through I2C has not been correctly executed in the given time
368 * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
369 * ApBoot to ApExecute but the power current state is not Apboot
370 * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
371 * transition from ApExecute to others power state but the
372 * power current state is not ApExecute
373 * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
374 * but the power current state is not ApDeepSleep/ApSleep/ApIdle
375 * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
376 * but the power current state is not correct
377 * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
378 * been correctly executed in the given time
379 * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
380 * been correctly executed in the given time
381 * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
382 * been correctly executed in the given time
383 * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
384 * been correctly executed in the given time
385 * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
386 * been correctly executed in the given time
387 */
388enum mbox_to_arm_err {
389 INIT_ERR = 0x00,
390 PLLARMLOCKP_ERR = 0x01,
391 PLLDDRLOCKP_ERR = 0x02,
392 PLLSOC0LOCKP_ERR = 0x03,
393 PLLSOC1LOCKP_ERR = 0x04,
394 ARMWFI_ERR = 0x05,
395 SYSCLKOK_ERR = 0x06,
396 BOOT_ERR = 0x07,
397 ROMCODESAVECONTEXT = 0x08,
398 VARMHIGHSPEEDVALTO_ERR = 0x10,
399 VARMHIGHSPEEDACCESS_ERR = 0x11,
400 VARMLOWSPEEDVALTO_ERR = 0x12,
401 VARMLOWSPEEDACCESS_ERR = 0x13,
402 VARMRETENTIONVALTO_ERR = 0x14,
403 VARMRETENTIONACCESS_ERR = 0x15,
404 VAPEHIGHSPEEDVALTO_ERR = 0x16,
405 VSAFEHPVALTO_ERR = 0x17,
406 VMODSEL1VALTO_ERR = 0x18,
407 VMODSEL2VALTO_ERR = 0x19,
408 VARMOFFACCESS_ERR = 0x1A,
409 VAPEOFFACCESS_ERR = 0x1B,
410 VARMRETACCES_ERR = 0x1C,
411 CURAPPWRSTISNOTBOOT = 0x20,
412 CURAPPWRSTISNOTEXECUTE = 0x21,
413 CURAPPWRSTISNOTSLEEPMODE = 0x22,
414 CURAPPWRSTISNOTCORRECTDBG = 0x23,
415 ARMREGU1VALTO_ERR = 0x24,
416 ARMREGU2VALTO_ERR = 0x25,
417 VAPEREGUVALTO_ERR = 0x26,
418 VSMPS3REGUVALTO_ERR = 0x27,
419 VMODREGUVALTO_ERR = 0x28
420};
421
422enum hw_acc {
423 SVAMMDSP = 0,
424 SVAPIPE = 1,
425 SIAMMDSP = 2,
426 SIAPIPE = 3,
427 SGA = 4,
428 B2R2MCDE = 5,
429 ESRAM12 = 6,
430 ESRAM34 = 7,
431};
432
433enum cs_pwrmgt {
434 PWRDNCS0 = 0,
435 WKUPCS0 = 1,
436 PWRDNCS1 = 2,
437 WKUPCS1 = 3
438};
439
440/* Defs related to autonomous power management */
441
442/**
443 * enum sia_sva_pwr_policy - Power policy
444 * @NO_CHGT: No change
445 * @DSPOFF_HWPOFF:
446 * @DSPOFFRAMRET_HWPOFF:
447 * @DSPCLKOFF_HWPOFF:
448 * @DSPCLKOFF_HWPCLKOFF:
449 *
450 */
451enum sia_sva_pwr_policy {
452 NO_CHGT = 0x0,
453 DSPOFF_HWPOFF = 0x1,
454 DSPOFFRAMRET_HWPOFF = 0x2,
455 DSPCLKOFF_HWPOFF = 0x3,
456 DSPCLKOFF_HWPCLKOFF = 0x4,
457};
458
459/**
460 * enum auto_enable - Auto Power enable
461 * @AUTO_OFF:
462 * @AUTO_ON:
463 *
464 */
465enum auto_enable {
466 AUTO_OFF = 0x0,
467 AUTO_ON = 0x1,
468};
469
470/* End of file previously known as prcmu-fw-defs_v1.h */
471
472/* PRCMU Wakeup defines */
473enum prcmu_wakeup_index {
474 PRCMU_WAKEUP_INDEX_RTC,
475 PRCMU_WAKEUP_INDEX_RTT0,
476 PRCMU_WAKEUP_INDEX_RTT1,
477 PRCMU_WAKEUP_INDEX_HSI0,
478 PRCMU_WAKEUP_INDEX_HSI1,
479 PRCMU_WAKEUP_INDEX_USB,
480 PRCMU_WAKEUP_INDEX_ABB,
481 PRCMU_WAKEUP_INDEX_ABB_FIFO,
482 PRCMU_WAKEUP_INDEX_ARM,
483 NUM_PRCMU_WAKEUP_INDICES
484};
485#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
486
487/* PRCMU QoS APE OPP class */
488#define PRCMU_QOS_APE_OPP 1
489#define PRCMU_QOS_DDR_OPP 2
490#define PRCMU_QOS_DEFAULT_VALUE -1
491
492/**
493 * enum hw_acc_dev - enum for hw accelerators
494 * @HW_ACC_SVAMMDSP: for SVAMMDSP
495 * @HW_ACC_SVAPIPE: for SVAPIPE
496 * @HW_ACC_SIAMMDSP: for SIAMMDSP
497 * @HW_ACC_SIAPIPE: for SIAPIPE
498 * @HW_ACC_SGA: for SGA
499 * @HW_ACC_B2R2: for B2R2
500 * @HW_ACC_MCDE: for MCDE
501 * @HW_ACC_ESRAM1: for ESRAM1
502 * @HW_ACC_ESRAM2: for ESRAM2
503 * @HW_ACC_ESRAM3: for ESRAM3
504 * @HW_ACC_ESRAM4: for ESRAM4
505 * @NUM_HW_ACC: number of hardware accelerators
506 *
507 * Different hw accelerators which can be turned ON/
508 * OFF or put into retention (MMDSPs and ESRAMs).
509 * Used with EPOD API.
510 *
511 * NOTE! Deprecated, to be removed when all users switched over to use the
512 * regulator API.
513 */
514enum hw_acc_dev {
515 HW_ACC_SVAMMDSP,
516 HW_ACC_SVAPIPE,
517 HW_ACC_SIAMMDSP,
518 HW_ACC_SIAPIPE,
519 HW_ACC_SGA,
520 HW_ACC_B2R2,
521 HW_ACC_MCDE,
522 HW_ACC_ESRAM1,
523 HW_ACC_ESRAM2,
524 HW_ACC_ESRAM3,
525 HW_ACC_ESRAM4,
526 NUM_HW_ACC
527};
528
529/*
530 * Ids for all EPODs (power domains)
531 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
532 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
533 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
534 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
535 * - EPOD_ID_SGA: power domain for SGA
536 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
537 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
538 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
539 * - NUM_EPOD_ID: number of power domains
540 */
541#define EPOD_ID_SVAMMDSP 0
542#define EPOD_ID_SVAPIPE 1
543#define EPOD_ID_SIAMMDSP 2
544#define EPOD_ID_SIAPIPE 3
545#define EPOD_ID_SGA 4
546#define EPOD_ID_B2R2_MCDE 5
547#define EPOD_ID_ESRAM12 6
548#define EPOD_ID_ESRAM34 7
549#define NUM_EPOD_ID 8
550
551/*
552 * state definition for EPOD (power domain)
553 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
554 * - EPOD_STATE_OFF: The EPOD is switched off
555 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
556 * retention
557 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
558 * - EPOD_STATE_ON: Same as above, but with clock enabled
559 */
560#define EPOD_STATE_NO_CHANGE 0x00
561#define EPOD_STATE_OFF 0x01
562#define EPOD_STATE_RAMRET 0x02
563#define EPOD_STATE_ON_CLK_OFF 0x03
564#define EPOD_STATE_ON 0x04
565
566/*
567 * CLKOUT sources
568 */
569#define PRCMU_CLKSRC_CLK38M 0x00
570#define PRCMU_CLKSRC_ACLK 0x01
571#define PRCMU_CLKSRC_SYSCLK 0x02
572#define PRCMU_CLKSRC_LCDCLK 0x03
573#define PRCMU_CLKSRC_SDMMCCLK 0x04
574#define PRCMU_CLKSRC_TVCLK 0x05
575#define PRCMU_CLKSRC_TIMCLK 0x06
576#define PRCMU_CLKSRC_CLK009 0x07
577/* These are only valid for CLKOUT1: */
578#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
579#define PRCMU_CLKSRC_I2CCLK 0x41
580#define PRCMU_CLKSRC_MSP02CLK 0x42
581#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
582#define PRCMU_CLKSRC_HSIRXCLK 0x44
583#define PRCMU_CLKSRC_HSITXCLK 0x45
584#define PRCMU_CLKSRC_ARMCLKFIX 0x46
585#define PRCMU_CLKSRC_HDMICLK 0x47
586
587/*
588 * Definitions for autonomous power management configuration.
589 */
590
591#define PRCMU_AUTO_PM_OFF 0
592#define PRCMU_AUTO_PM_ON 1
593
594#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
595#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
596
597enum prcmu_auto_pm_policy {
598 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
599 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
600 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
601 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
602 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
603};
604
605/**
606 * struct prcmu_auto_pm_config - Autonomous power management configuration.
607 * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
608 * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
609 * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
610 * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
611 * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
612 * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
613 */
614struct prcmu_auto_pm_config {
615 u8 sia_auto_pm_enable;
616 u8 sia_power_on;
617 u8 sia_policy;
618 u8 sva_auto_pm_enable;
619 u8 sva_power_on;
620 u8 sva_policy;
621};
622
623/**
624 * enum ddr_opp - DDR OPP states definition
625 * @DDR_100_OPP: The new DDR operating point is ddr100opp
626 * @DDR_50_OPP: The new DDR operating point is ddr50opp
627 * @DDR_25_OPP: The new DDR operating point is ddr25opp
628 */
629enum ddr_opp {
630 DDR_100_OPP = 0x00,
631 DDR_50_OPP = 0x01,
632 DDR_25_OPP = 0x02,
633};
634
635/*
636 * Clock identifiers.
637 */
638enum prcmu_clock {
639 PRCMU_SGACLK,
640 PRCMU_UARTCLK,
641 PRCMU_MSP02CLK,
642 PRCMU_MSP1CLK,
643 PRCMU_I2CCLK,
644 PRCMU_SDMMCCLK,
645 PRCMU_SLIMCLK,
646 PRCMU_PER1CLK,
647 PRCMU_PER2CLK,
648 PRCMU_PER3CLK,
649 PRCMU_PER5CLK,
650 PRCMU_PER6CLK,
651 PRCMU_PER7CLK,
652 PRCMU_LCDCLK,
653 PRCMU_BMLCLK,
654 PRCMU_HSITXCLK,
655 PRCMU_HSIRXCLK,
656 PRCMU_HDMICLK,
657 PRCMU_APEATCLK,
658 PRCMU_APETRACECLK,
659 PRCMU_MCDECLK,
660 PRCMU_IPI2CCLK,
661 PRCMU_DSIALTCLK,
662 PRCMU_DMACLK,
663 PRCMU_B2R2CLK,
664 PRCMU_TVCLK,
665 PRCMU_SSPCLK,
666 PRCMU_RNGCLK,
667 PRCMU_UICCCLK,
668 PRCMU_NUM_REG_CLOCKS,
669 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
670 PRCMU_TIMCLK,
671};
672
673/*
674 * Definitions for controlling ESRAM0 in deep sleep.
675 */
676#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
677#define ESRAM0_DEEP_SLEEP_STATE_RET 2
678
679#ifdef CONFIG_MFD_DB8500_PRCMU
680void __init prcmu_early_init(void);
681int prcmu_set_display_clocks(void);
682int prcmu_disable_dsipll(void);
683int prcmu_enable_dsipll(void);
684#else
685static inline void __init prcmu_early_init(void) {}
686#endif
687
688#ifdef CONFIG_MFD_DB8500_PRCMU
689
690int prcmu_set_rc_a2p(enum romcode_write);
691enum romcode_read prcmu_get_rc_p2a(void);
692enum ap_pwrst prcmu_get_xp70_current_state(void);
693int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
694
695void prcmu_enable_wakeups(u32 wakeups);
696static inline void prcmu_disable_wakeups(void)
697{
698 prcmu_enable_wakeups(0);
699}
700
701void prcmu_config_abb_event_readout(u32 abb_events);
702void prcmu_get_abb_event_buffer(void __iomem **buf);
703int prcmu_set_arm_opp(u8 opp);
704int prcmu_get_arm_opp(void);
705bool prcmu_has_arm_maxopp(void);
706bool prcmu_is_u8400(void);
707int prcmu_set_ape_opp(u8 opp);
708int prcmu_get_ape_opp(void);
709int prcmu_request_ape_opp_100_voltage(bool enable);
710int prcmu_release_usb_wakeup_state(void);
711int prcmu_set_ddr_opp(u8 opp);
712int prcmu_get_ddr_opp(void);
713unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
714void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
715/* NOTE! Use regulator framework instead */
716int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
717int prcmu_set_epod(u16 epod_id, u8 epod_state);
718void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
719 struct prcmu_auto_pm_config *idle);
720bool prcmu_is_auto_pm_enabled(void);
721
722int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
723int prcmu_request_clock(u8 clock, bool enable);
724int prcmu_set_clock_divider(u8 clock, u8 divider);
725int prcmu_config_esram0_deep_sleep(u8 state);
726int prcmu_config_hotdog(u8 threshold);
727int prcmu_config_hotmon(u8 low, u8 high);
728int prcmu_start_temp_sense(u16 cycles32k);
729int prcmu_stop_temp_sense(void);
730int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
731int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
732
733void prcmu_ac_wake_req(void);
734void prcmu_ac_sleep_req(void);
735void prcmu_system_reset(u16 reset_code);
736void prcmu_modem_reset(void);
737bool prcmu_is_ac_wake_requested(void);
738void prcmu_enable_spi2(void);
739void prcmu_disable_spi2(void);
740
741#else /* !CONFIG_MFD_DB8500_PRCMU */
742
743static inline int prcmu_set_rc_a2p(enum romcode_write code)
744{
745 return 0;
746}
747
748static inline enum romcode_read prcmu_get_rc_p2a(void)
749{
750 return INIT;
751}
752
753static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
754{
755 return AP_EXECUTE;
756}
757
758static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
759 bool keep_ap_pll)
760{
761 return 0;
762}
763
764static inline void prcmu_enable_wakeups(u32 wakeups) {}
765
766static inline void prcmu_disable_wakeups(void) {}
767
768static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
769
770static inline int prcmu_set_arm_opp(u8 opp)
771{
772 return 0;
773}
774
775static inline int prcmu_get_arm_opp(void)
776{
777 return ARM_100_OPP;
778}
779
780static bool prcmu_has_arm_maxopp(void)
781{
782 return false;
783}
784
785static bool prcmu_is_u8400(void)
786{
787 return false;
788}
789
790static inline int prcmu_set_ape_opp(u8 opp)
791{
792 return 0;
793}
794
795static inline int prcmu_get_ape_opp(void)
796{
797 return APE_100_OPP;
798}
799
800static inline int prcmu_request_ape_opp_100_voltage(bool enable)
801{
802 return 0;
803}
804
805static inline int prcmu_release_usb_wakeup_state(void)
806{
807 return 0;
808}
809
810static inline int prcmu_set_ddr_opp(u8 opp)
811{
812 return 0;
813}
814
815static inline int prcmu_get_ddr_opp(void)
816{
817 return DDR_100_OPP;
818}
819
820static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
821{
822 return 0;
823}
824
825static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
826
827static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
828{
829 return 0;
830}
831
832static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
833 struct prcmu_auto_pm_config *idle)
834{
835}
836
837static inline bool prcmu_is_auto_pm_enabled(void)
838{
839 return false;
840}
841
842static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
843{
844 return 0;
845}
846
847static inline int prcmu_request_clock(u8 clock, bool enable)
848{
849 return 0;
850}
851
852static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
853{
854 return 0;
855}
856
857int prcmu_config_esram0_deep_sleep(u8 state)
858{
859 return 0;
860}
861
862static inline int prcmu_config_hotdog(u8 threshold)
863{
864 return 0;
865}
866
867static inline int prcmu_config_hotmon(u8 low, u8 high)
868{
869 return 0;
870}
871
872static inline int prcmu_start_temp_sense(u16 cycles32k)
873{
874 return 0;
875}
876
877static inline int prcmu_stop_temp_sense(void)
878{
879 return 0;
880}
881
882static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
883{
884 return -ENOSYS;
885}
886
887static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
888{
889 return -ENOSYS;
890}
891
892static inline void prcmu_ac_wake_req(void) {}
893
894static inline void prcmu_ac_sleep_req(void) {}
895
896static inline void prcmu_system_reset(u16 reset_code) {}
897
898static inline void prcmu_modem_reset(void) {}
899
900static inline bool prcmu_is_ac_wake_requested(void)
901{
902 return false;
903}
904
905#ifndef CONFIG_UX500_SOC_DB5500
906static inline int prcmu_set_display_clocks(void)
907{
908 return 0;
909}
910
911static inline int prcmu_disable_dsipll(void)
912{
913 return 0;
914}
915
916static inline int prcmu_enable_dsipll(void)
917{
918 return 0;
919}
920#endif
921
922static inline int prcmu_enable_spi2(void)
923{
924 return 0;
925}
926
927static inline int prcmu_disable_spi2(void)
928{
929 return 0;
930}
931
932#endif /* !CONFIG_MFD_DB8500_PRCMU */
933
934#ifdef CONFIG_UX500_PRCMU_QOS_POWER
935int prcmu_qos_requirement(int pm_qos_class);
936int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
937int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
938void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
939int prcmu_qos_add_notifier(int prcmu_qos_class,
940 struct notifier_block *notifier);
941int prcmu_qos_remove_notifier(int prcmu_qos_class,
942 struct notifier_block *notifier);
943#else
944static inline int prcmu_qos_requirement(int prcmu_qos_class)
945{
946 return 0;
947}
948
949static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
950 char *name, s32 value)
951{
952 return 0;
953}
954
955static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
956 char *name, s32 new_value)
957{
958 return 0;
959}
960
961static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
962{
963}
964
965static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
966 struct notifier_block *notifier)
967{
968 return 0;
969}
970static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
971 struct notifier_block *notifier)
972{
973 return 0;
974}
975
976#endif
977
978#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/regulator/db8500-prcmu.h b/include/linux/regulator/db8500-prcmu.h
new file mode 100644
index 000000000000..612062313b68
--- /dev/null
+++ b/include/linux/regulator/db8500-prcmu.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
7 *
8 * Interface to power domain regulators on DB8500
9 */
10
11#ifndef __REGULATOR_H__
12#define __REGULATOR_H__
13
14/* Number of DB8500 regulators and regulator enumeration */
15enum db8500_regulator_id {
16 DB8500_REGULATOR_VAPE,
17 DB8500_REGULATOR_VARM,
18 DB8500_REGULATOR_VMODEM,
19 DB8500_REGULATOR_VPLL,
20 DB8500_REGULATOR_VSMPS1,
21 DB8500_REGULATOR_VSMPS2,
22 DB8500_REGULATOR_VSMPS3,
23 DB8500_REGULATOR_VRF1,
24 DB8500_REGULATOR_SWITCH_SVAMMDSP,
25 DB8500_REGULATOR_SWITCH_SVAMMDSPRET,
26 DB8500_REGULATOR_SWITCH_SVAPIPE,
27 DB8500_REGULATOR_SWITCH_SIAMMDSP,
28 DB8500_REGULATOR_SWITCH_SIAMMDSPRET,
29 DB8500_REGULATOR_SWITCH_SIAPIPE,
30 DB8500_REGULATOR_SWITCH_SGA,
31 DB8500_REGULATOR_SWITCH_B2R2_MCDE,
32 DB8500_REGULATOR_SWITCH_ESRAM12,
33 DB8500_REGULATOR_SWITCH_ESRAM12RET,
34 DB8500_REGULATOR_SWITCH_ESRAM34,
35 DB8500_REGULATOR_SWITCH_ESRAM34RET,
36 DB8500_NUM_REGULATORS
37};
38
39/*
40 * Exported interface for CPUIdle only. This function is called with all
41 * interrupts turned off.
42 */
43int power_state_active_is_enabled(void);
44
45#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-30 08:06:29 -0400