aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorOded Gabbay <oded.gabbay@gmail.com>2019-02-15 17:39:17 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-02-18 03:46:45 -0500
commit9494a8dd8d22cbff8ce358aaa223fffe1b070cb0 (patch)
tree8a7b51e6440aa5248026140fa33d42172dde26de /include
parent839c48030d27a690cc85f0762f9f6f07a3349fb3 (diff)
habanalabs: add h/w queues module
This patch adds the H/W queues module and the code to initialize Goya's various compute and DMA engines and their queues. Goya has 5 DMA channels, 8 TPC engines and a single MME engine. For each channel/engine, there is a H/W queue logic which is used to pass commands from the user to the H/W. That logic is called QMAN. There are two types of QMANs: external and internal. The DMA QMANs are considered external while the TPC and MME QMANs are considered internal. For each external queue there is a completion queue, which is located on the Host memory. The differences between external and internal QMANs are: 1. The location of the queue's memory. External QMANs are located on the Host memory while internal QMANs are located on the on-chip memory. 2. The external QMAN write an entry to a completion queue and sends an MSI-X interrupt upon completion of a command buffer that was given to it. The internal QMAN doesn't do that. Reviewed-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/misc/habanalabs.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h
index a8edfd3e9c95..756266cf0416 100644
--- a/include/uapi/misc/habanalabs.h
+++ b/include/uapi/misc/habanalabs.h
@@ -17,6 +17,35 @@
17 */ 17 */
18#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 18#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
19 19
20/*
21 * Queue Numbering
22 *
23 * The external queues (DMA channels + CPU) MUST be before the internal queues
24 * and each group (DMA channels + CPU and internal) must be contiguous inside
25 * itself but there can be a gap between the two groups (although not
26 * recommended)
27 */
28
29enum goya_queue_id {
30 GOYA_QUEUE_ID_DMA_0 = 0,
31 GOYA_QUEUE_ID_DMA_1,
32 GOYA_QUEUE_ID_DMA_2,
33 GOYA_QUEUE_ID_DMA_3,
34 GOYA_QUEUE_ID_DMA_4,
35 GOYA_QUEUE_ID_CPU_PQ,
36 GOYA_QUEUE_ID_MME,
37 GOYA_QUEUE_ID_TPC0,
38 GOYA_QUEUE_ID_TPC1,
39 GOYA_QUEUE_ID_TPC2,
40 GOYA_QUEUE_ID_TPC3,
41 GOYA_QUEUE_ID_TPC4,
42 GOYA_QUEUE_ID_TPC5,
43 GOYA_QUEUE_ID_TPC6,
44 GOYA_QUEUE_ID_TPC7,
45 GOYA_QUEUE_ID_SIZE
46};
47
48
20/* Opcode to create a new command buffer */ 49/* Opcode to create a new command buffer */
21#define HL_CB_OP_CREATE 0 50#define HL_CB_OP_CREATE 0
22/* Opcode to destroy previously created command buffer */ 51/* Opcode to destroy previously created command buffer */