Merge tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd

Pull MTD updates from Brian Norris:
 "First cycle with Boris as NAND maintainer! Many (most) bullets stolen
  from him.

  Generic:
   - Migrated NAND LED trigger to be a generic MTD trigger

  NAND:
   - Introduction of the "ECC algorithm" concept, to avoid overloading
     the ECC mode field too much more
   - Replaced the nand_ecclayout infrastructure with something a little
     more flexible (finally!) and future proof
   - Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some
     of this into their own tree as well
   - Prepare the sunxi NAND driver to receive DMA support
   - Handle bitflips in erased pages on GPMI revisions that do not
     support this in hardware.

  SPI NOR:
   - Start using the spi_flash_read() API for SPI drivers that support
     it (i.e., SPI drivers with special memory-mapped flash modes)

  And other small scattered improvments"

* tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd: (155 commits)
  mtd: spi-nor: support GigaDevice gd25lq64c
  mtd: nand_bch: fix spelling of "probably"
  mtd: brcmnand: respect ECC algorithm set by NAND subsystem
  gpmi-nand: Handle ECC Errors in erased pages
  Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
  mtd: nand: add support for "nand-ecc-algo" DT property
  mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
  mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
  mtd: nand: read ECC algorithm from the new field
  mtd: nand: fsmc: validate ECC setup by checking algorithm directly
  mtd: nand: set ECC algorithm to Hamming on fallback
  staging: mt29f_spinand: set ECC algorithm explicitly
  CRIS v32: nand: set ECC algorithm explicitly
  mtd: nand: atmel: set ECC algorithm explicitly
  mtd: nand: davinci: set ECC algorithm explicitly
  mtd: nand: bf5xx: set ECC algorithm explicitly
  mtd: nand: omap2: Fix high memory dma prefetch transfer
  mtd: nand: omap2: Start dma request before enabling prefetch
  mtd: nandsim: add __init attribute
  mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
  ...

14 files changed, 329 insertions, 258 deletions

diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 846513c73606..a5ac2cad5cb7 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -587,7 +587,6 @@ struct mtd_info;
 
 struct bcma_sflash {
         bool present;
-        u32 window;
         u32 blocksize;
         u16 numblocks;
         u32 size;
diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 0023088b253b..3f9778cbc79d 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -39,6 +39,10 @@
 #define FSL_IFC_VERSION_MASK    0x0F0F0000
 #define FSL_IFC_VERSION_1_0_0   0x01000000
 #define FSL_IFC_VERSION_1_1_0   0x01010000
+#define FSL_IFC_VERSION_2_0_0   0x02000000
+
+#define PGOFFSET_64K    (64*1024)
+#define PGOFFSET_4K     (4*1024)
 
 /*
  * CSPR - Chip Select Property Register
@@ -723,20 +727,26 @@ struct fsl_ifc_nand {
         __be32 nand_evter_en;
         u32 res17[0x2];
         __be32 nand_evter_intr_en;
-        u32 res18[0x2];
+        __be32 nand_vol_addr_stat;
+        u32 res18;
         __be32 nand_erattr0;
         __be32 nand_erattr1;
         u32 res19[0x10];
         __be32 nand_fsr;
-        u32 res20;
-        __be32 nand_eccstat[4];
-        u32 res21[0x20];
+        u32 res20[0x3];
+        __be32 nand_eccstat[6];
+        u32 res21[0x1c];
         __be32 nanndcr;
         u32 res22[0x2];
         __be32 nand_autoboot_trgr;
         u32 res23;
         __be32 nand_mdr;
-        u32 res24[0x5C];
+        u32 res24[0x1C];
+        __be32 nand_dll_lowcfg0;
+        __be32 nand_dll_lowcfg1;
+        u32 res25;
+        __be32 nand_dll_lowstat;
+        u32 res26[0x3c];
 };
 
 /*
@@ -771,13 +781,12 @@ struct fsl_ifc_gpcm {
         __be32 gpcm_erattr1;
         __be32 gpcm_erattr2;
         __be32 gpcm_stat;
-        u32 res4[0x1F3];
 };
 
 /*
  * IFC Controller Registers
  */
-struct fsl_ifc_regs {
+struct fsl_ifc_global {
         __be32 ifc_rev;
         u32 res1[0x2];
         struct {
@@ -803,21 +812,26 @@ struct fsl_ifc_regs {
         } ftim_cs[FSL_IFC_BANK_COUNT];
         u32 res9[0x30];
         __be32 rb_stat;
-        u32 res10[0x2];
+        __be32 rb_map;
+        __be32 wb_map;
         __be32 ifc_gcr;
-        u32 res11[0x2];
+        u32 res10[0x2];
         __be32 cm_evter_stat;
-        u32 res12[0x2];
+        u32 res11[0x2];
         __be32 cm_evter_en;
-        u32 res13[0x2];
+        u32 res12[0x2];
         __be32 cm_evter_intr_en;
-        u32 res14[0x2];
+        u32 res13[0x2];
         __be32 cm_erattr0;
         __be32 cm_erattr1;
-        u32 res15[0x2];
+        u32 res14[0x2];
         __be32 ifc_ccr;
         __be32 ifc_csr;
-        u32 res16[0x2EB];
+        __be32 ddr_ccr_low;
+};
+
+
+struct fsl_ifc_runtime {
         struct fsl_ifc_nand ifc_nand;
         struct fsl_ifc_nor ifc_nor;
         struct fsl_ifc_gpcm ifc_gpcm;
@@ -831,7 +845,8 @@ extern int fsl_ifc_find(phys_addr_t addr_base);
 struct fsl_ifc_ctrl {
         /* device info */
         struct device                   *dev;
-        struct fsl_ifc_regs __iomem     *regs;
+        struct fsl_ifc_global __iomem   *gregs;
+        struct fsl_ifc_runtime __iomem  *rregs;
         int                             irq;
         int                             nand_irq;
         spinlock_t                      lock;
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index c8be32e9fc49..ad3c3488073c 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -103,24 +103,6 @@
 
 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 
-/*
- * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
- * and it has to be read consecutively and immediately after the 512
- * byte data block for hardware to generate the error bit offsets
- * Managing the ecc bytes in the following way is easier. This way is
- * similar to oobfree structure maintained already in u-boot nand driver
- */
-#define MAX_ECCPLACE_ENTRIES    32
-
-struct fsmc_nand_eccplace {
-        uint8_t offset;
-        uint8_t length;
-};
-
-struct fsmc_eccplace {
-        struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
-};
-
 struct fsmc_nand_timings {
         uint8_t tclr;
         uint8_t tar;
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 5e0eb7ccabd4..3aa56e3104bb 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -122,18 +122,13 @@
 #endif
 
 #ifdef CONFIG_MTD_MAP_BANK_WIDTH_32
-# ifdef map_bankwidth
-#  undef map_bankwidth
-#  define map_bankwidth(map) ((map)->bankwidth)
-#  undef map_bankwidth_is_large
-#  define map_bankwidth_is_large(map) (map_bankwidth(map) > BITS_PER_LONG/8)
-#  undef map_words
-#  define map_words(map) map_calc_words(map)
-# else
-#  define map_bankwidth(map) 32
-#  define map_bankwidth_is_large(map) (1)
-#  define map_words(map) map_calc_words(map)
-# endif
+/* always use indirect access for 256-bit to preserve kernel stack */
+# undef map_bankwidth
+# define map_bankwidth(map) ((map)->bankwidth)
+# undef map_bankwidth_is_large
+# define map_bankwidth_is_large(map) (map_bankwidth(map) > BITS_PER_LONG/8)
+# undef map_words
+# define map_words(map) map_calc_words(map)
 #define map_bankwidth_is_32(map) (map_bankwidth(map) == 32)
 #undef MAX_MAP_BANKWIDTH
 #define MAX_MAP_BANKWIDTH 32
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index ef9fea4fc400..29a170612203 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -96,16 +96,35 @@ struct mtd_oob_ops {
 
 #define MTD_MAX_OOBFREE_ENTRIES_LARGE   32
 #define MTD_MAX_ECCPOS_ENTRIES_LARGE    640
+/**
+ * struct mtd_oob_region - oob region definition
+ * @offset: region offset
+ * @length: region length
+ *
+ * This structure describes a region of the OOB area, and is used
+ * to retrieve ECC or free bytes sections.
+ * Each section is defined by an offset within the OOB area and a
+ * length.
+ */
+struct mtd_oob_region {
+        u32 offset;
+        u32 length;
+};
+
 /*
- * Internal ECC layout control structure. For historical reasons, there is a
- * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained
- * for export to user-space via the ECCGETLAYOUT ioctl.
- * nand_ecclayout should be expandable in the future simply by the above macros.
+ * struct mtd_ooblayout_ops - NAND OOB layout operations
+ * @ecc: function returning an ECC region in the OOB area.
+ *       Should return -ERANGE if %section exceeds the total number of
+ *       ECC sections.
+ * @free: function returning a free region in the OOB area.
+ *        Should return -ERANGE if %section exceeds the total number of
+ *        free sections.
  */
-struct nand_ecclayout {
-        __u32 eccbytes;
-        __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
-        struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+struct mtd_ooblayout_ops {
+        int (*ecc)(struct mtd_info *mtd, int section,
+                   struct mtd_oob_region *oobecc);
+        int (*free)(struct mtd_info *mtd, int section,
+                    struct mtd_oob_region *oobfree);
 };
 
 struct module;  /* only needed for owner field in mtd_info */
@@ -166,8 +185,8 @@ struct mtd_info {
         const char *name;
         int index;
 
-        /* ECC layout structure pointer - read only! */
-        struct nand_ecclayout *ecclayout;
+        /* OOB layout description */
+        const struct mtd_ooblayout_ops *ooblayout;
 
         /* the ecc step size. */
         unsigned int ecc_step_size;
@@ -253,6 +272,30 @@ struct mtd_info {
         int usecount;
 };
 
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+                      struct mtd_oob_region *oobecc);
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+                                 int *section,
+                                 struct mtd_oob_region *oobregion);
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+                               const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+                               u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+                       struct mtd_oob_region *oobfree);
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+                                const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+                                u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd);
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd);
+
+static inline void mtd_set_ooblayout(struct mtd_info *mtd,
+                                     const struct mtd_ooblayout_ops *ooblayout)
+{
+        mtd->ooblayout = ooblayout;
+}
+
 static inline void mtd_set_of_node(struct mtd_info *mtd,
                                    struct device_node *np)
 {
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 56574ba36555..fbe8e164a4ee 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -116,9 +116,14 @@ typedef enum {
         NAND_ECC_HW,
         NAND_ECC_HW_SYNDROME,
         NAND_ECC_HW_OOB_FIRST,
-        NAND_ECC_SOFT_BCH,
 } nand_ecc_modes_t;
 
+enum nand_ecc_algo {
+        NAND_ECC_UNKNOWN,
+        NAND_ECC_HAMMING,
+        NAND_ECC_BCH,
+};
+
 /*
  * Constants for Hardware ECC
  */
@@ -458,6 +463,7 @@ struct nand_hw_control {
 /**
  * struct nand_ecc_ctrl - Control structure for ECC
  * @mode:       ECC mode
+ * @algo:       ECC algorithm
  * @steps:      number of ECC steps per page
  * @size:       data bytes per ECC step
  * @bytes:      ECC bytes per step
@@ -466,7 +472,6 @@ struct nand_hw_control {
  * @prepad:     padding information for syndrome based ECC generators
  * @postpad:    padding information for syndrome based ECC generators
  * @options:    ECC specific options (see NAND_ECC_XXX flags defined above)
- * @layout:     ECC layout control struct pointer
  * @priv:       pointer to private ECC control data
  * @hwctl:      function to control hardware ECC generator. Must only
  *              be provided if an hardware ECC is available
@@ -508,6 +513,7 @@ struct nand_hw_control {
  */
 struct nand_ecc_ctrl {
         nand_ecc_modes_t mode;
+        enum nand_ecc_algo algo;
         int steps;
         int size;
         int bytes;
@@ -516,7 +522,6 @@ struct nand_ecc_ctrl {
         int prepad;
         int postpad;
         unsigned int options;
-        struct nand_ecclayout   *layout;
         void *priv;
         void (*hwctl)(struct mtd_info *mtd, int mode);
         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
@@ -740,6 +745,9 @@ struct nand_chip {
         void *priv;
 };
 
+extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
+extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
+
 static inline void nand_set_flash_node(struct nand_chip *chip,
                                        struct device_node *np)
 {
@@ -1070,4 +1078,18 @@ int nand_check_erased_ecc_chunk(void *data, int datalen,
                                 void *ecc, int ecclen,
                                 void *extraoob, int extraooblen,
                                 int threshold);
+
+/* Default write_oob implementation */
+int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
+
+/* Default write_oob syndrome implementation */
+int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+                            int page);
+
+/* Default read_oob implementation */
+int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
+
+/* Default read_oob syndrome implementation */
+int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+                           int page);
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 4596503c9da9..0aaa98b219a4 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -80,7 +80,6 @@ struct onenand_bufferram {
  * @page_buf:           [INTERN] page main data buffer
  * @oob_buf:            [INTERN] page oob data buffer
  * @subpagesize:        [INTERN] holds the subpagesize
- * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
  * @bbm:                [REPLACEABLE] pointer to Bad Block Management
  * @priv:               [OPTIONAL] pointer to private chip date
  */
@@ -134,7 +133,6 @@ struct onenand_chip {
 #endif
 
         int                     subpagesize;
-        struct nand_ecclayout   *ecclayout;
 
         void                    *bbm;
 
diff --git a/include/linux/mtd/sharpsl.h b/include/linux/mtd/sharpsl.h
index 25f4d2a845c1..65e91d0fa981 100644
--- a/include/linux/mtd/sharpsl.h
+++ b/include/linux/mtd/sharpsl.h
@@ -14,7 +14,7 @@
 
 struct sharpsl_nand_platform_data {
         struct nand_bbt_descr   *badblock_pattern;
-        struct nand_ecclayout   *ecc_layout;
+        const struct mtd_ooblayout_ops *ecc_layout;
         struct mtd_partition    *partitions;
         unsigned int            nr_partitions;
 };
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 3c36113a88e1..7f041bd88b82 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -21,6 +21,7 @@
  * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  */
 #define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
+#define SNOR_MFR_GIGADEVICE     0xc8
 #define SNOR_MFR_INTEL          CFI_MFR_INTEL
 #define SNOR_MFR_MICRON         CFI_MFR_ST /* ST Micro <--> Micron */
 #define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h
deleted file mode 100644
index e266caa36402..000000000000
--- a/include/linux/of_mtd.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * OF helpers for mtd.
- *
- * This file is released under the GPLv2
- */
-
-#ifndef __LINUX_OF_MTD_H
-#define __LINUX_OF_MTD_H
-
-#ifdef CONFIG_OF_MTD
-
-#include <linux/of.h>
-int of_get_nand_ecc_mode(struct device_node *np);
-int of_get_nand_ecc_step_size(struct device_node *np);
-int of_get_nand_ecc_strength(struct device_node *np);
-int of_get_nand_bus_width(struct device_node *np);
-bool of_get_nand_on_flash_bbt(struct device_node *np);
-
-#else /* CONFIG_OF_MTD */
-
-static inline int of_get_nand_ecc_mode(struct device_node *np)
-{
-        return -ENOSYS;
-}
-
-static inline int of_get_nand_ecc_step_size(struct device_node *np)
-{
-        return -ENOSYS;
-}
-
-static inline int of_get_nand_ecc_strength(struct device_node *np)
-{
-        return -ENOSYS;
-}
-
-static inline int of_get_nand_bus_width(struct device_node *np)
-{
-        return -ENOSYS;
-}
-
-static inline bool of_get_nand_on_flash_bbt(struct device_node *np)
-{
-        return false;
-}
-
-#endif /* CONFIG_OF_MTD */
-
-#endif /* __LINUX_OF_MTD_H */
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index d833eb4dd446..9e9d79e8efa5 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -7,161 +7,53 @@
  *  option) any later version.
  */
 
-/* Maximum Number of Chip Selects */
-#define GPMC_CS_NUM             8
+#include <linux/platform_data/gpmc-omap.h>
 
 #define GPMC_CONFIG_WP          0x00000005
 
-#define GPMC_IRQ_FIFOEVENTENABLE        0x01
-#define GPMC_IRQ_COUNT_EVENT            0x02
-
-#define GPMC_BURST_4                    4       /* 4 word burst */
-#define GPMC_BURST_8                    8       /* 8 word burst */
-#define GPMC_BURST_16                   16      /* 16 word burst */
-#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
-#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
-#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
-#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
-
-/* bool type time settings */
-struct gpmc_bool_timings {
-        bool cycle2cyclediffcsen;
-        bool cycle2cyclesamecsen;
-        bool we_extra_delay;
-        bool oe_extra_delay;
-        bool adv_extra_delay;
-        bool cs_extra_delay;
-        bool time_para_granularity;
-};
+/* IRQ numbers in GPMC IRQ domain for legacy boot use */
+#define GPMC_IRQ_FIFOEVENTENABLE        0
+#define GPMC_IRQ_COUNT_EVENT            1
 
-/*
- * Note that all values in this struct are in nanoseconds except sync_clk
- * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+/**
+ * gpmc_nand_ops - Interface between NAND and GPMC
+ * @nand_write_buffer_empty: get the NAND write buffer empty status.
  */
-struct gpmc_timings {
-        /* Minimum clock period for synchronous mode (in picoseconds) */
-        u32 sync_clk;
-
-        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
-        u32 cs_on;              /* Assertion time */
-        u32 cs_rd_off;          /* Read deassertion time */
-        u32 cs_wr_off;          /* Write deassertion time */
-
-        /* ADV signal timings corresponding to GPMC_CONFIG3 */
-        u32 adv_on;             /* Assertion time */
-        u32 adv_rd_off;         /* Read deassertion time */
-        u32 adv_wr_off;         /* Write deassertion time */
-        u32 adv_aad_mux_on;     /* ADV assertion time for AAD */
-        u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
-        u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
-
-        /* WE signals timings corresponding to GPMC_CONFIG4 */
-        u32 we_on;              /* WE assertion time */
-        u32 we_off;             /* WE deassertion time */
-
-        /* OE signals timings corresponding to GPMC_CONFIG4 */
-        u32 oe_on;              /* OE assertion time */
-        u32 oe_off;             /* OE deassertion time */
-        u32 oe_aad_mux_on;      /* OE assertion time for AAD */
-        u32 oe_aad_mux_off;     /* OE deassertion time for AAD */
-
-        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
-        u32 page_burst_access;  /* Multiple access word delay */
-        u32 access;             /* Start-cycle to first data valid delay */
-        u32 rd_cycle;           /* Total read cycle time */
-        u32 wr_cycle;           /* Total write cycle time */
-
-        u32 bus_turnaround;
-        u32 cycle2cycle_delay;
-
-        u32 wait_monitoring;
-        u32 clk_activation;
-
-        /* The following are only on OMAP3430 */
-        u32 wr_access;          /* WRACCESSTIME */
-        u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
-
-        struct gpmc_bool_timings bool_timings;
+struct gpmc_nand_ops {
+        bool (*nand_writebuffer_empty)(void);
 };
 
-/* Device timings in picoseconds */
-struct gpmc_device_timings {
-        u32 t_ceasu;    /* address setup to CS valid */
-        u32 t_avdasu;   /* address setup to ADV valid */
-        /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
-         * of tusb using these timings even for sync whilst
-         * ideally for adv_rd/(wr)_off it should have considered
-         * t_avdh instead. This indirectly necessitates r/w
-         * variations of t_avdp as it is possible to have one
-         * sync & other async
-         */
-        u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
-        u32 t_avdp_w;
-        u32 t_aavdh;    /* address hold time */
-        u32 t_oeasu;    /* address setup to OE valid */
-        u32 t_aa;       /* access time from ADV assertion */
-        u32 t_iaa;      /* initial access time */
-        u32 t_oe;       /* access time from OE assertion */
-        u32 t_ce;       /* access time from CS asertion */
-        u32 t_rd_cycle; /* read cycle time */
-        u32 t_cez_r;    /* read CS deassertion to high Z */
-        u32 t_cez_w;    /* write CS deassertion to high Z */
-        u32 t_oez;      /* OE deassertion to high Z */
-        u32 t_weasu;    /* address setup to WE valid */
-        u32 t_wpl;      /* write assertion time */
-        u32 t_wph;      /* write deassertion time */
-        u32 t_wr_cycle; /* write cycle time */
-
-        u32 clk;
-        u32 t_bacc;     /* burst access valid clock to output delay */
-        u32 t_ces;      /* CS setup time to clk */
-        u32 t_avds;     /* ADV setup time to clk */
-        u32 t_avdh;     /* ADV hold time from clk */
-        u32 t_ach;      /* address hold time from clk */
-        u32 t_rdyo;     /* clk to ready valid */
-
-        u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
-        u32 t_ce_avd;   /* CS on to ADV on delay */
-
-        /* XXX: check the possibility of combining
-         * cyc_aavhd_oe & cyc_aavdh_we
-         */
-        u8 cyc_aavdh_oe;/* read address hold time in cycles */
-        u8 cyc_aavdh_we;/* write address hold time in cycles */
-        u8 cyc_oe;      /* access time from OE assertion in cycles */
-        u8 cyc_wpl;     /* write deassertion time in cycles */
-        u32 cyc_iaa;    /* initial access time in cycles */
-
-        /* extra delays */
-        bool ce_xdelay;
-        bool avd_xdelay;
-        bool oe_xdelay;
-        bool we_xdelay;
-};
+struct gpmc_nand_regs;
 
-struct gpmc_settings {
-        bool burst_wrap;        /* enables wrap bursting */
-        bool burst_read;        /* enables read page/burst mode */
-        bool burst_write;       /* enables write page/burst mode */
-        bool device_nand;       /* device is NAND */
-        bool sync_read;         /* enables synchronous reads */
-        bool sync_write;        /* enables synchronous writes */
-        bool wait_on_read;      /* monitor wait on reads */
-        bool wait_on_write;     /* monitor wait on writes */
-        u32 burst_len;          /* page/burst length */
-        u32 device_width;       /* device bus width (8 or 16 bit) */
-        u32 mux_add_data;       /* multiplex address & data */
-        u32 wait_pin;           /* wait-pin to be used */
-};
+#if IS_ENABLED(CONFIG_OMAP_GPMC)
+struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
+                                             int cs);
+#else
+static inline gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
+                                                    int cs)
+{
+        return NULL;
+}
+#endif /* CONFIG_OMAP_GPMC */
+
+/*--------------------------------*/
+
+/* deprecated APIs */
+#if IS_ENABLED(CONFIG_OMAP_GPMC)
+void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+#else
+static inline void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+{
+}
+#endif /* CONFIG_OMAP_GPMC */
+/*--------------------------------*/
 
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
                              struct gpmc_settings *gpmc_s,
                              struct gpmc_device_timings *dev_t);
 
-struct gpmc_nand_regs;
 struct device_node;
 
-extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h
new file mode 100644
index 000000000000..67ccdb0e1606
--- /dev/null
+++ b/include/linux/platform_data/gpmc-omap.h
@@ -0,0 +1,172 @@
+/*
+ * OMAP GPMC Platform data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc. - http://www.ti.com
+ *      Roger Quadros <rogerq@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _GPMC_OMAP_H_
+#define _GPMC_OMAP_H_
+
+/* Maximum Number of Chip Selects */
+#define GPMC_CS_NUM             8
+
+/* bool type time settings */
+struct gpmc_bool_timings {
+        bool cycle2cyclediffcsen;
+        bool cycle2cyclesamecsen;
+        bool we_extra_delay;
+        bool oe_extra_delay;
+        bool adv_extra_delay;
+        bool cs_extra_delay;
+        bool time_para_granularity;
+};
+
+/*
+ * Note that all values in this struct are in nanoseconds except sync_clk
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+ */
+struct gpmc_timings {
+        /* Minimum clock period for synchronous mode (in picoseconds) */
+        u32 sync_clk;
+
+        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
+        u32 cs_on;              /* Assertion time */
+        u32 cs_rd_off;          /* Read deassertion time */
+        u32 cs_wr_off;          /* Write deassertion time */
+
+        /* ADV signal timings corresponding to GPMC_CONFIG3 */
+        u32 adv_on;             /* Assertion time */
+        u32 adv_rd_off;         /* Read deassertion time */
+        u32 adv_wr_off;         /* Write deassertion time */
+        u32 adv_aad_mux_on;     /* ADV assertion time for AAD */
+        u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
+        u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
+
+        /* WE signals timings corresponding to GPMC_CONFIG4 */
+        u32 we_on;              /* WE assertion time */
+        u32 we_off;             /* WE deassertion time */
+
+        /* OE signals timings corresponding to GPMC_CONFIG4 */
+        u32 oe_on;              /* OE assertion time */
+        u32 oe_off;             /* OE deassertion time */
+        u32 oe_aad_mux_on;      /* OE assertion time for AAD */
+        u32 oe_aad_mux_off;     /* OE deassertion time for AAD */
+
+        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
+        u32 page_burst_access;  /* Multiple access word delay */
+        u32 access;             /* Start-cycle to first data valid delay */
+        u32 rd_cycle;           /* Total read cycle time */
+        u32 wr_cycle;           /* Total write cycle time */
+
+        u32 bus_turnaround;
+        u32 cycle2cycle_delay;
+
+        u32 wait_monitoring;
+        u32 clk_activation;
+
+        /* The following are only on OMAP3430 */
+        u32 wr_access;          /* WRACCESSTIME */
+        u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
+
+        struct gpmc_bool_timings bool_timings;
+};
+
+/* Device timings in picoseconds */
+struct gpmc_device_timings {
+        u32 t_ceasu;    /* address setup to CS valid */
+        u32 t_avdasu;   /* address setup to ADV valid */
+        /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
+         * of tusb using these timings even for sync whilst
+         * ideally for adv_rd/(wr)_off it should have considered
+         * t_avdh instead. This indirectly necessitates r/w
+         * variations of t_avdp as it is possible to have one
+         * sync & other async
+         */
+        u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
+        u32 t_avdp_w;
+        u32 t_aavdh;    /* address hold time */
+        u32 t_oeasu;    /* address setup to OE valid */
+        u32 t_aa;       /* access time from ADV assertion */
+        u32 t_iaa;      /* initial access time */
+        u32 t_oe;       /* access time from OE assertion */
+        u32 t_ce;       /* access time from CS asertion */
+        u32 t_rd_cycle; /* read cycle time */
+        u32 t_cez_r;    /* read CS deassertion to high Z */
+        u32 t_cez_w;    /* write CS deassertion to high Z */
+        u32 t_oez;      /* OE deassertion to high Z */
+        u32 t_weasu;    /* address setup to WE valid */
+        u32 t_wpl;      /* write assertion time */
+        u32 t_wph;      /* write deassertion time */
+        u32 t_wr_cycle; /* write cycle time */
+
+        u32 clk;
+        u32 t_bacc;     /* burst access valid clock to output delay */
+        u32 t_ces;      /* CS setup time to clk */
+        u32 t_avds;     /* ADV setup time to clk */
+        u32 t_avdh;     /* ADV hold time from clk */
+        u32 t_ach;      /* address hold time from clk */
+        u32 t_rdyo;     /* clk to ready valid */
+
+        u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
+        u32 t_ce_avd;   /* CS on to ADV on delay */
+
+        /* XXX: check the possibility of combining
+         * cyc_aavhd_oe & cyc_aavdh_we
+         */
+        u8 cyc_aavdh_oe;/* read address hold time in cycles */
+        u8 cyc_aavdh_we;/* write address hold time in cycles */
+        u8 cyc_oe;      /* access time from OE assertion in cycles */
+        u8 cyc_wpl;     /* write deassertion time in cycles */
+        u32 cyc_iaa;    /* initial access time in cycles */
+
+        /* extra delays */
+        bool ce_xdelay;
+        bool avd_xdelay;
+        bool oe_xdelay;
+        bool we_xdelay;
+};
+
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
+
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
+/* Data for each chip select */
+struct gpmc_omap_cs_data {
+        bool valid;                     /* data is valid */
+        bool is_nand;                   /* device within this CS is NAND */
+        struct gpmc_settings *settings;
+        struct gpmc_device_timings *device_timings;
+        struct gpmc_timings *gpmc_timings;
+        struct platform_device *pdev;   /* device within this CS region */
+        unsigned int pdata_size;
+};
+
+struct gpmc_omap_platform_data {
+        struct gpmc_omap_cs_data cs[GPMC_CS_NUM];
+};
+
+#endif /* _GPMC_OMAP_H */
diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h
index 090bbab0130a..17d57a18bac5 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -45,7 +45,6 @@ enum omap_ecc {
 };
 
 struct gpmc_nand_regs {
-        void __iomem    *gpmc_status;
         void __iomem    *gpmc_nand_command;
         void __iomem    *gpmc_nand_address;
         void __iomem    *gpmc_nand_data;
@@ -64,21 +63,24 @@ struct gpmc_nand_regs {
         void __iomem    *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
         void __iomem    *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
         void __iomem    *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
+        /* Deprecated. Do not use */
+        void __iomem    *gpmc_status;
 };
 
 struct omap_nand_platform_data {
         int                     cs;
         struct mtd_partition    *parts;
         int                     nr_parts;
-        bool                    dev_ready;
         bool                    flash_bbt;
         enum nand_io            xfer_type;
         int                     devsize;
         enum omap_ecc           ecc_opt;
-        struct gpmc_nand_regs   reg;
 
-        /* for passing the partitions */
-        struct device_node      *of_node;
         struct device_node      *elm_of_node;
+
+        /* deprecated */
+        struct gpmc_nand_regs   reg;
+        struct device_node      *of_node;
+        bool                    dev_ready;
 };
 #endif
diff --git a/include/uapi/mtd/mtd-abi.h b/include/uapi/mtd/mtd-abi.h
index 763bb6950402..0ec1da2ef652 100644
--- a/include/uapi/mtd/mtd-abi.h
+++ b/include/uapi/mtd/mtd-abi.h
@@ -228,7 +228,7 @@ struct nand_oobfree {
  * complete set of ECC information. The ioctl truncates the larger internal
  * structure to retain binary compatibility with the static declaration of the
  * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of
- * the user struct, not the MAX size of the internal struct nand_ecclayout.
+ * the user struct, not the MAX size of the internal OOB layout representation.
  */
 struct nand_ecclayout_user {
         __u32 eccbytes;