Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:

 - Improvements to the tlb_dump code
 - KVM fixes
 - Add support for appended DTB
 - Minor improvements to the R12000 support
 - Minor improvements to the R12000 support
 - Various platform improvments for BCM47xx
 - The usual pile of minor cleanups
 - A number of BPF fixes and improvments
 - Some improvments to the support for R3000 and DECstations
 - Some improvments to the ATH79 platform support
 - A major patchset for the JZ4740 SOC adding support for the CI20 platform
 - Add support for the Pistachio SOC
 - Minor BMIPS/BCM63xx platform support improvments.
 - Avoid "SYNC 0" as memory barrier when unlocking spinlocks
 - Add support for the XWR-1750 board.
 - Paul's __cpuinit/__cpuinitdata cleanups.
 - New Malta CPU board support large memory so enable ZONE_DMA32.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
  MIPS: spinlock: Adjust arch_spin_lock back-off time
  MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
  MIPS: BCM47xx: Simplify handling SPROM revisions
  MIPS: Cobalt Don't use module_init in non-modular MTD registration.
  MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
  MIPS: use for_each_sg()
  MIPS: BCM47xx: Don't select BCMA_HOST_PCI
  MIPS: BCM47xx: Add helper variable for storing NVRAM length
  MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
  MIPS: Replace smp_mb with release barrier function in unlocks.
  MIPS: i8259: DT support
  MIPS: Malta: Basic DT plumbing
  MIPS: include errno.h for ENODEV in mips-cm.h
  MIPS: Define GCR_GIC_STATUS register fields
  MIPS: BPF: Introduce BPF ASM helpers
  MIPS: BPF: Use BPF register names to describe the ABI
  MIPS: BPF: Move register definition to the BPF header
  MIPS: net: BPF: Replace RSIZE with SZREG
  MIPS: BPF: Free up some callee-saved registers
  MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
  ...

7 files changed, 206 insertions, 2 deletions

diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h
new file mode 100644
index 000000000000..43153d3e9bd2
--- /dev/null
+++ b/include/dt-bindings/clock/jz4740-cgu.h
@@ -0,0 +1,37 @@
+/*
+ * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4740 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+
+#define JZ4740_CLK_EXT          0
+#define JZ4740_CLK_RTC          1
+#define JZ4740_CLK_PLL          2
+#define JZ4740_CLK_PLL_HALF     3
+#define JZ4740_CLK_CCLK         4
+#define JZ4740_CLK_HCLK         5
+#define JZ4740_CLK_PCLK         6
+#define JZ4740_CLK_MCLK         7
+#define JZ4740_CLK_LCD          8
+#define JZ4740_CLK_LCD_PCLK     9
+#define JZ4740_CLK_I2S          10
+#define JZ4740_CLK_SPI          11
+#define JZ4740_CLK_MMC          12
+#define JZ4740_CLK_UHC          13
+#define JZ4740_CLK_UDC          14
+#define JZ4740_CLK_UART0        15
+#define JZ4740_CLK_UART1        16
+#define JZ4740_CLK_DMA          17
+#define JZ4740_CLK_IPU          18
+#define JZ4740_CLK_ADC          19
+#define JZ4740_CLK_I2C          20
+#define JZ4740_CLK_AIC          21
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
new file mode 100644
index 000000000000..467165e3cfee
--- /dev/null
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -0,0 +1,88 @@
+/*
+ * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4780 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+
+#define JZ4780_CLK_EXCLK        0
+#define JZ4780_CLK_RTCLK        1
+#define JZ4780_CLK_APLL         2
+#define JZ4780_CLK_MPLL         3
+#define JZ4780_CLK_EPLL         4
+#define JZ4780_CLK_VPLL         5
+#define JZ4780_CLK_OTGPHY       6
+#define JZ4780_CLK_SCLKA        7
+#define JZ4780_CLK_CPUMUX       8
+#define JZ4780_CLK_CPU          9
+#define JZ4780_CLK_L2CACHE      10
+#define JZ4780_CLK_AHB0         11
+#define JZ4780_CLK_AHB2PMUX     12
+#define JZ4780_CLK_AHB2         13
+#define JZ4780_CLK_PCLK         14
+#define JZ4780_CLK_DDR          15
+#define JZ4780_CLK_VPU          16
+#define JZ4780_CLK_I2SPLL       17
+#define JZ4780_CLK_I2S          18
+#define JZ4780_CLK_LCD0PIXCLK   19
+#define JZ4780_CLK_LCD1PIXCLK   20
+#define JZ4780_CLK_MSCMUX       21
+#define JZ4780_CLK_MSC0         22
+#define JZ4780_CLK_MSC1         23
+#define JZ4780_CLK_MSC2         24
+#define JZ4780_CLK_UHC          25
+#define JZ4780_CLK_SSIPLL       26
+#define JZ4780_CLK_SSI          27
+#define JZ4780_CLK_CIMMCLK      28
+#define JZ4780_CLK_PCMPLL       29
+#define JZ4780_CLK_PCM          30
+#define JZ4780_CLK_GPU          31
+#define JZ4780_CLK_HDMI         32
+#define JZ4780_CLK_BCH          33
+#define JZ4780_CLK_NEMC         34
+#define JZ4780_CLK_OTG0         35
+#define JZ4780_CLK_SSI0         36
+#define JZ4780_CLK_SMB0         37
+#define JZ4780_CLK_SMB1         38
+#define JZ4780_CLK_SCC          39
+#define JZ4780_CLK_AIC          40
+#define JZ4780_CLK_TSSI0        41
+#define JZ4780_CLK_OWI          42
+#define JZ4780_CLK_KBC          43
+#define JZ4780_CLK_SADC         44
+#define JZ4780_CLK_UART0        45
+#define JZ4780_CLK_UART1        46
+#define JZ4780_CLK_UART2        47
+#define JZ4780_CLK_UART3        48
+#define JZ4780_CLK_SSI1         49
+#define JZ4780_CLK_SSI2         50
+#define JZ4780_CLK_PDMA         51
+#define JZ4780_CLK_GPS          52
+#define JZ4780_CLK_MAC          53
+#define JZ4780_CLK_SMB2         54
+#define JZ4780_CLK_CIM          55
+#define JZ4780_CLK_LCD          56
+#define JZ4780_CLK_TVE          57
+#define JZ4780_CLK_IPU          58
+#define JZ4780_CLK_DDR0         59
+#define JZ4780_CLK_DDR1         60
+#define JZ4780_CLK_SMB3         61
+#define JZ4780_CLK_TSSI1        62
+#define JZ4780_CLK_COMPRESS     63
+#define JZ4780_CLK_AIC1         64
+#define JZ4780_CLK_GPVLC        65
+#define JZ4780_CLK_OTG1         66
+#define JZ4780_CLK_UART4        67
+#define JZ4780_CLK_AHBMON       68
+#define JZ4780_CLK_SMB4         69
+#define JZ4780_CLK_DES          70
+#define JZ4780_CLK_X2D          71
+#define JZ4780_CLK_CORE1        72
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/phy/phy-pistachio-usb.h b/include/dt-bindings/phy/phy-pistachio-usb.h
new file mode 100644
index 000000000000..d1877aa0a3f5
--- /dev/null
+++ b/include/dt-bindings/phy/phy-pistachio-usb.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PHY_PISTACHIO
+#define _DT_BINDINGS_PHY_PISTACHIO
+
+#define REFCLK_XO_CRYSTAL       0x0
+#define REFCLK_X0_EXT_CLK       0x1
+#define REFCLK_CLK_CORE         0x2
+
+#endif /* _DT_BINDINGS_PHY_PISTACHIO */
diff --git a/include/linux/bcm47xx_nvram.h b/include/linux/bcm47xx_nvram.h
index b12b07e75929..2793652fbf66 100644
--- a/include/linux/bcm47xx_nvram.h
+++ b/include/linux/bcm47xx_nvram.h
@@ -10,11 +10,17 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/vmalloc.h>
 
-#ifdef CONFIG_BCM47XX
+#ifdef CONFIG_BCM47XX_NVRAM
 int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
 int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
 int bcm47xx_nvram_gpio_pin(const char *name);
+char *bcm47xx_nvram_get_contents(size_t *val_len);
+static inline void bcm47xx_nvram_release_contents(char *nvram)
+{
+        vfree(nvram);
+};
 #else
 static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)
 {
@@ -29,6 +35,15 @@ static inline int bcm47xx_nvram_gpio_pin(const char *name)
 {
         return -ENOTSUPP;
 };
+
+static inline char *bcm47xx_nvram_get_contents(size_t *val_len)
+{
+        return NULL;
+};
+
+static inline void bcm47xx_nvram_release_contents(char *nvram)
+{
+};
 #endif