Merge tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:

 - removal of AVR32 support in dw driver as AVR32 is gone

 - new driver for Broadcom stream buffer accelerator (SBA) RAID driver

 - add support for Faraday Technology FTDMAC020 in amba-pl08x driver

 - IOMMU support in pl330 driver

 - updates to bunch of drivers

* tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (36 commits)
  dmaengine: qcom_hidma: correct API violation for submit
  dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpy
  dmaengine: tegra-apb: Really fix runtime-pm usage
  dmaengine: fsl_raid: make of_device_ids const.
  dmaengine: qcom_hidma: allow ACPI/DT parameters to be overridden
  dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly
  dmaengine: Kconfig: Simplify the help text for MXS_DMA
  dmaengine: pl330: Delete unused functions
  dmaengine: Replace WARN_TAINT_ONCE() with pr_warn_once()
  dmaengine: Kconfig: Extend the dependency for MXS_DMA
  dmaengine: mxs: Use %zu for printing a size_t variable
  dmaengine: ste_dma40: Cleanup scatterlist layering violations
  dmaengine: imx-dma: cleanup scatterlist layering violations
  dmaengine: use proper name for the R-Car SoC
  dmaengine: imx-sdma: Fix compilation warning.
  dmaengine: imx-sdma: Handle return value of clk_prepare_enable
  dmaengine: pl330: Add IOMMU support to slave tranfers
  dmaengine: DW DMAC: Handle return value of clk_prepare_enable
  dmaengine: pl08x: use GENMASK() to create bitmasks
  dmaengine: pl08x: Add support for Faraday Technology FTDMAC020
  ...

3 files changed, 121 insertions, 17 deletions

diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 580b5323a717..ab036b6b1804 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -44,7 +44,14 @@
 
 #define PL080_SYNC                              (0x34)
 
-/* Per channel configuration registers */
+/* The Faraday Technology FTDMAC020 variant registers */
+#define FTDMAC020_CH_BUSY                       (0x20)
+/* Identical to PL080_CONFIG */
+#define FTDMAC020_CSR                           (0x24)
+/* Identical to PL080_SYNC */
+#define FTDMAC020_SYNC                          (0x2C)
+#define FTDMAC020_REVISION                      (0x30)
+#define FTDMAC020_FEATURE                       (0x34)
 
 /* Per channel configuration registers */
 #define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
@@ -55,13 +62,20 @@
 #define PL080_CH_CONFIG                         (0x10)
 #define PL080S_CH_CONTROL2                      (0x10)
 #define PL080S_CH_CONFIG                        (0x14)
-
-#define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
+/* The Faraday FTDMAC020 derivative shuffles the registers around */
+#define FTDMAC020_CH_CSR                        (0x00)
+#define FTDMAC020_CH_CFG                        (0x04)
+#define FTDMAC020_CH_SRC_ADDR                   (0x08)
+#define FTDMAC020_CH_DST_ADDR                   (0x0C)
+#define FTDMAC020_CH_LLP                        (0x10)
+#define FTDMAC020_CH_SIZE                       (0x14)
+
+#define PL080_LLI_ADDR_MASK                     GENMASK(31, 2)
 #define PL080_LLI_ADDR_SHIFT                    (2)
 #define PL080_LLI_LM_AHB2                       BIT(0)
 
 #define PL080_CONTROL_TC_IRQ_EN                 BIT(31)
-#define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
+#define PL080_CONTROL_PROT_MASK                 GENMASK(30, 28)
 #define PL080_CONTROL_PROT_SHIFT                (28)
 #define PL080_CONTROL_PROT_CACHE                BIT(30)
 #define PL080_CONTROL_PROT_BUFF                 BIT(29)
@@ -70,16 +84,16 @@
 #define PL080_CONTROL_SRC_INCR                  BIT(26)
 #define PL080_CONTROL_DST_AHB2                  BIT(25)
 #define PL080_CONTROL_SRC_AHB2                  BIT(24)
-#define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
+#define PL080_CONTROL_DWIDTH_MASK               GENMASK(23, 21)
 #define PL080_CONTROL_DWIDTH_SHIFT              (21)
-#define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
+#define PL080_CONTROL_SWIDTH_MASK               GENMASK(20, 18)
 #define PL080_CONTROL_SWIDTH_SHIFT              (18)
-#define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
+#define PL080_CONTROL_DB_SIZE_MASK              GENMASK(17, 15)
 #define PL080_CONTROL_DB_SIZE_SHIFT             (15)
-#define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
+#define PL080_CONTROL_SB_SIZE_MASK              GENMASK(14, 12)
 #define PL080_CONTROL_SB_SIZE_SHIFT             (12)
-#define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
-#define PL080S_CONTROL_TRANSFER_SIZE_MASK       (0x1ffffff << 0)
+#define PL080_CONTROL_TRANSFER_SIZE_MASK        GENMASK(11, 0)
+#define PL080S_CONTROL_TRANSFER_SIZE_MASK       GENMASK(24, 0)
 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
 
 #define PL080_BSIZE_1                           (0x0)
@@ -102,11 +116,11 @@
 #define PL080_CONFIG_LOCK                       BIT(16)
 #define PL080_CONFIG_TC_IRQ_MASK                BIT(15)
 #define PL080_CONFIG_ERR_IRQ_MASK               BIT(14)
-#define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
+#define PL080_CONFIG_FLOW_CONTROL_MASK          GENMASK(13, 11)
 #define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
-#define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
+#define PL080_CONFIG_DST_SEL_MASK               GENMASK(9, 6)
 #define PL080_CONFIG_DST_SEL_SHIFT              (6)
-#define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
+#define PL080_CONFIG_SRC_SEL_MASK               GENMASK(4, 1)
 #define PL080_CONFIG_SRC_SEL_SHIFT              (1)
 #define PL080_CONFIG_ENABLE                     BIT(0)
 
@@ -119,6 +133,73 @@
 #define PL080_FLOW_PER2MEM_PER                  (0x6)
 #define PL080_FLOW_SRC2DST_SRC                  (0x7)
 
+#define FTDMAC020_CH_CSR_TC_MSK                 BIT(31)
+/* Later versions have a threshold in bits 24..26,  */
+#define FTDMAC020_CH_CSR_FIFOTH_MSK             GENMASK(26, 24)
+#define FTDMAC020_CH_CSR_FIFOTH_SHIFT           (24)
+#define FTDMAC020_CH_CSR_CHPR1_MSK              GENMASK(23, 22)
+#define FTDMAC020_CH_CSR_PROT3                  BIT(21)
+#define FTDMAC020_CH_CSR_PROT2                  BIT(20)
+#define FTDMAC020_CH_CSR_PROT1                  BIT(19)
+#define FTDMAC020_CH_CSR_SRC_SIZE_MSK           GENMASK(18, 16)
+#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT         (16)
+#define FTDMAC020_CH_CSR_ABT                    BIT(15)
+#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK          GENMASK(13, 11)
+#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT        (11)
+#define FTDMAC020_CH_CSR_DST_WIDTH_MSK          GENMASK(10, 8)
+#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT        (8)
+#define FTDMAC020_CH_CSR_MODE                   BIT(7)
+/* 00 = increase, 01 = decrease, 10 = fix */
+#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK          GENMASK(6, 5)
+#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT        (5)
+#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK          GENMASK(4, 3)
+#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT        (3)
+#define FTDMAC020_CH_CSR_SRC_SEL                BIT(2)
+#define FTDMAC020_CH_CSR_DST_SEL                BIT(1)
+#define FTDMAC020_CH_CSR_EN                     BIT(0)
+
+/* FIFO threshold setting */
+#define FTDMAC020_CH_CSR_FIFOTH_1               (0x0)
+#define FTDMAC020_CH_CSR_FIFOTH_2               (0x1)
+#define FTDMAC020_CH_CSR_FIFOTH_4               (0x2)
+#define FTDMAC020_CH_CSR_FIFOTH_8               (0x3)
+#define FTDMAC020_CH_CSR_FIFOTH_16              (0x4)
+/* The FTDMAC020 supports 64bit wide transfers */
+#define FTDMAC020_WIDTH_64BIT                   (0x3)
+/* Address can be increased, decreased or fixed */
+#define FTDMAC020_CH_CSR_SRCAD_CTL_INC          (0x0)
+#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC          (0x1)
+#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED        (0x2)
+
+#define FTDMAC020_CH_CFG_LLP_CNT_MASK           GENMASK(19, 16)
+#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT          (16)
+#define FTDMAC020_CH_CFG_BUSY                   BIT(8)
+#define FTDMAC020_CH_CFG_INT_ABT_MASK           BIT(2)
+#define FTDMAC020_CH_CFG_INT_ERR_MASK           BIT(1)
+#define FTDMAC020_CH_CFG_INT_TC_MASK            BIT(0)
+
+/* Inside the LLIs, the applicable CSR fields are mapped differently */
+#define FTDMAC020_LLI_TC_MSK                    BIT(28)
+#define FTDMAC020_LLI_SRC_WIDTH_MSK             GENMASK(27, 25)
+#define FTDMAC020_LLI_SRC_WIDTH_SHIFT           (25)
+#define FTDMAC020_LLI_DST_WIDTH_MSK             GENMASK(24, 22)
+#define FTDMAC020_LLI_DST_WIDTH_SHIFT           (22)
+#define FTDMAC020_LLI_SRCAD_CTL_MSK             GENMASK(21, 20)
+#define FTDMAC020_LLI_SRCAD_CTL_SHIFT           (20)
+#define FTDMAC020_LLI_DSTAD_CTL_MSK             GENMASK(19, 18)
+#define FTDMAC020_LLI_DSTAD_CTL_SHIFT           (18)
+#define FTDMAC020_LLI_SRC_SEL                   BIT(17)
+#define FTDMAC020_LLI_DST_SEL                   BIT(16)
+#define FTDMAC020_LLI_TRANSFER_SIZE_MASK        GENMASK(11, 0)
+#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT       (0)
+
+#define FTDMAC020_CFG_LLP_CNT_MASK              GENMASK(19, 16)
+#define FTDMAC020_CFG_LLP_CNT_SHIFT             (16)
+#define FTDMAC020_CFG_BUSY                      BIT(8)
+#define FTDMAC020_CFG_INT_ABT_MSK               BIT(2)
+#define FTDMAC020_CFG_INT_ERR_MSK               BIT(1)
+#define FTDMAC020_CFG_INT_TC_MSK                BIT(0)
+
 /* DMA linked list chain structure */
 
 struct pl080_lli {
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 5308eae9ce35..79d1bcee738d 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -47,8 +47,6 @@ enum {
  * devices with static assignments
  * @muxval: a number usually used to poke into some mux regiser to
  * mux in the signal to this channel
- * @cctl_memcpy: options for the channel control register for memcpy
- *  *** not used for slave channels ***
  * @addr: source/target address in physical memory for this DMA channel,
  * can be the address of a FIFO register for burst requests for example.
  * This can be left undefined if the PrimeCell API is used for configuring
@@ -63,12 +61,28 @@ struct pl08x_channel_data {
         int min_signal;
         int max_signal;
         u32 muxval;
-        u32 cctl_memcpy;
         dma_addr_t addr;
         bool single;
         u8 periph_buses;
 };
 
+enum pl08x_burst_size {
+        PL08X_BURST_SZ_1,
+        PL08X_BURST_SZ_4,
+        PL08X_BURST_SZ_8,
+        PL08X_BURST_SZ_16,
+        PL08X_BURST_SZ_32,
+        PL08X_BURST_SZ_64,
+        PL08X_BURST_SZ_128,
+        PL08X_BURST_SZ_256,
+};
+
+enum pl08x_bus_width {
+        PL08X_BUS_WIDTH_8_BITS,
+        PL08X_BUS_WIDTH_16_BITS,
+        PL08X_BUS_WIDTH_32_BITS,
+};
+
 /**
  * struct pl08x_platform_data - the platform configuration for the PL08x
  * PrimeCells.
@@ -76,6 +90,11 @@ struct pl08x_channel_data {
  * platform, all inclusive, including multiplexed channels. The available
  * physical channels will be multiplexed around these signals as they are
  * requested, just enumerate all possible channels.
+ * @num_slave_channels: number of elements in the slave channel array
+ * @memcpy_burst_size: the appropriate burst size for memcpy operations
+ * @memcpy_bus_width: memory bus width
+ * @memcpy_prot_buff: whether memcpy DMA is bufferable
+ * @memcpy_prot_cache: whether memcpy DMA is cacheable
  * @get_xfer_signal: request a physical signal to be used for a DMA transfer
  * immediately: if there is some multiplexing or similar blocking the use
  * of the channel the transfer can be denied by returning less than zero,
@@ -90,7 +109,10 @@ struct pl08x_channel_data {
 struct pl08x_platform_data {
         struct pl08x_channel_data *slave_channels;
         unsigned int num_slave_channels;
-        struct pl08x_channel_data memcpy_channel;
+        enum pl08x_burst_size memcpy_burst_size;
+        enum pl08x_bus_width memcpy_bus_width;
+        bool memcpy_prot_buff;
+        bool memcpy_prot_cache;
         int (*get_xfer_signal)(const struct pl08x_channel_data *);
         void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
         u8 lli_buses;
diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h
index 4d57bbaaa1bf..30f945329818 100644
--- a/include/linux/raid/pq.h
+++ b/include/linux/raid/pq.h
@@ -142,6 +142,7 @@ int raid6_select_algo(void);
 extern const u8 raid6_gfmul[256][256] __attribute__((aligned(256)));
 extern const u8 raid6_vgfmul[256][32] __attribute__((aligned(256)));
 extern const u8 raid6_gfexp[256]      __attribute__((aligned(256)));
+extern const u8 raid6_gflog[256]      __attribute__((aligned(256)));
 extern const u8 raid6_gfinv[256]      __attribute__((aligned(256)));
 extern const u8 raid6_gfexi[256]      __attribute__((aligned(256)));