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authorLinus Torvalds <torvalds@linux-foundation.org>2015-06-26 16:18:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-06-26 16:18:51 -0400
commit099bfbfc7fbbe22356c02f0caf709ac32e1126ea (patch)
treec2dfe2f9445255d866e9203cff9e9f865ef93513 /include
parent22165fa79814e71e7a5974b3c37a5028ed16c8f9 (diff)
parentc5fd936e992dd2829167d2adc63e151675ca6898 (diff)
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.2. I've one other new driver from freescale on my radar, it's been posted and reviewed, I'd just like to get someone to give it a last look, so maybe I'll send it or maybe I'll leave it. There is no major nouveau changes in here, Ben was working on something big, and we agreed it was a bit late, there wasn't anything else he considered urgent to merge. There might be another msm pull for some bits that are waiting on arm-soc, I'll see how we time it. This touches some "of" stuff, acks are in place except for the fixes to the build in various configs,t hat I just applied. Summary: New drivers: - virtio-gpu: KMS only pieces of driver for virtio-gpu in qemu. This is just the first part of this driver, enough to run unaccelerated userspace on. As qemu merges more we'll start adding the 3D features for the virgl 3d work. - amdgpu: a new driver from AMD to driver their newer GPUs. (VI+) It contains a new cleaner userspace API, and is a clean break from radeon moving forward, that AMD are going to concentrate on. It also contains a set of register headers auto generated from AMD internal database. core: - atomic modesetting API completed, enabled by default now. - Add support for mode_id blob to atomic ioctl to complete interface. - bunch of Displayport MST fixes - lots of misc fixes. panel: - new simple panels - fix some long-standing build issues with bridge drivers radeon: - VCE1 support - add a GPU reset counter for userspace - lots of fixes. amdkfd: - H/W debugger support module - static user-mode queues - support killing all the waves when a process terminates - use standard DECLARE_BITMAP i915: - Add Broxton support - S3, rotation support for Skylake - RPS booting tuning - CPT modeset sequence fixes - ns2501 dither support - enable cmd parser on haswell - cdclk handling fixes - gen8 dynamic pte allocation - lots of atomic conversion work exynos: - Add atomic modesetting support - Add iommu support - Consolidate drm driver initialization - and MIC, DECON and MIPI-DSI support for exynos5433 omapdrm: - atomic modesetting support (fixes lots of things in rewrite) tegra: - DP aux transaction fixes - iommu support fix msm: - adreno a306 support - various dsi bits - various 64-bit fixes - NV12MT support rcar-du: - atomic and misc fixes sti: - fix HDMI timing complaince tilcdc: - use drm component API to access tda998x driver - fix module unloading qxl: - stability fixes" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (872 commits) drm/nouveau: Pause between setting gpu to D3hot and cutting the power drm/dp/mst: close deadlock in connector destruction. drm: Always enable atomic API drm/vgem: Set unique to "vgem" of: fix a build error to of_graph_get_endpoint_by_regs function drm/dp/mst: take lock around looking up the branch device on hpd irq drm/dp/mst: make sure mst_primary mstb is valid in work function of: add EXPORT_SYMBOL for of_graph_get_endpoint_by_regs ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' drm/atomic: Don't set crtc_state->enable manually drm/exynos: dsi: do not set TE GPIO direction by input drm/exynos: dsi: add support for MIC driver as a bridge drm/exynos: dsi: add support for Exynos5433 drm/exynos: dsi: make use of array for clock access drm/exynos: dsi: make use of driver data for static values drm/exynos: dsi: add macros for register access drm/exynos: dsi: rename pll_clk to sclk_clk drm/exynos: mic: add MIC driver of: add helper for getting endpoint node of specific identifiers drm/exynos: add Exynos5433 decon driver ...
Diffstat (limited to 'include')
-rw-r--r--include/drm/bridge/ptn3460.h45
-rw-r--r--include/drm/drmP.h19
-rw-r--r--include/drm/drm_atomic.h95
-rw-r--r--include/drm/drm_atomic_helper.h5
-rw-r--r--include/drm/drm_crtc.h65
-rw-r--r--include/drm/drm_dp_helper.h6
-rw-r--r--include/drm/drm_dp_mst_helper.h4
-rw-r--r--include/drm/drm_modes.h4
-rw-r--r--include/drm/i915_pciids.h4
-rw-r--r--include/linux/of_graph.h8
-rw-r--r--include/uapi/drm/amdgpu_drm.h631
-rw-r--r--include/uapi/drm/drm.h2
-rw-r--r--include/uapi/drm/drm_fourcc.h15
-rw-r--r--include/uapi/drm/drm_mode.h20
-rw-r--r--include/uapi/drm/i915_drm.h9
-rw-r--r--include/uapi/drm/msm_drm.h76
-rw-r--r--include/uapi/drm/radeon_drm.h1
-rw-r--r--include/uapi/linux/Kbuild1
-rw-r--r--include/uapi/linux/kfd_ioctl.h135
-rw-r--r--include/uapi/linux/virtio_gpu.h206
-rw-r--r--include/uapi/linux/virtio_ids.h1
-rw-r--r--include/video/exynos5433_decon.h165
22 files changed, 1399 insertions, 118 deletions
diff --git a/include/drm/bridge/ptn3460.h b/include/drm/bridge/ptn3460.h
deleted file mode 100644
index b11f8e17e72f..000000000000
--- a/include/drm/bridge/ptn3460.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * Copyright (C) 2013 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DRM_BRIDGE_PTN3460_H_
15#define _DRM_BRIDGE_PTN3460_H_
16
17struct drm_device;
18struct drm_bridge;
19struct drm_encoder;
20struct i2c_client;
21struct device_node;
22
23#if defined(CONFIG_DRM_PTN3460) || defined(CONFIG_DRM_PTN3460_MODULE)
24
25int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder,
26 struct i2c_client *client, struct device_node *node);
27
28void ptn3460_destroy(struct drm_bridge *bridge);
29
30#else
31
32static inline int ptn3460_init(struct drm_device *dev,
33 struct drm_encoder *encoder, struct i2c_client *client,
34 struct device_node *node)
35{
36 return 0;
37}
38
39static inline void ptn3460_destroy(struct drm_bridge *bridge)
40{
41}
42
43#endif
44
45#endif
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 62c40777c009..48db6a56975f 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -326,6 +326,10 @@ struct drm_file {
326 struct list_head fbs; 326 struct list_head fbs;
327 struct mutex fbs_lock; 327 struct mutex fbs_lock;
328 328
329 /** User-created blob properties; this retains a reference on the
330 * property. */
331 struct list_head blobs;
332
329 wait_queue_head_t event_wait; 333 wait_queue_head_t event_wait;
330 struct list_head event_list; 334 struct list_head event_list;
331 int event_space; 335 int event_space;
@@ -355,8 +359,7 @@ struct drm_lock_data {
355 * @minor: Link back to minor char device we are master for. Immutable. 359 * @minor: Link back to minor char device we are master for. Immutable.
356 * @unique: Unique identifier: e.g. busid. Protected by drm_global_mutex. 360 * @unique: Unique identifier: e.g. busid. Protected by drm_global_mutex.
357 * @unique_len: Length of unique field. Protected by drm_global_mutex. 361 * @unique_len: Length of unique field. Protected by drm_global_mutex.
358 * @magiclist: Hash of used authentication tokens. Protected by struct_mutex. 362 * @magic_map: Map of used authentication tokens. Protected by struct_mutex.
359 * @magicfree: List of used authentication tokens. Protected by struct_mutex.
360 * @lock: DRI lock information. 363 * @lock: DRI lock information.
361 * @driver_priv: Pointer to driver-private information. 364 * @driver_priv: Pointer to driver-private information.
362 */ 365 */
@@ -365,8 +368,7 @@ struct drm_master {
365 struct drm_minor *minor; 368 struct drm_minor *minor;
366 char *unique; 369 char *unique;
367 int unique_len; 370 int unique_len;
368 struct drm_open_hash magiclist; 371 struct idr magic_map;
369 struct list_head magicfree;
370 struct drm_lock_data lock; 372 struct drm_lock_data lock;
371 void *driver_priv; 373 void *driver_priv;
372}; 374};
@@ -686,9 +688,13 @@ struct drm_pending_vblank_event {
686struct drm_vblank_crtc { 688struct drm_vblank_crtc {
687 struct drm_device *dev; /* pointer to the drm_device */ 689 struct drm_device *dev; /* pointer to the drm_device */
688 wait_queue_head_t queue; /**< VBLANK wait queue */ 690 wait_queue_head_t queue; /**< VBLANK wait queue */
689 struct timeval time[DRM_VBLANKTIME_RBSIZE]; /**< timestamp of current count */
690 struct timer_list disable_timer; /* delayed disable timer */ 691 struct timer_list disable_timer; /* delayed disable timer */
691 atomic_t count; /**< number of VBLANK interrupts */ 692
693 /* vblank counter, protected by dev->vblank_time_lock for writes */
694 unsigned long count;
695 /* vblank timestamps, protected by dev->vblank_time_lock for writes */
696 struct timeval time[DRM_VBLANKTIME_RBSIZE];
697
692 atomic_t refcount; /* number of users of vblank interruptsper crtc */ 698 atomic_t refcount; /* number of users of vblank interruptsper crtc */
693 u32 last; /* protected by dev->vbl_lock, used */ 699 u32 last; /* protected by dev->vbl_lock, used */
694 /* for wraparound handling */ 700 /* for wraparound handling */
@@ -812,6 +818,7 @@ struct drm_device {
812#endif 818#endif
813 819
814 struct platform_device *platformdev; /**< Platform device struture */ 820 struct platform_device *platformdev; /**< Platform device struture */
821 struct virtio_device *virtdev;
815 822
816 struct drm_sg_mem *sg; /**< Scatter gather memory */ 823 struct drm_sg_mem *sg; /**< Scatter gather memory */
817 unsigned int num_crtcs; /**< Number of CRTCs on this device */ 824 unsigned int num_crtcs; /**< Number of CRTCs on this device */
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index c157103492b0..8a3a913320eb 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -35,6 +35,11 @@ drm_atomic_state_alloc(struct drm_device *dev);
35void drm_atomic_state_clear(struct drm_atomic_state *state); 35void drm_atomic_state_clear(struct drm_atomic_state *state);
36void drm_atomic_state_free(struct drm_atomic_state *state); 36void drm_atomic_state_free(struct drm_atomic_state *state);
37 37
38int __must_check
39drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state);
40void drm_atomic_state_default_clear(struct drm_atomic_state *state);
41void drm_atomic_state_default_release(struct drm_atomic_state *state);
42
38struct drm_crtc_state * __must_check 43struct drm_crtc_state * __must_check
39drm_atomic_get_crtc_state(struct drm_atomic_state *state, 44drm_atomic_get_crtc_state(struct drm_atomic_state *state,
40 struct drm_crtc *crtc); 45 struct drm_crtc *crtc);
@@ -54,6 +59,62 @@ int drm_atomic_connector_set_property(struct drm_connector *connector,
54 struct drm_connector_state *state, struct drm_property *property, 59 struct drm_connector_state *state, struct drm_property *property,
55 uint64_t val); 60 uint64_t val);
56 61
62/**
63 * drm_atomic_get_existing_crtc_state - get crtc state, if it exists
64 * @state: global atomic state object
65 * @crtc: crtc to grab
66 *
67 * This function returns the crtc state for the given crtc, or NULL
68 * if the crtc is not part of the global atomic state.
69 */
70static inline struct drm_crtc_state *
71drm_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
72 struct drm_crtc *crtc)
73{
74 return state->crtc_states[drm_crtc_index(crtc)];
75}
76
77/**
78 * drm_atomic_get_existing_plane_state - get plane state, if it exists
79 * @state: global atomic state object
80 * @plane: plane to grab
81 *
82 * This function returns the plane state for the given plane, or NULL
83 * if the plane is not part of the global atomic state.
84 */
85static inline struct drm_plane_state *
86drm_atomic_get_existing_plane_state(struct drm_atomic_state *state,
87 struct drm_plane *plane)
88{
89 return state->plane_states[drm_plane_index(plane)];
90}
91
92/**
93 * drm_atomic_get_existing_connector_state - get connector state, if it exists
94 * @state: global atomic state object
95 * @connector: connector to grab
96 *
97 * This function returns the connector state for the given connector,
98 * or NULL if the connector is not part of the global atomic state.
99 */
100static inline struct drm_connector_state *
101drm_atomic_get_existing_connector_state(struct drm_atomic_state *state,
102 struct drm_connector *connector)
103{
104 int index = drm_connector_index(connector);
105
106 if (index >= state->num_connector)
107 return NULL;
108
109 return state->connector_states[index];
110}
111
112int __must_check
113drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
114 struct drm_display_mode *mode);
115int __must_check
116drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
117 struct drm_property_blob *blob);
57int __must_check 118int __must_check
58drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state, 119drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
59 struct drm_crtc *crtc); 120 struct drm_crtc *crtc);
@@ -65,6 +126,10 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
65int __must_check 126int __must_check
66drm_atomic_add_affected_connectors(struct drm_atomic_state *state, 127drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
67 struct drm_crtc *crtc); 128 struct drm_crtc *crtc);
129int __must_check
130drm_atomic_add_affected_planes(struct drm_atomic_state *state,
131 struct drm_crtc *crtc);
132
68int 133int
69drm_atomic_connectors_for_crtc(struct drm_atomic_state *state, 134drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
70 struct drm_crtc *crtc); 135 struct drm_crtc *crtc);
@@ -77,26 +142,32 @@ int __must_check drm_atomic_async_commit(struct drm_atomic_state *state);
77 142
78#define for_each_connector_in_state(state, connector, connector_state, __i) \ 143#define for_each_connector_in_state(state, connector, connector_state, __i) \
79 for ((__i) = 0; \ 144 for ((__i) = 0; \
80 (connector) = (state)->connectors[__i], \ 145 (__i) < (state)->num_connector && \
81 (connector_state) = (state)->connector_states[__i], \ 146 ((connector) = (state)->connectors[__i], \
82 (__i) < (state)->num_connector; \ 147 (connector_state) = (state)->connector_states[__i], 1); \
83 (__i)++) \ 148 (__i)++) \
84 if (connector) 149 if (connector)
85 150
86#define for_each_crtc_in_state(state, crtc, crtc_state, __i) \ 151#define for_each_crtc_in_state(state, crtc, crtc_state, __i) \
87 for ((__i) = 0; \ 152 for ((__i) = 0; \
88 (crtc) = (state)->crtcs[__i], \ 153 (__i) < (state)->dev->mode_config.num_crtc && \
89 (crtc_state) = (state)->crtc_states[__i], \ 154 ((crtc) = (state)->crtcs[__i], \
90 (__i) < (state)->dev->mode_config.num_crtc; \ 155 (crtc_state) = (state)->crtc_states[__i], 1); \
91 (__i)++) \ 156 (__i)++) \
92 if (crtc_state) 157 if (crtc_state)
93 158
94#define for_each_plane_in_state(state, plane, plane_state, __i) \ 159#define for_each_plane_in_state(state, plane, plane_state, __i) \
95 for ((__i) = 0; \ 160 for ((__i) = 0; \
96 (plane) = (state)->planes[__i], \ 161 (__i) < (state)->dev->mode_config.num_total_plane && \
97 (plane_state) = (state)->plane_states[__i], \ 162 ((plane) = (state)->planes[__i], \
98 (__i) < (state)->dev->mode_config.num_total_plane; \ 163 (plane_state) = (state)->plane_states[__i], 1); \
99 (__i)++) \ 164 (__i)++) \
100 if (plane_state) 165 if (plane_state)
166static inline bool
167drm_atomic_crtc_needs_modeset(struct drm_crtc_state *state)
168{
169 return state->mode_changed || state->active_changed;
170}
171
101 172
102#endif /* DRM_ATOMIC_H_ */ 173#endif /* DRM_ATOMIC_H_ */
diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
index d665781eb542..cc1fee8a12d0 100644
--- a/include/drm/drm_atomic_helper.h
+++ b/include/drm/drm_atomic_helper.h
@@ -43,6 +43,10 @@ int drm_atomic_helper_commit(struct drm_device *dev,
43void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, 43void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
44 struct drm_atomic_state *old_state); 44 struct drm_atomic_state *old_state);
45 45
46void
47drm_atomic_helper_update_legacy_modeset_state(struct drm_device *dev,
48 struct drm_atomic_state *old_state);
49
46void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev, 50void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev,
47 struct drm_atomic_state *state); 51 struct drm_atomic_state *state);
48void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, 52void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev,
@@ -54,6 +58,7 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev,
54 struct drm_atomic_state *state); 58 struct drm_atomic_state *state);
55void drm_atomic_helper_cleanup_planes(struct drm_device *dev, 59void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
56 struct drm_atomic_state *old_state); 60 struct drm_atomic_state *old_state);
61void drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state);
57 62
58void drm_atomic_helper_swap_state(struct drm_device *dev, 63void drm_atomic_helper_swap_state(struct drm_device *dev,
59 struct drm_atomic_state *state); 64 struct drm_atomic_state *state);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index ca71c03143d1..57ca8cc383a6 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -216,7 +216,10 @@ struct drm_framebuffer {
216 216
217struct drm_property_blob { 217struct drm_property_blob {
218 struct drm_mode_object base; 218 struct drm_mode_object base;
219 struct list_head head; 219 struct drm_device *dev;
220 struct kref refcount;
221 struct list_head head_global;
222 struct list_head head_file;
220 size_t length; 223 size_t length;
221 unsigned char data[]; 224 unsigned char data[];
222}; 225};
@@ -296,6 +299,9 @@ struct drm_crtc_state {
296 299
297 struct drm_display_mode mode; 300 struct drm_display_mode mode;
298 301
302 /* blob property to expose current mode to atomic userspace */
303 struct drm_property_blob *mode_blob;
304
299 struct drm_pending_vblank_event *event; 305 struct drm_pending_vblank_event *event;
300 306
301 struct drm_atomic_state *state; 307 struct drm_atomic_state *state;
@@ -647,6 +653,7 @@ struct drm_encoder {
647 * @audio_latency: audio latency info from ELD, if found 653 * @audio_latency: audio latency info from ELD, if found
648 * @null_edid_counter: track sinks that give us all zeros for the EDID 654 * @null_edid_counter: track sinks that give us all zeros for the EDID
649 * @bad_edid_counter: track sinks that give us an EDID with invalid checksum 655 * @bad_edid_counter: track sinks that give us an EDID with invalid checksum
656 * @edid_corrupt: indicates whether the last read EDID was corrupt
650 * @debugfs_entry: debugfs directory for this connector 657 * @debugfs_entry: debugfs directory for this connector
651 * @state: current atomic state for this connector 658 * @state: current atomic state for this connector
652 * @has_tile: is this connector connected to a tiled monitor 659 * @has_tile: is this connector connected to a tiled monitor
@@ -719,6 +726,11 @@ struct drm_connector {
719 int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */ 726 int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */
720 unsigned bad_edid_counter; 727 unsigned bad_edid_counter;
721 728
729 /* Flag for raw EDID header corruption - used in Displayport
730 * compliance testing - * Displayport Link CTS Core 1.2 rev1.1 4.2.2.6
731 */
732 bool edid_corrupt;
733
722 struct dentry *debugfs_entry; 734 struct dentry *debugfs_entry;
723 735
724 struct drm_connector_state *state; 736 struct drm_connector_state *state;
@@ -731,6 +743,8 @@ struct drm_connector {
731 uint8_t num_h_tile, num_v_tile; 743 uint8_t num_h_tile, num_v_tile;
732 uint8_t tile_h_loc, tile_v_loc; 744 uint8_t tile_h_loc, tile_v_loc;
733 uint16_t tile_h_size, tile_v_size; 745 uint16_t tile_h_size, tile_v_size;
746
747 struct list_head destroy_list;
734}; 748};
735 749
736/** 750/**
@@ -895,6 +909,8 @@ struct drm_bridge_funcs {
895/** 909/**
896 * struct drm_bridge - central DRM bridge control structure 910 * struct drm_bridge - central DRM bridge control structure
897 * @dev: DRM device this bridge belongs to 911 * @dev: DRM device this bridge belongs to
912 * @encoder: encoder to which this bridge is connected
913 * @next: the next bridge in the encoder chain
898 * @of_node: device node pointer to the bridge 914 * @of_node: device node pointer to the bridge
899 * @list: to keep track of all added bridges 915 * @list: to keep track of all added bridges
900 * @base: base mode object 916 * @base: base mode object
@@ -904,6 +920,7 @@ struct drm_bridge_funcs {
904struct drm_bridge { 920struct drm_bridge {
905 struct drm_device *dev; 921 struct drm_device *dev;
906 struct drm_encoder *encoder; 922 struct drm_encoder *encoder;
923 struct drm_bridge *next;
907#ifdef CONFIG_OF 924#ifdef CONFIG_OF
908 struct device_node *of_node; 925 struct device_node *of_node;
909#endif 926#endif
@@ -977,6 +994,9 @@ struct drm_mode_set {
977 * @atomic_check: check whether a given atomic state update is possible 994 * @atomic_check: check whether a given atomic state update is possible
978 * @atomic_commit: commit an atomic state update previously verified with 995 * @atomic_commit: commit an atomic state update previously verified with
979 * atomic_check() 996 * atomic_check()
997 * @atomic_state_alloc: allocate a new atomic state
998 * @atomic_state_clear: clear the atomic state
999 * @atomic_state_free: free the atomic state
980 * 1000 *
981 * Some global (i.e. not per-CRTC, connector, etc) mode setting functions that 1001 * Some global (i.e. not per-CRTC, connector, etc) mode setting functions that
982 * involve drivers. 1002 * involve drivers.
@@ -992,6 +1012,9 @@ struct drm_mode_config_funcs {
992 int (*atomic_commit)(struct drm_device *dev, 1012 int (*atomic_commit)(struct drm_device *dev,
993 struct drm_atomic_state *a, 1013 struct drm_atomic_state *a,
994 bool async); 1014 bool async);
1015 struct drm_atomic_state *(*atomic_state_alloc)(struct drm_device *dev);
1016 void (*atomic_state_clear)(struct drm_atomic_state *state);
1017 void (*atomic_state_free)(struct drm_atomic_state *state);
995}; 1018};
996 1019
997/** 1020/**
@@ -1048,6 +1071,7 @@ struct drm_mode_group {
1048 * @poll_running: track polling status for this device 1071 * @poll_running: track polling status for this device
1049 * @output_poll_work: delayed work for polling in process context 1072 * @output_poll_work: delayed work for polling in process context
1050 * @property_blob_list: list of all the blob property objects 1073 * @property_blob_list: list of all the blob property objects
1074 * @blob_lock: mutex for blob property allocation and management
1051 * @*_property: core property tracking 1075 * @*_property: core property tracking
1052 * @preferred_depth: preferred RBG pixel depth, used by fb helpers 1076 * @preferred_depth: preferred RBG pixel depth, used by fb helpers
1053 * @prefer_shadow: hint to userspace to prefer shadow-fb rendering 1077 * @prefer_shadow: hint to userspace to prefer shadow-fb rendering
@@ -1103,6 +1127,8 @@ struct drm_mode_config {
1103 bool delayed_event; 1127 bool delayed_event;
1104 struct delayed_work output_poll_work; 1128 struct delayed_work output_poll_work;
1105 1129
1130 struct mutex blob_lock;
1131
1106 /* pointers to standard properties */ 1132 /* pointers to standard properties */
1107 struct list_head property_blob_list; 1133 struct list_head property_blob_list;
1108 struct drm_property *edid_property; 1134 struct drm_property *edid_property;
@@ -1122,6 +1148,7 @@ struct drm_mode_config {
1122 struct drm_property *prop_fb_id; 1148 struct drm_property *prop_fb_id;
1123 struct drm_property *prop_crtc_id; 1149 struct drm_property *prop_crtc_id;
1124 struct drm_property *prop_active; 1150 struct drm_property *prop_active;
1151 struct drm_property *prop_mode_id;
1125 1152
1126 /* DVI-I properties */ 1153 /* DVI-I properties */
1127 struct drm_property *dvi_i_subconnector_property; 1154 struct drm_property *dvi_i_subconnector_property;
@@ -1230,6 +1257,17 @@ extern void drm_bridge_remove(struct drm_bridge *bridge);
1230extern struct drm_bridge *of_drm_find_bridge(struct device_node *np); 1257extern struct drm_bridge *of_drm_find_bridge(struct device_node *np);
1231extern int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge); 1258extern int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge);
1232 1259
1260bool drm_bridge_mode_fixup(struct drm_bridge *bridge,
1261 const struct drm_display_mode *mode,
1262 struct drm_display_mode *adjusted_mode);
1263void drm_bridge_disable(struct drm_bridge *bridge);
1264void drm_bridge_post_disable(struct drm_bridge *bridge);
1265void drm_bridge_mode_set(struct drm_bridge *bridge,
1266 struct drm_display_mode *mode,
1267 struct drm_display_mode *adjusted_mode);
1268void drm_bridge_pre_enable(struct drm_bridge *bridge);
1269void drm_bridge_enable(struct drm_bridge *bridge);
1270
1233extern int drm_encoder_init(struct drm_device *dev, 1271extern int drm_encoder_init(struct drm_device *dev,
1234 struct drm_encoder *encoder, 1272 struct drm_encoder *encoder,
1235 const struct drm_encoder_funcs *funcs, 1273 const struct drm_encoder_funcs *funcs,
@@ -1263,6 +1301,7 @@ extern int drm_plane_init(struct drm_device *dev,
1263 bool is_primary); 1301 bool is_primary);
1264extern void drm_plane_cleanup(struct drm_plane *plane); 1302extern void drm_plane_cleanup(struct drm_plane *plane);
1265extern unsigned int drm_plane_index(struct drm_plane *plane); 1303extern unsigned int drm_plane_index(struct drm_plane *plane);
1304extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int idx);
1266extern void drm_plane_force_disable(struct drm_plane *plane); 1305extern void drm_plane_force_disable(struct drm_plane *plane);
1267extern int drm_plane_check_pixel_format(const struct drm_plane *plane, 1306extern int drm_plane_check_pixel_format(const struct drm_plane *plane,
1268 u32 format); 1307 u32 format);
@@ -1283,6 +1322,8 @@ extern const char *drm_get_dvi_i_select_name(int val);
1283extern const char *drm_get_tv_subconnector_name(int val); 1322extern const char *drm_get_tv_subconnector_name(int val);
1284extern const char *drm_get_tv_select_name(int val); 1323extern const char *drm_get_tv_select_name(int val);
1285extern void drm_fb_release(struct drm_file *file_priv); 1324extern void drm_fb_release(struct drm_file *file_priv);
1325extern void drm_property_destroy_user_blobs(struct drm_device *dev,
1326 struct drm_file *file_priv);
1286extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); 1327extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
1287extern void drm_mode_group_destroy(struct drm_mode_group *group); 1328extern void drm_mode_group_destroy(struct drm_mode_group *group);
1288extern void drm_reinit_primary_mode_group(struct drm_device *dev); 1329extern void drm_reinit_primary_mode_group(struct drm_device *dev);
@@ -1362,6 +1403,13 @@ struct drm_property *drm_property_create_object(struct drm_device *dev,
1362 int flags, const char *name, uint32_t type); 1403 int flags, const char *name, uint32_t type);
1363struct drm_property *drm_property_create_bool(struct drm_device *dev, int flags, 1404struct drm_property *drm_property_create_bool(struct drm_device *dev, int flags,
1364 const char *name); 1405 const char *name);
1406struct drm_property_blob *drm_property_create_blob(struct drm_device *dev,
1407 size_t length,
1408 const void *data);
1409struct drm_property_blob *drm_property_lookup_blob(struct drm_device *dev,
1410 uint32_t id);
1411struct drm_property_blob *drm_property_reference_blob(struct drm_property_blob *blob);
1412void drm_property_unreference_blob(struct drm_property_blob *blob);
1365extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); 1413extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property);
1366extern int drm_property_add_enum(struct drm_property *property, int index, 1414extern int drm_property_add_enum(struct drm_property *property, int index,
1367 uint64_t value, const char *name); 1415 uint64_t value, const char *name);
@@ -1421,6 +1469,10 @@ extern int drm_mode_getproperty_ioctl(struct drm_device *dev,
1421 void *data, struct drm_file *file_priv); 1469 void *data, struct drm_file *file_priv);
1422extern int drm_mode_getblob_ioctl(struct drm_device *dev, 1470extern int drm_mode_getblob_ioctl(struct drm_device *dev,
1423 void *data, struct drm_file *file_priv); 1471 void *data, struct drm_file *file_priv);
1472extern int drm_mode_createblob_ioctl(struct drm_device *dev,
1473 void *data, struct drm_file *file_priv);
1474extern int drm_mode_destroyblob_ioctl(struct drm_device *dev,
1475 void *data, struct drm_file *file_priv);
1424extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev, 1476extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
1425 void *data, struct drm_file *file_priv); 1477 void *data, struct drm_file *file_priv);
1426extern int drm_mode_getencoder(struct drm_device *dev, 1478extern int drm_mode_getencoder(struct drm_device *dev,
@@ -1442,7 +1494,8 @@ extern void drm_set_preferred_mode(struct drm_connector *connector,
1442 int hpref, int vpref); 1494 int hpref, int vpref);
1443 1495
1444extern int drm_edid_header_is_valid(const u8 *raw_edid); 1496extern int drm_edid_header_is_valid(const u8 *raw_edid);
1445extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid); 1497extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1498 bool *edid_corrupt);
1446extern bool drm_edid_is_valid(struct edid *edid); 1499extern bool drm_edid_is_valid(struct edid *edid);
1447 1500
1448extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev, 1501extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
@@ -1525,14 +1578,6 @@ static inline struct drm_property *drm_property_find(struct drm_device *dev,
1525 return mo ? obj_to_property(mo) : NULL; 1578 return mo ? obj_to_property(mo) : NULL;
1526} 1579}
1527 1580
1528static inline struct drm_property_blob *
1529drm_property_blob_find(struct drm_device *dev, uint32_t id)
1530{
1531 struct drm_mode_object *mo;
1532 mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_BLOB);
1533 return mo ? obj_to_blob(mo) : NULL;
1534}
1535
1536/* Plane list iterator for legacy (overlay only) planes. */ 1581/* Plane list iterator for legacy (overlay only) planes. */
1537#define drm_for_each_legacy_plane(plane, planelist) \ 1582#define drm_for_each_legacy_plane(plane, planelist) \
1538 list_for_each_entry(plane, planelist, head) \ 1583 list_for_each_entry(plane, planelist, head) \
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 523f04c90dea..2e86f642fc33 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -679,9 +679,9 @@ struct drm_dp_aux_msg {
679 * An AUX channel can also be used to transport I2C messages to a sink. A 679 * An AUX channel can also be used to transport I2C messages to a sink. A
680 * typical application of that is to access an EDID that's present in the 680 * typical application of that is to access an EDID that's present in the
681 * sink device. The .transfer() function can also be used to execute such 681 * sink device. The .transfer() function can also be used to execute such
682 * transactions. The drm_dp_aux_register_i2c_bus() function registers an 682 * transactions. The drm_dp_aux_register() function registers an I2C
683 * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers 683 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
684 * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter. 684 * should call drm_dp_aux_unregister() to remove the I2C adapter.
685 * The I2C adapter uses long transfers by default; if a partial response is 685 * The I2C adapter uses long transfers by default; if a partial response is
686 * received, the adapter will drop down to the size given by the partial 686 * received, the adapter will drop down to the size given by the partial
687 * response for this transaction only. 687 * response for this transaction only.
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index a2507817be41..86d0b25ed054 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -463,6 +463,10 @@ struct drm_dp_mst_topology_mgr {
463 struct work_struct work; 463 struct work_struct work;
464 464
465 struct work_struct tx_work; 465 struct work_struct tx_work;
466
467 struct list_head destroy_connector_list;
468 struct mutex destroy_connector_lock;
469 struct work_struct destroy_connector_work;
466}; 470};
467 471
468int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, int conn_base_id); 472int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, int conn_base_id);
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index 0616188c7801..08a8cac9e555 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -182,6 +182,10 @@ struct drm_cmdline_mode;
182 182
183struct drm_display_mode *drm_mode_create(struct drm_device *dev); 183struct drm_display_mode *drm_mode_create(struct drm_device *dev);
184void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode); 184void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode);
185void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,
186 const struct drm_display_mode *in);
187int drm_mode_convert_umode(struct drm_display_mode *out,
188 const struct drm_mode_modeinfo *in);
185void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); 189void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
186void drm_mode_debug_printmodeline(const struct drm_display_mode *mode); 190void drm_mode_debug_printmodeline(const struct drm_display_mode *mode);
187 191
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 613372375ada..17c445612e01 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -286,5 +286,9 @@
286 INTEL_SKL_GT2_IDS(info), \ 286 INTEL_SKL_GT2_IDS(info), \
287 INTEL_SKL_GT3_IDS(info) 287 INTEL_SKL_GT3_IDS(info)
288 288
289#define INTEL_BXT_IDS(info) \
290 INTEL_VGA_DEVICE(0x0A84, info), \
291 INTEL_VGA_DEVICE(0x1A84, info), \
292 INTEL_VGA_DEVICE(0x5A84, info)
289 293
290#endif /* _I915_PCIIDS_H */ 294#endif /* _I915_PCIIDS_H */
diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
index 7bc92e050608..f8bcd0e21a26 100644
--- a/include/linux/of_graph.h
+++ b/include/linux/of_graph.h
@@ -45,6 +45,8 @@ int of_graph_parse_endpoint(const struct device_node *node,
45struct device_node *of_graph_get_port_by_id(struct device_node *node, u32 id); 45struct device_node *of_graph_get_port_by_id(struct device_node *node, u32 id);
46struct device_node *of_graph_get_next_endpoint(const struct device_node *parent, 46struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
47 struct device_node *previous); 47 struct device_node *previous);
48struct device_node *of_graph_get_endpoint_by_regs(
49 const struct device_node *parent, int port_reg, int reg);
48struct device_node *of_graph_get_remote_port_parent( 50struct device_node *of_graph_get_remote_port_parent(
49 const struct device_node *node); 51 const struct device_node *node);
50struct device_node *of_graph_get_remote_port(const struct device_node *node); 52struct device_node *of_graph_get_remote_port(const struct device_node *node);
@@ -69,6 +71,12 @@ static inline struct device_node *of_graph_get_next_endpoint(
69 return NULL; 71 return NULL;
70} 72}
71 73
74static inline struct device_node *of_graph_get_endpoint_by_regs(
75 const struct device_node *parent, int port_reg, int reg)
76{
77 return NULL;
78}
79
72static inline struct device_node *of_graph_get_remote_port_parent( 80static inline struct device_node *of_graph_get_remote_port_parent(
73 const struct device_node *node) 81 const struct device_node *node)
74{ 82{
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
new file mode 100644
index 000000000000..d3f4832db289
--- /dev/null
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -0,0 +1,631 @@
1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include <drm/drm.h>
36
37#define DRM_AMDGPU_GEM_CREATE 0x00
38#define DRM_AMDGPU_GEM_MMAP 0x01
39#define DRM_AMDGPU_CTX 0x02
40#define DRM_AMDGPU_BO_LIST 0x03
41#define DRM_AMDGPU_CS 0x04
42#define DRM_AMDGPU_INFO 0x05
43#define DRM_AMDGPU_GEM_METADATA 0x06
44#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
45#define DRM_AMDGPU_GEM_VA 0x08
46#define DRM_AMDGPU_WAIT_CS 0x09
47#define DRM_AMDGPU_GEM_OP 0x10
48#define DRM_AMDGPU_GEM_USERPTR 0x11
49
50#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
51#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
52#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
53#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
54#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
55#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
56#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
57#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
58#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
59#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
60#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
61#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
62
63#define AMDGPU_GEM_DOMAIN_CPU 0x1
64#define AMDGPU_GEM_DOMAIN_GTT 0x2
65#define AMDGPU_GEM_DOMAIN_VRAM 0x4
66#define AMDGPU_GEM_DOMAIN_GDS 0x8
67#define AMDGPU_GEM_DOMAIN_GWS 0x10
68#define AMDGPU_GEM_DOMAIN_OA 0x20
69
70/* Flag that CPU access will be required for the case of VRAM domain */
71#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
72/* Flag that CPU access will not work, this VRAM domain is invisible */
73#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
74/* Flag that USWC attributes should be used for GTT */
75#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
76
77struct drm_amdgpu_gem_create_in {
78 /** the requested memory size */
79 uint64_t bo_size;
80 /** physical start_addr alignment in bytes for some HW requirements */
81 uint64_t alignment;
82 /** the requested memory domains */
83 uint64_t domains;
84 /** allocation flags */
85 uint64_t domain_flags;
86};
87
88struct drm_amdgpu_gem_create_out {
89 /** returned GEM object handle */
90 uint32_t handle;
91 uint32_t _pad;
92};
93
94union drm_amdgpu_gem_create {
95 struct drm_amdgpu_gem_create_in in;
96 struct drm_amdgpu_gem_create_out out;
97};
98
99/** Opcode to create new residency list. */
100#define AMDGPU_BO_LIST_OP_CREATE 0
101/** Opcode to destroy previously created residency list */
102#define AMDGPU_BO_LIST_OP_DESTROY 1
103/** Opcode to update resource information in the list */
104#define AMDGPU_BO_LIST_OP_UPDATE 2
105
106struct drm_amdgpu_bo_list_in {
107 /** Type of operation */
108 uint32_t operation;
109 /** Handle of list or 0 if we want to create one */
110 uint32_t list_handle;
111 /** Number of BOs in list */
112 uint32_t bo_number;
113 /** Size of each element describing BO */
114 uint32_t bo_info_size;
115 /** Pointer to array describing BOs */
116 uint64_t bo_info_ptr;
117};
118
119struct drm_amdgpu_bo_list_entry {
120 /** Handle of BO */
121 uint32_t bo_handle;
122 /** New (if specified) BO priority to be used during migration */
123 uint32_t bo_priority;
124};
125
126struct drm_amdgpu_bo_list_out {
127 /** Handle of resource list */
128 uint32_t list_handle;
129 uint32_t _pad;
130};
131
132union drm_amdgpu_bo_list {
133 struct drm_amdgpu_bo_list_in in;
134 struct drm_amdgpu_bo_list_out out;
135};
136
137/* context related */
138#define AMDGPU_CTX_OP_ALLOC_CTX 1
139#define AMDGPU_CTX_OP_FREE_CTX 2
140#define AMDGPU_CTX_OP_QUERY_STATE 3
141
142/* GPU reset status */
143#define AMDGPU_CTX_NO_RESET 0
144/* this the context caused it */
145#define AMDGPU_CTX_GUILTY_RESET 1
146/* some other context caused it */
147#define AMDGPU_CTX_INNOCENT_RESET 2
148/* unknown cause */
149#define AMDGPU_CTX_UNKNOWN_RESET 3
150
151struct drm_amdgpu_ctx_in {
152 /** AMDGPU_CTX_OP_* */
153 uint32_t op;
154 /** For future use, no flags defined so far */
155 uint32_t flags;
156 uint32_t ctx_id;
157 uint32_t _pad;
158};
159
160union drm_amdgpu_ctx_out {
161 struct {
162 uint32_t ctx_id;
163 uint32_t _pad;
164 } alloc;
165
166 struct {
167 /** For future use, no flags defined so far */
168 uint64_t flags;
169 /** Number of resets caused by this context so far. */
170 uint32_t hangs;
171 /** Reset status since the last call of the ioctl. */
172 uint32_t reset_status;
173 } state;
174};
175
176union drm_amdgpu_ctx {
177 struct drm_amdgpu_ctx_in in;
178 union drm_amdgpu_ctx_out out;
179};
180
181/*
182 * This is not a reliable API and you should expect it to fail for any
183 * number of reasons and have fallback path that do not use userptr to
184 * perform any operation.
185 */
186#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
187#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
188#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
189#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
190
191struct drm_amdgpu_gem_userptr {
192 uint64_t addr;
193 uint64_t size;
194 /* AMDGPU_GEM_USERPTR_* */
195 uint32_t flags;
196 /* Resulting GEM handle */
197 uint32_t handle;
198};
199
200/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
201#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
202#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
203#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
204#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
205#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
206#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
207#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
208#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
209#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
210#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
211#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
212#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
213#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
214#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
215#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
216#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
217
218#define AMDGPU_TILING_SET(field, value) \
219 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
220#define AMDGPU_TILING_GET(value, field) \
221 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
222
223#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
224#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
225
226/** The same structure is shared for input/output */
227struct drm_amdgpu_gem_metadata {
228 /** GEM Object handle */
229 uint32_t handle;
230 /** Do we want get or set metadata */
231 uint32_t op;
232 struct {
233 /** For future use, no flags defined so far */
234 uint64_t flags;
235 /** family specific tiling info */
236 uint64_t tiling_info;
237 uint32_t data_size_bytes;
238 uint32_t data[64];
239 } data;
240};
241
242struct drm_amdgpu_gem_mmap_in {
243 /** the GEM object handle */
244 uint32_t handle;
245 uint32_t _pad;
246};
247
248struct drm_amdgpu_gem_mmap_out {
249 /** mmap offset from the vma offset manager */
250 uint64_t addr_ptr;
251};
252
253union drm_amdgpu_gem_mmap {
254 struct drm_amdgpu_gem_mmap_in in;
255 struct drm_amdgpu_gem_mmap_out out;
256};
257
258struct drm_amdgpu_gem_wait_idle_in {
259 /** GEM object handle */
260 uint32_t handle;
261 /** For future use, no flags defined so far */
262 uint32_t flags;
263 /** Absolute timeout to wait */
264 uint64_t timeout;
265};
266
267struct drm_amdgpu_gem_wait_idle_out {
268 /** BO status: 0 - BO is idle, 1 - BO is busy */
269 uint32_t status;
270 /** Returned current memory domain */
271 uint32_t domain;
272};
273
274union drm_amdgpu_gem_wait_idle {
275 struct drm_amdgpu_gem_wait_idle_in in;
276 struct drm_amdgpu_gem_wait_idle_out out;
277};
278
279struct drm_amdgpu_wait_cs_in {
280 /** Command submission handle */
281 uint64_t handle;
282 /** Absolute timeout to wait */
283 uint64_t timeout;
284 uint32_t ip_type;
285 uint32_t ip_instance;
286 uint32_t ring;
287 uint32_t ctx_id;
288};
289
290struct drm_amdgpu_wait_cs_out {
291 /** CS status: 0 - CS completed, 1 - CS still busy */
292 uint64_t status;
293};
294
295union drm_amdgpu_wait_cs {
296 struct drm_amdgpu_wait_cs_in in;
297 struct drm_amdgpu_wait_cs_out out;
298};
299
300#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
301#define AMDGPU_GEM_OP_SET_PLACEMENT 1
302
303/* Sets or returns a value associated with a buffer. */
304struct drm_amdgpu_gem_op {
305 /** GEM object handle */
306 uint32_t handle;
307 /** AMDGPU_GEM_OP_* */
308 uint32_t op;
309 /** Input or return value */
310 uint64_t value;
311};
312
313#define AMDGPU_VA_OP_MAP 1
314#define AMDGPU_VA_OP_UNMAP 2
315
316/* Mapping flags */
317/* readable mapping */
318#define AMDGPU_VM_PAGE_READABLE (1 << 1)
319/* writable mapping */
320#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
321/* executable mapping, new for VI */
322#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
323
324struct drm_amdgpu_gem_va {
325 /** GEM object handle */
326 uint32_t handle;
327 uint32_t _pad;
328 /** AMDGPU_VA_OP_* */
329 uint32_t operation;
330 /** AMDGPU_VM_PAGE_* */
331 uint32_t flags;
332 /** va address to assign . Must be correctly aligned.*/
333 uint64_t va_address;
334 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
335 uint64_t offset_in_bo;
336 /** Specify mapping size. Must be correctly aligned. */
337 uint64_t map_size;
338};
339
340#define AMDGPU_HW_IP_GFX 0
341#define AMDGPU_HW_IP_COMPUTE 1
342#define AMDGPU_HW_IP_DMA 2
343#define AMDGPU_HW_IP_UVD 3
344#define AMDGPU_HW_IP_VCE 4
345#define AMDGPU_HW_IP_NUM 5
346
347#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
348
349#define AMDGPU_CHUNK_ID_IB 0x01
350#define AMDGPU_CHUNK_ID_FENCE 0x02
351
352struct drm_amdgpu_cs_chunk {
353 uint32_t chunk_id;
354 uint32_t length_dw;
355 uint64_t chunk_data;
356};
357
358struct drm_amdgpu_cs_in {
359 /** Rendering context id */
360 uint32_t ctx_id;
361 /** Handle of resource list associated with CS */
362 uint32_t bo_list_handle;
363 uint32_t num_chunks;
364 uint32_t _pad;
365 /** this points to uint64_t * which point to cs chunks */
366 uint64_t chunks;
367};
368
369struct drm_amdgpu_cs_out {
370 uint64_t handle;
371};
372
373union drm_amdgpu_cs {
374 struct drm_amdgpu_cs_in in;
375 struct drm_amdgpu_cs_out out;
376};
377
378/* Specify flags to be used for IB */
379
380/* This IB should be submitted to CE */
381#define AMDGPU_IB_FLAG_CE (1<<0)
382
383/* CE Preamble */
384#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
385
386struct drm_amdgpu_cs_chunk_ib {
387 uint32_t _pad;
388 /** AMDGPU_IB_FLAG_* */
389 uint32_t flags;
390 /** Virtual address to begin IB execution */
391 uint64_t va_start;
392 /** Size of submission */
393 uint32_t ib_bytes;
394 /** HW IP to submit to */
395 uint32_t ip_type;
396 /** HW IP index of the same type to submit to */
397 uint32_t ip_instance;
398 /** Ring index to submit to */
399 uint32_t ring;
400};
401
402struct drm_amdgpu_cs_chunk_fence {
403 uint32_t handle;
404 uint32_t offset;
405};
406
407struct drm_amdgpu_cs_chunk_data {
408 union {
409 struct drm_amdgpu_cs_chunk_ib ib_data;
410 struct drm_amdgpu_cs_chunk_fence fence_data;
411 };
412};
413
414/**
415 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
416 *
417 */
418#define AMDGPU_IDS_FLAGS_FUSION 0x1
419
420/* indicate if acceleration can be working */
421#define AMDGPU_INFO_ACCEL_WORKING 0x00
422/* get the crtc_id from the mode object id? */
423#define AMDGPU_INFO_CRTC_FROM_ID 0x01
424/* query hw IP info */
425#define AMDGPU_INFO_HW_IP_INFO 0x02
426/* query hw IP instance count for the specified type */
427#define AMDGPU_INFO_HW_IP_COUNT 0x03
428/* timestamp for GL_ARB_timer_query */
429#define AMDGPU_INFO_TIMESTAMP 0x05
430/* Query the firmware version */
431#define AMDGPU_INFO_FW_VERSION 0x0e
432 /* Subquery id: Query VCE firmware version */
433 #define AMDGPU_INFO_FW_VCE 0x1
434 /* Subquery id: Query UVD firmware version */
435 #define AMDGPU_INFO_FW_UVD 0x2
436 /* Subquery id: Query GMC firmware version */
437 #define AMDGPU_INFO_FW_GMC 0x03
438 /* Subquery id: Query GFX ME firmware version */
439 #define AMDGPU_INFO_FW_GFX_ME 0x04
440 /* Subquery id: Query GFX PFP firmware version */
441 #define AMDGPU_INFO_FW_GFX_PFP 0x05
442 /* Subquery id: Query GFX CE firmware version */
443 #define AMDGPU_INFO_FW_GFX_CE 0x06
444 /* Subquery id: Query GFX RLC firmware version */
445 #define AMDGPU_INFO_FW_GFX_RLC 0x07
446 /* Subquery id: Query GFX MEC firmware version */
447 #define AMDGPU_INFO_FW_GFX_MEC 0x08
448 /* Subquery id: Query SMC firmware version */
449 #define AMDGPU_INFO_FW_SMC 0x0a
450 /* Subquery id: Query SDMA firmware version */
451 #define AMDGPU_INFO_FW_SDMA 0x0b
452/* number of bytes moved for TTM migration */
453#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
454/* the used VRAM size */
455#define AMDGPU_INFO_VRAM_USAGE 0x10
456/* the used GTT size */
457#define AMDGPU_INFO_GTT_USAGE 0x11
458/* Information about GDS, etc. resource configuration */
459#define AMDGPU_INFO_GDS_CONFIG 0x13
460/* Query information about VRAM and GTT domains */
461#define AMDGPU_INFO_VRAM_GTT 0x14
462/* Query information about register in MMR address space*/
463#define AMDGPU_INFO_READ_MMR_REG 0x15
464/* Query information about device: rev id, family, etc. */
465#define AMDGPU_INFO_DEV_INFO 0x16
466/* visible vram usage */
467#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
468
469#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
470#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
471#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
472#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
473
474/* Input structure for the INFO ioctl */
475struct drm_amdgpu_info {
476 /* Where the return value will be stored */
477 uint64_t return_pointer;
478 /* The size of the return value. Just like "size" in "snprintf",
479 * it limits how many bytes the kernel can write. */
480 uint32_t return_size;
481 /* The query request id. */
482 uint32_t query;
483
484 union {
485 struct {
486 uint32_t id;
487 uint32_t _pad;
488 } mode_crtc;
489
490 struct {
491 /** AMDGPU_HW_IP_* */
492 uint32_t type;
493 /**
494 * Index of the IP if there are more IPs of the same
495 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
496 */
497 uint32_t ip_instance;
498 } query_hw_ip;
499
500 struct {
501 uint32_t dword_offset;
502 /** number of registers to read */
503 uint32_t count;
504 uint32_t instance;
505 /** For future use, no flags defined so far */
506 uint32_t flags;
507 } read_mmr_reg;
508
509 struct {
510 /** AMDGPU_INFO_FW_* */
511 uint32_t fw_type;
512 /**
513 * Index of the IP if there are more IPs of
514 * the same type.
515 */
516 uint32_t ip_instance;
517 /**
518 * Index of the engine. Whether this is used depends
519 * on the firmware type. (e.g. MEC, SDMA)
520 */
521 uint32_t index;
522 uint32_t _pad;
523 } query_fw;
524 };
525};
526
527struct drm_amdgpu_info_gds {
528 /** GDS GFX partition size */
529 uint32_t gds_gfx_partition_size;
530 /** GDS compute partition size */
531 uint32_t compute_partition_size;
532 /** total GDS memory size */
533 uint32_t gds_total_size;
534 /** GWS size per GFX partition */
535 uint32_t gws_per_gfx_partition;
536 /** GSW size per compute partition */
537 uint32_t gws_per_compute_partition;
538 /** OA size per GFX partition */
539 uint32_t oa_per_gfx_partition;
540 /** OA size per compute partition */
541 uint32_t oa_per_compute_partition;
542 uint32_t _pad;
543};
544
545struct drm_amdgpu_info_vram_gtt {
546 uint64_t vram_size;
547 uint64_t vram_cpu_accessible_size;
548 uint64_t gtt_size;
549};
550
551struct drm_amdgpu_info_firmware {
552 uint32_t ver;
553 uint32_t feature;
554};
555
556#define AMDGPU_VRAM_TYPE_UNKNOWN 0
557#define AMDGPU_VRAM_TYPE_GDDR1 1
558#define AMDGPU_VRAM_TYPE_DDR2 2
559#define AMDGPU_VRAM_TYPE_GDDR3 3
560#define AMDGPU_VRAM_TYPE_GDDR4 4
561#define AMDGPU_VRAM_TYPE_GDDR5 5
562#define AMDGPU_VRAM_TYPE_HBM 6
563#define AMDGPU_VRAM_TYPE_DDR3 7
564
565struct drm_amdgpu_info_device {
566 /** PCI Device ID */
567 uint32_t device_id;
568 /** Internal chip revision: A0, A1, etc.) */
569 uint32_t chip_rev;
570 uint32_t external_rev;
571 /** Revision id in PCI Config space */
572 uint32_t pci_rev;
573 uint32_t family;
574 uint32_t num_shader_engines;
575 uint32_t num_shader_arrays_per_engine;
576 /* in KHz */
577 uint32_t gpu_counter_freq;
578 uint64_t max_engine_clock;
579 uint64_t max_memory_clock;
580 /* cu information */
581 uint32_t cu_active_number;
582 uint32_t cu_ao_mask;
583 uint32_t cu_bitmap[4][4];
584 /** Render backend pipe mask. One render backend is CB+DB. */
585 uint32_t enabled_rb_pipes_mask;
586 uint32_t num_rb_pipes;
587 uint32_t num_hw_gfx_contexts;
588 uint32_t _pad;
589 uint64_t ids_flags;
590 /** Starting virtual address for UMDs. */
591 uint64_t virtual_address_offset;
592 /** The maximum virtual address */
593 uint64_t virtual_address_max;
594 /** Required alignment of virtual addresses. */
595 uint32_t virtual_address_alignment;
596 /** Page table entry - fragment size */
597 uint32_t pte_fragment_size;
598 uint32_t gart_page_size;
599 /** constant engine ram size*/
600 uint32_t ce_ram_size;
601 /** video memory type info*/
602 uint32_t vram_type;
603 /** video memory bit width*/
604 uint32_t vram_bit_width;
605};
606
607struct drm_amdgpu_info_hw_ip {
608 /** Version of h/w IP */
609 uint32_t hw_ip_version_major;
610 uint32_t hw_ip_version_minor;
611 /** Capabilities */
612 uint64_t capabilities_flags;
613 /** command buffer address start alignment*/
614 uint32_t ib_start_alignment;
615 /** command buffer size alignment*/
616 uint32_t ib_size_alignment;
617 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
618 uint32_t available_rings;
619 uint32_t _pad;
620};
621
622/*
623 * Supported GPU families
624 */
625#define AMDGPU_FAMILY_UNKNOWN 0
626#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
627#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
628#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
629#define AMDGPU_FAMILY_CZ 135 /* Carrizo */
630
631#endif
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index ff6ef62d084b..3801584a0c53 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -786,6 +786,8 @@ struct drm_prime_handle {
786#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 786#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
787#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 787#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
788#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 788#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
789#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
790#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
789 791
790/** 792/**
791 * Device specific ioctls should only be in their respective headers 793 * Device specific ioctls should only be in their respective headers
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 07735822a28f..2f295cde657e 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -207,4 +207,19 @@
207 */ 207 */
208#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 208#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
209 209
210/*
211 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
212 *
213 * Macroblocks are laid in a Z-shape, and each pixel data is following the
214 * standard NV12 style.
215 * As for NV12, an image is the result of two frame buffers: one for Y,
216 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
217 * Alignment requirements are (for each buffer):
218 * - multiple of 128 pixels for the width
219 * - multiple of 32 pixels for the height
220 *
221 * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html
222 */
223#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
224
210#endif /* DRM_FOURCC_H */ 225#endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index dbeba949462a..359107ab629e 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -558,4 +558,24 @@ struct drm_mode_atomic {
558 __u64 user_data; 558 __u64 user_data;
559}; 559};
560 560
561/**
562 * Create a new 'blob' data property, copying length bytes from data pointer,
563 * and returning new blob ID.
564 */
565struct drm_mode_create_blob {
566 /** Pointer to data to copy. */
567 __u64 data;
568 /** Length of data to copy. */
569 __u32 length;
570 /** Return: new property ID. */
571 __u32 blob_id;
572};
573
574/**
575 * Destroy a user-created blob property.
576 */
577struct drm_mode_destroy_blob {
578 __u32 blob_id;
579};
580
561#endif 581#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 551b6737f5df..6e1a2ed116cb 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -171,8 +171,12 @@ typedef struct _drm_i915_sarea {
171#define I915_BOX_TEXTURE_LOAD 0x8 171#define I915_BOX_TEXTURE_LOAD 0x8
172#define I915_BOX_LOST_CONTEXT 0x10 172#define I915_BOX_LOST_CONTEXT 0x10
173 173
174/* I915 specific ioctls 174/*
175 * The device specific ioctl range is 0x40 to 0x79. 175 * i915 specific ioctls.
176 *
177 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
178 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
179 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
176 */ 180 */
177#define DRM_I915_INIT 0x00 181#define DRM_I915_INIT 0x00
178#define DRM_I915_FLUSH 0x01 182#define DRM_I915_FLUSH 0x01
@@ -996,6 +1000,7 @@ struct drm_intel_overlay_put_image {
996/* flags */ 1000/* flags */
997#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1001#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
998#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1002#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1003#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
999struct drm_intel_overlay_attrs { 1004struct drm_intel_overlay_attrs {
1000 __u32 flags; 1005 __u32 flags;
1001 __u32 color_key; 1006 __u32 color_key;
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 0664c31f010c..75a232b9a970 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -23,7 +23,7 @@
23 23
24/* Please note that modifications to all structs defined here are 24/* Please note that modifications to all structs defined here are
25 * subject to backwards-compatibility constraints: 25 * subject to backwards-compatibility constraints:
26 * 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit 26 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
27 * user/kernel compatibility 27 * user/kernel compatibility
28 * 2) Keep fields aligned to their size 28 * 2) Keep fields aligned to their size
29 * 3) Because of how drm_ioctl() works, we can add new fields at 29 * 3) Because of how drm_ioctl() works, we can add new fields at
@@ -44,8 +44,8 @@
44 * same as 'struct timespec' but 32/64b ABI safe. 44 * same as 'struct timespec' but 32/64b ABI safe.
45 */ 45 */
46struct drm_msm_timespec { 46struct drm_msm_timespec {
47 int64_t tv_sec; /* seconds */ 47 __s64 tv_sec; /* seconds */
48 int64_t tv_nsec; /* nanoseconds */ 48 __s64 tv_nsec; /* nanoseconds */
49}; 49};
50 50
51#define MSM_PARAM_GPU_ID 0x01 51#define MSM_PARAM_GPU_ID 0x01
@@ -53,9 +53,9 @@ struct drm_msm_timespec {
53#define MSM_PARAM_CHIP_ID 0x03 53#define MSM_PARAM_CHIP_ID 0x03
54 54
55struct drm_msm_param { 55struct drm_msm_param {
56 uint32_t pipe; /* in, MSM_PIPE_x */ 56 __u32 pipe; /* in, MSM_PIPE_x */
57 uint32_t param; /* in, MSM_PARAM_x */ 57 __u32 param; /* in, MSM_PARAM_x */
58 uint64_t value; /* out (get_param) or in (set_param) */ 58 __u64 value; /* out (get_param) or in (set_param) */
59}; 59};
60 60
61/* 61/*
@@ -77,15 +77,15 @@ struct drm_msm_param {
77 MSM_BO_UNCACHED) 77 MSM_BO_UNCACHED)
78 78
79struct drm_msm_gem_new { 79struct drm_msm_gem_new {
80 uint64_t size; /* in */ 80 __u64 size; /* in */
81 uint32_t flags; /* in, mask of MSM_BO_x */ 81 __u32 flags; /* in, mask of MSM_BO_x */
82 uint32_t handle; /* out */ 82 __u32 handle; /* out */
83}; 83};
84 84
85struct drm_msm_gem_info { 85struct drm_msm_gem_info {
86 uint32_t handle; /* in */ 86 __u32 handle; /* in */
87 uint32_t pad; 87 __u32 pad;
88 uint64_t offset; /* out, offset to pass to mmap() */ 88 __u64 offset; /* out, offset to pass to mmap() */
89}; 89};
90 90
91#define MSM_PREP_READ 0x01 91#define MSM_PREP_READ 0x01
@@ -95,13 +95,13 @@ struct drm_msm_gem_info {
95#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 95#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
96 96
97struct drm_msm_gem_cpu_prep { 97struct drm_msm_gem_cpu_prep {
98 uint32_t handle; /* in */ 98 __u32 handle; /* in */
99 uint32_t op; /* in, mask of MSM_PREP_x */ 99 __u32 op; /* in, mask of MSM_PREP_x */
100 struct drm_msm_timespec timeout; /* in */ 100 struct drm_msm_timespec timeout; /* in */
101}; 101};
102 102
103struct drm_msm_gem_cpu_fini { 103struct drm_msm_gem_cpu_fini {
104 uint32_t handle; /* in */ 104 __u32 handle; /* in */
105}; 105};
106 106
107/* 107/*
@@ -120,11 +120,11 @@ struct drm_msm_gem_cpu_fini {
120 * otherwise EINVAL. 120 * otherwise EINVAL.
121 */ 121 */
122struct drm_msm_gem_submit_reloc { 122struct drm_msm_gem_submit_reloc {
123 uint32_t submit_offset; /* in, offset from submit_bo */ 123 __u32 submit_offset; /* in, offset from submit_bo */
124 uint32_t or; /* in, value OR'd with result */ 124 __u32 or; /* in, value OR'd with result */
125 int32_t shift; /* in, amount of left shift (can be negative) */ 125 __s32 shift; /* in, amount of left shift (can be negative) */
126 uint32_t reloc_idx; /* in, index of reloc_bo buffer */ 126 __u32 reloc_idx; /* in, index of reloc_bo buffer */
127 uint64_t reloc_offset; /* in, offset from start of reloc_bo */ 127 __u64 reloc_offset; /* in, offset from start of reloc_bo */
128}; 128};
129 129
130/* submit-types: 130/* submit-types:
@@ -139,13 +139,13 @@ struct drm_msm_gem_submit_reloc {
139#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 139#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
140#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 140#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
141struct drm_msm_gem_submit_cmd { 141struct drm_msm_gem_submit_cmd {
142 uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */ 142 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
143 uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */ 143 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
144 uint32_t submit_offset; /* in, offset into submit_bo */ 144 __u32 submit_offset; /* in, offset into submit_bo */
145 uint32_t size; /* in, cmdstream size */ 145 __u32 size; /* in, cmdstream size */
146 uint32_t pad; 146 __u32 pad;
147 uint32_t nr_relocs; /* in, number of submit_reloc's */ 147 __u32 nr_relocs; /* in, number of submit_reloc's */
148 uint64_t __user relocs; /* in, ptr to array of submit_reloc's */ 148 __u64 __user relocs; /* in, ptr to array of submit_reloc's */
149}; 149};
150 150
151/* Each buffer referenced elsewhere in the cmdstream submit (ie. the 151/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
@@ -165,9 +165,9 @@ struct drm_msm_gem_submit_cmd {
165#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 165#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
166 166
167struct drm_msm_gem_submit_bo { 167struct drm_msm_gem_submit_bo {
168 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */ 168 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
169 uint32_t handle; /* in, GEM handle */ 169 __u32 handle; /* in, GEM handle */
170 uint64_t presumed; /* in/out, presumed buffer address */ 170 __u64 presumed; /* in/out, presumed buffer address */
171}; 171};
172 172
173/* Each cmdstream submit consists of a table of buffers involved, and 173/* Each cmdstream submit consists of a table of buffers involved, and
@@ -175,12 +175,12 @@ struct drm_msm_gem_submit_bo {
175 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 175 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
176 */ 176 */
177struct drm_msm_gem_submit { 177struct drm_msm_gem_submit {
178 uint32_t pipe; /* in, MSM_PIPE_x */ 178 __u32 pipe; /* in, MSM_PIPE_x */
179 uint32_t fence; /* out */ 179 __u32 fence; /* out */
180 uint32_t nr_bos; /* in, number of submit_bo's */ 180 __u32 nr_bos; /* in, number of submit_bo's */
181 uint32_t nr_cmds; /* in, number of submit_cmd's */ 181 __u32 nr_cmds; /* in, number of submit_cmd's */
182 uint64_t __user bos; /* in, ptr to array of submit_bo's */ 182 __u64 __user bos; /* in, ptr to array of submit_bo's */
183 uint64_t __user cmds; /* in, ptr to array of submit_cmd's */ 183 __u64 __user cmds; /* in, ptr to array of submit_cmd's */
184}; 184};
185 185
186/* The normal way to synchronize with the GPU is just to CPU_PREP on 186/* The normal way to synchronize with the GPU is just to CPU_PREP on
@@ -191,8 +191,8 @@ struct drm_msm_gem_submit {
191 * APIs without requiring a dummy bo to synchronize on. 191 * APIs without requiring a dummy bo to synchronize on.
192 */ 192 */
193struct drm_msm_wait_fence { 193struct drm_msm_wait_fence {
194 uint32_t fence; /* in */ 194 __u32 fence; /* in */
195 uint32_t pad; 195 __u32 pad;
196 struct drm_msm_timespec timeout; /* in */ 196 struct drm_msm_timespec timeout; /* in */
197}; 197};
198 198
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 94d44ab2fda1..1ef76661e1a1 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -1039,6 +1039,7 @@ struct drm_radeon_cs {
1039#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 1039#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
1040#define RADEON_INFO_READ_REG 0x24 1040#define RADEON_INFO_READ_REG 0x24
1041#define RADEON_INFO_VA_UNMAP_WORKING 0x25 1041#define RADEON_INFO_VA_UNMAP_WORKING 0x25
1042#define RADEON_INFO_GPU_RESET_COUNTER 0x26
1042 1043
1043struct drm_radeon_info { 1044struct drm_radeon_info {
1044 uint32_t request; 1045 uint32_t request;
diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
index 1a0006a76b00..4460e5820b0e 100644
--- a/include/uapi/linux/Kbuild
+++ b/include/uapi/linux/Kbuild
@@ -430,6 +430,7 @@ header-y += virtio_balloon.h
430header-y += virtio_blk.h 430header-y += virtio_blk.h
431header-y += virtio_config.h 431header-y += virtio_config.h
432header-y += virtio_console.h 432header-y += virtio_console.h
433header-y += virtio_gpu.h
433header-y += virtio_ids.h 434header-y += virtio_ids.h
434header-y += virtio_input.h 435header-y += virtio_input.h
435header-y += virtio_net.h 436header-y += virtio_net.h
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index af94f31e33ac..d6833426fdef 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -27,7 +27,7 @@
27#include <linux/ioctl.h> 27#include <linux/ioctl.h>
28 28
29#define KFD_IOCTL_MAJOR_VERSION 1 29#define KFD_IOCTL_MAJOR_VERSION 1
30#define KFD_IOCTL_MINOR_VERSION 0 30#define KFD_IOCTL_MINOR_VERSION 1
31 31
32struct kfd_ioctl_get_version_args { 32struct kfd_ioctl_get_version_args {
33 uint32_t major_version; /* from KFD */ 33 uint32_t major_version; /* from KFD */
@@ -128,6 +128,110 @@ struct kfd_ioctl_get_process_apertures_args {
128 uint32_t pad; 128 uint32_t pad;
129}; 129};
130 130
131#define MAX_ALLOWED_NUM_POINTS 100
132#define MAX_ALLOWED_AW_BUFF_SIZE 4096
133#define MAX_ALLOWED_WAC_BUFF_SIZE 128
134
135struct kfd_ioctl_dbg_register_args {
136 uint32_t gpu_id; /* to KFD */
137 uint32_t pad;
138};
139
140struct kfd_ioctl_dbg_unregister_args {
141 uint32_t gpu_id; /* to KFD */
142 uint32_t pad;
143};
144
145struct kfd_ioctl_dbg_address_watch_args {
146 uint64_t content_ptr; /* a pointer to the actual content */
147 uint32_t gpu_id; /* to KFD */
148 uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
149};
150
151struct kfd_ioctl_dbg_wave_control_args {
152 uint64_t content_ptr; /* a pointer to the actual content */
153 uint32_t gpu_id; /* to KFD */
154 uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
155};
156
157/* Matching HSA_EVENTTYPE */
158#define KFD_IOC_EVENT_SIGNAL 0
159#define KFD_IOC_EVENT_NODECHANGE 1
160#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
161#define KFD_IOC_EVENT_HW_EXCEPTION 3
162#define KFD_IOC_EVENT_SYSTEM_EVENT 4
163#define KFD_IOC_EVENT_DEBUG_EVENT 5
164#define KFD_IOC_EVENT_PROFILE_EVENT 6
165#define KFD_IOC_EVENT_QUEUE_EVENT 7
166#define KFD_IOC_EVENT_MEMORY 8
167
168#define KFD_IOC_WAIT_RESULT_COMPLETE 0
169#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
170#define KFD_IOC_WAIT_RESULT_FAIL 2
171
172#define KFD_SIGNAL_EVENT_LIMIT 256
173
174struct kfd_ioctl_create_event_args {
175 uint64_t event_page_offset; /* from KFD */
176 uint32_t event_trigger_data; /* from KFD - signal events only */
177 uint32_t event_type; /* to KFD */
178 uint32_t auto_reset; /* to KFD */
179 uint32_t node_id; /* to KFD - only valid for certain
180 event types */
181 uint32_t event_id; /* from KFD */
182 uint32_t event_slot_index; /* from KFD */
183};
184
185struct kfd_ioctl_destroy_event_args {
186 uint32_t event_id; /* to KFD */
187 uint32_t pad;
188};
189
190struct kfd_ioctl_set_event_args {
191 uint32_t event_id; /* to KFD */
192 uint32_t pad;
193};
194
195struct kfd_ioctl_reset_event_args {
196 uint32_t event_id; /* to KFD */
197 uint32_t pad;
198};
199
200struct kfd_memory_exception_failure {
201 uint32_t NotPresent; /* Page not present or supervisor privilege */
202 uint32_t ReadOnly; /* Write access to a read-only page */
203 uint32_t NoExecute; /* Execute access to a page marked NX */
204 uint32_t pad;
205};
206
207/* memory exception data*/
208struct kfd_hsa_memory_exception_data {
209 struct kfd_memory_exception_failure failure;
210 uint64_t va;
211 uint32_t gpu_id;
212 uint32_t pad;
213};
214
215/* Event data*/
216struct kfd_event_data {
217 union {
218 struct kfd_hsa_memory_exception_data memory_exception_data;
219 }; /* From KFD */
220 uint64_t kfd_event_data_ext; /* pointer to an extension structure
221 for future exception types */
222 uint32_t event_id; /* to KFD */
223 uint32_t pad;
224};
225
226struct kfd_ioctl_wait_events_args {
227 uint64_t events_ptr; /* pointed to struct
228 kfd_event_data array, to KFD */
229 uint32_t num_events; /* to KFD */
230 uint32_t wait_for_all; /* to KFD */
231 uint32_t timeout; /* to KFD */
232 uint32_t wait_result; /* from KFD */
233};
234
131#define AMDKFD_IOCTL_BASE 'K' 235#define AMDKFD_IOCTL_BASE 'K'
132#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 236#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
133#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 237#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
@@ -155,7 +259,34 @@ struct kfd_ioctl_get_process_apertures_args {
155#define AMDKFD_IOC_UPDATE_QUEUE \ 259#define AMDKFD_IOC_UPDATE_QUEUE \
156 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 260 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
157 261
262#define AMDKFD_IOC_CREATE_EVENT \
263 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
264
265#define AMDKFD_IOC_DESTROY_EVENT \
266 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
267
268#define AMDKFD_IOC_SET_EVENT \
269 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
270
271#define AMDKFD_IOC_RESET_EVENT \
272 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
273
274#define AMDKFD_IOC_WAIT_EVENTS \
275 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
276
277#define AMDKFD_IOC_DBG_REGISTER \
278 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
279
280#define AMDKFD_IOC_DBG_UNREGISTER \
281 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
282
283#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
284 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
285
286#define AMDKFD_IOC_DBG_WAVE_CONTROL \
287 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
288
158#define AMDKFD_COMMAND_START 0x01 289#define AMDKFD_COMMAND_START 0x01
159#define AMDKFD_COMMAND_END 0x08 290#define AMDKFD_COMMAND_END 0x11
160 291
161#endif 292#endif
diff --git a/include/uapi/linux/virtio_gpu.h b/include/uapi/linux/virtio_gpu.h
new file mode 100644
index 000000000000..478be5270e26
--- /dev/null
+++ b/include/uapi/linux/virtio_gpu.h
@@ -0,0 +1,206 @@
1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include <linux/types.h>
42
43enum virtio_gpu_ctrl_type {
44 VIRTIO_GPU_UNDEFINED = 0,
45
46 /* 2d commands */
47 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
48 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
49 VIRTIO_GPU_CMD_RESOURCE_UNREF,
50 VIRTIO_GPU_CMD_SET_SCANOUT,
51 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
52 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
53 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
54 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
55
56 /* cursor commands */
57 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
58 VIRTIO_GPU_CMD_MOVE_CURSOR,
59
60 /* success responses */
61 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
62 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
63
64 /* error responses */
65 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
66 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
67 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
68 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
69 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
70 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
71};
72
73#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
74
75struct virtio_gpu_ctrl_hdr {
76 __le32 type;
77 __le32 flags;
78 __le64 fence_id;
79 __le32 ctx_id;
80 __le32 padding;
81};
82
83/* data passed in the cursor vq */
84
85struct virtio_gpu_cursor_pos {
86 __le32 scanout_id;
87 __le32 x;
88 __le32 y;
89 __le32 padding;
90};
91
92/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
93struct virtio_gpu_update_cursor {
94 struct virtio_gpu_ctrl_hdr hdr;
95 struct virtio_gpu_cursor_pos pos; /* update & move */
96 __le32 resource_id; /* update only */
97 __le32 hot_x; /* update only */
98 __le32 hot_y; /* update only */
99 __le32 padding;
100};
101
102/* data passed in the control vq, 2d related */
103
104struct virtio_gpu_rect {
105 __le32 x;
106 __le32 y;
107 __le32 width;
108 __le32 height;
109};
110
111/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
112struct virtio_gpu_resource_unref {
113 struct virtio_gpu_ctrl_hdr hdr;
114 __le32 resource_id;
115 __le32 padding;
116};
117
118/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
119struct virtio_gpu_resource_create_2d {
120 struct virtio_gpu_ctrl_hdr hdr;
121 __le32 resource_id;
122 __le32 format;
123 __le32 width;
124 __le32 height;
125};
126
127/* VIRTIO_GPU_CMD_SET_SCANOUT */
128struct virtio_gpu_set_scanout {
129 struct virtio_gpu_ctrl_hdr hdr;
130 struct virtio_gpu_rect r;
131 __le32 scanout_id;
132 __le32 resource_id;
133};
134
135/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
136struct virtio_gpu_resource_flush {
137 struct virtio_gpu_ctrl_hdr hdr;
138 struct virtio_gpu_rect r;
139 __le32 resource_id;
140 __le32 padding;
141};
142
143/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
144struct virtio_gpu_transfer_to_host_2d {
145 struct virtio_gpu_ctrl_hdr hdr;
146 struct virtio_gpu_rect r;
147 __le64 offset;
148 __le32 resource_id;
149 __le32 padding;
150};
151
152struct virtio_gpu_mem_entry {
153 __le64 addr;
154 __le32 length;
155 __le32 padding;
156};
157
158/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
159struct virtio_gpu_resource_attach_backing {
160 struct virtio_gpu_ctrl_hdr hdr;
161 __le32 resource_id;
162 __le32 nr_entries;
163};
164
165/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
166struct virtio_gpu_resource_detach_backing {
167 struct virtio_gpu_ctrl_hdr hdr;
168 __le32 resource_id;
169 __le32 padding;
170};
171
172/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
173#define VIRTIO_GPU_MAX_SCANOUTS 16
174struct virtio_gpu_resp_display_info {
175 struct virtio_gpu_ctrl_hdr hdr;
176 struct virtio_gpu_display_one {
177 struct virtio_gpu_rect r;
178 __le32 enabled;
179 __le32 flags;
180 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
181};
182
183#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
184
185struct virtio_gpu_config {
186 __u32 events_read;
187 __u32 events_clear;
188 __u32 num_scanouts;
189 __u32 reserved;
190};
191
192/* simple formats for fbcon/X use */
193enum virtio_gpu_formats {
194 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
195 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
196 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
197 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
198
199 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
200 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
201
202 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
203 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
204};
205
206#endif
diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_ids.h
index 5f60aa4be50a..77925f587b15 100644
--- a/include/uapi/linux/virtio_ids.h
+++ b/include/uapi/linux/virtio_ids.h
@@ -39,6 +39,7 @@
39#define VIRTIO_ID_9P 9 /* 9p virtio console */ 39#define VIRTIO_ID_9P 9 /* 9p virtio console */
40#define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */ 40#define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */
41#define VIRTIO_ID_CAIF 12 /* Virtio caif */ 41#define VIRTIO_ID_CAIF 12 /* Virtio caif */
42#define VIRTIO_ID_GPU 16 /* virtio GPU */
42#define VIRTIO_ID_INPUT 18 /* virtio input */ 43#define VIRTIO_ID_INPUT 18 /* virtio input */
43 44
44#endif /* _LINUX_VIRTIO_IDS_H */ 45#endif /* _LINUX_VIRTIO_IDS_H */
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
new file mode 100644
index 000000000000..3696575b02f2
--- /dev/null
+++ b/include/video/exynos5433_decon.h
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2014 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundationr
7 */
8
9#ifndef EXYNOS_REGS_DECON_H
10#define EXYNOS_REGS_DECON_H
11
12/* Exynos543X DECON */
13#define DECON_VIDCON0 0x0000
14#define DECON_VIDOUTCON0 0x0010
15#define DECON_WINCONx(n) (0x0020 + ((n) * 4))
16#define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
17#define DECON_SHADOWCON 0x00A0
18#define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
19#define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
20#define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
21#define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
22#define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
23#define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10))
24#define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10))
25#define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10))
26#define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10))
27#define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10))
28#define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10))
29#define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4))
30#define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4))
31#define DECON_VIDINTCON0 0x0220
32#define DECON_VIDINTCON1 0x0224
33#define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8))
34#define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8))
35#define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4))
36#define DECON_WINxMAP(n) (0x0270 + ((n) * 4))
37#define DECON_QOSLUT07_00 0x02C0
38#define DECON_QOSLUT15_08 0x02C4
39#define DECON_QOSCTRL 0x02C8
40#define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4))
41#define DECON_BLENDCON 0x0310
42#define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4))
43#define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4))
44#define DECON_FRAMEFIFO_REG7 0x051C
45#define DECON_FRAMEFIFO_REG8 0x0520
46#define DECON_FRAMEFIFO_STATUS 0x0524
47#define DECON_CMU 0x1404
48#define DECON_UPDATE 0x1410
49#define DECON_UPDATE_SCHEME 0x1438
50#define DECON_VIDCON1 0x2000
51#define DECON_VIDCON2 0x2004
52#define DECON_VIDCON3 0x2008
53#define DECON_VIDCON4 0x200C
54#define DECON_VIDTCON2 0x2028
55#define DECON_FRAME_SIZE 0x2038
56#define DECON_LINECNT_OP_THRESHOLD 0x203C
57#define DECON_TRIGCON 0x2040
58#define DECON_TRIGSKIP 0x2050
59#define DECON_CRCRDATA 0x20B0
60#define DECON_CRCCTRL 0x20B4
61
62/* Exynos5430 DECON */
63#define DECON_VIDTCON0 0x2020
64#define DECON_VIDTCON1 0x2024
65
66/* Exynos5433 DECON */
67#define DECON_VIDTCON00 0x2010
68#define DECON_VIDTCON01 0x2014
69#define DECON_VIDTCON10 0x2018
70#define DECON_VIDTCON11 0x201C
71
72/* Exynos543X DECON Internal */
73#define DECON_W013DSTREOCON 0x0320
74#define DECON_W233DSTREOCON 0x0324
75#define DECON_FRAMEFIFO_REG0 0x0500
76#define DECON_ENHANCER_CTRL 0x2100
77
78/* Exynos543X DECON TV */
79#define DECON_VCLKCON0 0x0014
80#define DECON_VIDINTCON2 0x0228
81#define DECON_VIDINTCON3 0x022C
82
83/* VIDCON0 */
84#define VIDCON0_SWRESET (1 << 28)
85#define VIDCON0_STOP_STATUS (1 << 2)
86#define VIDCON0_ENVID (1 << 1)
87#define VIDCON0_ENVID_F (1 << 0)
88
89/* VIDOUTCON0 */
90#define VIDOUT_LCD_ON (1 << 24)
91#define VIDOUT_IF_F_MASK (0x3 << 20)
92#define VIDOUT_RGB_IF (0x0 << 20)
93#define VIDOUT_COMMAND_IF (0x2 << 20)
94
95/* WINCONx */
96#define WINCONx_HAWSWP_F (1 << 16)
97#define WINCONx_WSWP_F (1 << 15)
98#define WINCONx_BURSTLEN_MASK (0x3 << 10)
99#define WINCONx_BURSTLEN_16WORD (0x0 << 10)
100#define WINCONx_BURSTLEN_8WORD (0x1 << 10)
101#define WINCONx_BURSTLEN_4WORD (0x2 << 10)
102#define WINCONx_BLD_PIX_F (1 << 6)
103#define WINCONx_BPPMODE_MASK (0xf << 2)
104#define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
105#define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
106#define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
107#define WINCONx_BPPMODE_24BPP_888 (0xb << 2)
108#define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
109#define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
110#define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
111#define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
112#define WINCONx_ALPHA_SEL_F (1 << 1)
113#define WINCONx_ENWIN_F (1 << 0)
114
115/* SHADOWCON */
116#define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
117
118/* VIDOSDxD */
119#define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
120#define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
121#define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0)
122
123/* VIDINTCON0 */
124#define VIDINTCON0_FRAMEDONE (1 << 17)
125#define VIDINTCON0_INTFRMEN (1 << 12)
126#define VIDINTCON0_INTEN (1 << 0)
127
128/* VIDINTCON1 */
129#define VIDINTCON1_INTFRMDONEPEND (1 << 2)
130#define VIDINTCON1_INTFRMPEND (1 << 1)
131#define VIDINTCON1_INTFIFOPEND (1 << 0)
132
133/* DECON_CMU */
134#define CMU_CLKGAGE_MODE_SFR_F (1 << 1)
135#define CMU_CLKGAGE_MODE_MEM_F (1 << 0)
136
137/* DECON_UPDATE */
138#define STANDALONE_UPDATE_F (1 << 0)
139
140/* DECON_VIDTCON00 */
141#define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16)
142#define VIDTCON00_VFPD_F(x) ((x) & 0xfff)
143
144/* DECON_VIDTCON01 */
145#define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16)
146
147/* DECON_VIDTCON10 */
148#define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16)
149#define VIDTCON10_HFPD_F(x) ((x) & 0xfff)
150
151/* DECON_VIDTCON11 */
152#define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16)
153
154/* DECON_VIDTCON2 */
155#define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16)
156#define VIDTCON2_HOZVAL(x) ((x) & 0xfff)
157
158/* TRIGCON */
159#define TRIGCON_TRIGEN_PER_F (1 << 31)
160#define TRIGCON_TRIGEN_F (1 << 30)
161#define TRIGCON_TE_AUTO_MASK (1 << 29)
162#define TRIGCON_SWTRIGCMD (1 << 1)
163#define TRIGCON_SWTRIGEN (1 << 0)
164
165#endif /* EXYNOS_REGS_DECON_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-23 16:31:29 -0400