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authorLinus Torvalds <torvalds@linux-foundation.org>2017-02-23 21:58:18 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-02-23 21:58:18 -0500
commitef96152e6a36e0510387cb174178b7982c1ae879 (patch)
treef2b881feb97893dd6e73380fe206bbfd5110559e /include/uapi
parentd5500a074741b78b7f778b4ab3415d5ecdcda0a7 (diff)
parent64a577196d66b44e37384bc5c4d78c61f59d5b2a (diff)
Merge tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.11. Nothing too major, the tinydrm and mmu-less support should make writing smaller drivers easier for some of the simpler platforms, and there are a bunch of documentation updates. Intel grew displayport MST audio support which is hopefully useful to people, and FBC is on by default for GEN9+ (so people know where to look for regressions). AMDGPU has a lot of fixes that would like new firmware files installed for some GPUs. Other than that it's pretty scattered all over. I may have a follow up pull request as I know BenH has a bunch of AST rework and fixes and I'd like to get those in once they've been tested by AST, and I've got at least one pull request I'm just trying to get the author to fix up. Core: - drm_mm reworked - Connector list locking and iterators - Documentation updates - Format handling rework - MMU-less support for fbdev helpers - drm_crtc_from_index helper - Core CRC API - Remove drm_framebuffer_unregister_private - Debugfs cleanup - EDID/Infoframe fixes - Release callback - Tinydrm support (smaller drivers for simple hw) panel: - Add support for some new simple panels i915: - FBC by default for gen9+ - Shared dpll cleanups and docs - GEN8 powerdomain cleanup - DMC support on GLK - DP MST audio support - HuC loading support - GVT init ordering fixes - GVT IOMMU workaround fix amdgpu/radeon: - Power/clockgating improvements - Preliminary SR-IOV support - TTM buffer priority and eviction fixes - SI DPM quirks removed due to firmware fixes - Powerplay improvements - VCE/UVD powergating fixes - Cleanup SI GFX code to match CI/VI - Support for > 2 displays on 3/5 crtc asics - SI headless fixes nouveau: - Rework securre boot code in prep for GP10x secure boot - Channel recovery improvements - Initial power budget code - MMU rework preperation vmwgfx: - Bunch of fixes and cleanups exynos: - Runtime PM support for MIC driver - Cleanups to use atomic helpers - UHD Support for TM2/TM2E boards - Trigger mode fix for Rinato board etnaviv: - Shader performance fix - Command stream validator fixes - Command buffer suballocator rockchip: - CDN DisplayPort support - IOMMU support for arm64 platform imx-drm: - Fix i.MX5 TV encoder probing - Remove lower fb size limits msm: - Support for HW cursor on MDP5 devices - DSI encoder cleanup - GPU DT bindings cleanup sti: - stih410 cleanups - Create fbdev at binding - HQVDP fixes - Remove stih416 chip functionality - DVI/HDMI mode selection fixes - FPS statistic reporting omapdrm: - IRQ code cleanup dwi-hdmi bridge: - Cleanups and fixes adv-bridge: - Updates for nexus sii8520 bridge: - Add interlace mode support - Rework HDMI and lots of fixes qxl: - probing/teardown cleanups ZTE drm: - HDMI audio via SPDIF interface - Video Layer overlay plane support - Add TV encoder output device atmel-hlcdc: - Rework fbdev creation logic tegra: - OF node fix fsl-dcu: - Minor fixes mali-dp: - Assorted fixes sunxi: - Minor fix" [ This was the "fixed" pull, that still had build warnings due to people not even having build tested the result. I'm not a happy camper I've fixed the things I noticed up in this merge. - Linus ] * tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux: (1177 commits) lib/Kconfig: make PRIME_NUMBERS not user selectable drm/tinydrm: helpers: Properly fix backlight dependency drm/tinydrm: mipi-dbi: Fix field width specifier warning drm/tinydrm: mipi-dbi: Silence: ‘cmd’ may be used uninitialized drm/sti: fix build warnings in sti_drv.c and sti_vtg.c files drm/amd/powerplay: fix PSI feature on Polars12 drm/amdgpu: refuse to reserve io mem for split VRAM buffers drm/ttm: fix use-after-free races in vm fault handling drm/tinydrm: Add support for Multi-Inno MI0283QT display dt-bindings: Add Multi-Inno MI0283QT binding dt-bindings: display/panel: Add common rotation property of: Add vendor prefix for Multi-Inno drm/tinydrm: Add MIPI DBI support drm/tinydrm: Add helper functions drm: Add DRM support for tiny LCD displays drm/amd/amdgpu: post card if there is real hw resetting performed drm/nouveau/tmr: provide backtrace when a timeout is hit drm/nouveau/pci/g92: Fix rearm drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios drm/nouveau/hwmon: expose power_max and power_crit ..
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/drm/Kbuild1
-rw-r--r--include/uapi/drm/amdgpu_drm.h9
-rw-r--r--include/uapi/drm/drm_fourcc.h59
-rw-r--r--include/uapi/drm/i915_drm.h136
-rw-r--r--include/uapi/linux/Kbuild1
5 files changed, 206 insertions, 0 deletions
diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
index 9355dd8eff3b..c97addd08f8c 100644
--- a/include/uapi/drm/Kbuild
+++ b/include/uapi/drm/Kbuild
@@ -9,6 +9,7 @@ header-y += i810_drm.h
9header-y += i915_drm.h 9header-y += i915_drm.h
10header-y += mga_drm.h 10header-y += mga_drm.h
11header-y += nouveau_drm.h 11header-y += nouveau_drm.h
12header-y += omap_drm.h
12header-y += qxl_drm.h 13header-y += qxl_drm.h
13header-y += r128_drm.h 14header-y += r128_drm.h
14header-y += radeon_drm.h 15header-y += radeon_drm.h
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 396183628f3c..5797283c2d79 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -528,6 +528,8 @@ struct drm_amdgpu_cs_chunk_data {
528 #define AMDGPU_INFO_VBIOS_SIZE 0x1 528 #define AMDGPU_INFO_VBIOS_SIZE 0x1
529 /* Subquery id: Query vbios image */ 529 /* Subquery id: Query vbios image */
530 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 530 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
531/* Query UVD handles */
532#define AMDGPU_INFO_NUM_HANDLES 0x1C
531 533
532#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 534#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
533#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 535#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -719,6 +721,13 @@ struct drm_amdgpu_info_hw_ip {
719 __u32 _pad; 721 __u32 _pad;
720}; 722};
721 723
724struct drm_amdgpu_info_num_handles {
725 /** Max handles as supported by firmware for UVD */
726 __u32 uvd_max_handles;
727 /** Handles currently in use for UVD */
728 __u32 uvd_used_handles;
729};
730
722#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 731#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
723 732
724struct drm_amdgpu_info_vce_clock_table_entry { 733struct drm_amdgpu_info_vce_clock_table_entry {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index a5890bf44c0a..ef20abb8119b 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -41,10 +41,17 @@ extern "C" {
41/* 8 bpp Red */ 41/* 8 bpp Red */
42#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 42#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
43 43
44/* 16 bpp Red */
45#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
46
44/* 16 bpp RG */ 47/* 16 bpp RG */
45#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 48#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
46#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 49#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
47 50
51/* 32 bpp RG */
52#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
53#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
54
48/* 8 bpp RGB */ 55/* 8 bpp RGB */
49#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 56#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
50#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 57#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
@@ -154,11 +161,13 @@ extern "C" {
154 161
155/* Vendor Ids: */ 162/* Vendor Ids: */
156#define DRM_FORMAT_MOD_NONE 0 163#define DRM_FORMAT_MOD_NONE 0
164#define DRM_FORMAT_MOD_VENDOR_NONE 0
157#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 165#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
158#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 166#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
159#define DRM_FORMAT_MOD_VENDOR_NV 0x03 167#define DRM_FORMAT_MOD_VENDOR_NV 0x03
160#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 168#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
161#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 169#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
170#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
162/* add more to the end as needed */ 171/* add more to the end as needed */
163 172
164#define fourcc_mod_code(vendor, val) \ 173#define fourcc_mod_code(vendor, val) \
@@ -172,6 +181,16 @@ extern "C" {
172 * authoritative source for all of these. 181 * authoritative source for all of these.
173 */ 182 */
174 183
184/*
185 * Linear Layout
186 *
187 * Just plain linear layout. Note that this is different from no specifying any
188 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
189 * which tells the driver to also take driver-internal information into account
190 * and so might actually result in a tiled framebuffer.
191 */
192#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
193
175/* Intel framebuffer modifiers */ 194/* Intel framebuffer modifiers */
176 195
177/* 196/*
@@ -233,6 +252,46 @@ extern "C" {
233 */ 252 */
234#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 253#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
235 254
255/* Vivante framebuffer modifiers */
256
257/*
258 * Vivante 4x4 tiling layout
259 *
260 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
261 * layout.
262 */
263#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
264
265/*
266 * Vivante 64x64 super-tiling layout
267 *
268 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
269 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
270 * major layout.
271 *
272 * For more information: see
273 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
274 */
275#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
276
277/*
278 * Vivante 4x4 tiling layout for dual-pipe
279 *
280 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
281 * different base address. Offsets from the base addresses are therefore halved
282 * compared to the non-split tiled layout.
283 */
284#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
285
286/*
287 * Vivante 64x64 super-tiling layout for dual-pipe
288 *
289 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
290 * starts at a different base address. Offsets from the base addresses are
291 * therefore halved compared to the non-split super-tiled layout.
292 */
293#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
294
236#if defined(__cplusplus) 295#if defined(__cplusplus)
237} 296}
238#endif 297#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1c12a350eca3..57093b455db6 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -258,6 +258,7 @@ typedef struct _drm_i915_sarea {
258#define DRM_I915_GEM_USERPTR 0x33 258#define DRM_I915_GEM_USERPTR 0x33
259#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 259#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
260#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 260#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
261#define DRM_I915_PERF_OPEN 0x36
261 262
262#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 263#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
263#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 264#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -311,6 +312,7 @@ typedef struct _drm_i915_sarea {
311#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 312#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
312#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 313#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
313#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 314#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
315#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
314 316
315/* Allow drivers to submit batchbuffers directly to hardware, relying 317/* Allow drivers to submit batchbuffers directly to hardware, relying
316 * on the security mechanisms provided by hardware. 318 * on th