Merge tag 'v4.4-rc2' into drm-intel-next-queued

Linux 4.4-rc2

Backmerge to get at

commit 1b0e3a049efe471c399674fd954500ce97438d30
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Nov 5 23:04:11 2015 +0200

    drm/i915/skl: disable display side power well support for now

so that we can proplery re-eanble skl power wells in -next.

Conflicts are just adjacent lines changed, except for intel_fbdev.c
where we need to interleave the changs. Nothing nefarious.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 111 insertions, 1 deletions

diff --git a/include/uapi/linux/virtio_gpu.h b/include/uapi/linux/virtio_gpu.h
index 478be5270e26..7a63faa9065c 100644
--- a/include/uapi/linux/virtio_gpu.h
+++ b/include/uapi/linux/virtio_gpu.h
@@ -40,6 +40,8 @@
 
 #include <linux/types.h>
 
+#define VIRTIO_GPU_F_VIRGL 0
+
 enum virtio_gpu_ctrl_type {
         VIRTIO_GPU_UNDEFINED = 0,
 
@@ -52,6 +54,18 @@ enum virtio_gpu_ctrl_type {
         VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
         VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
         VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
+        VIRTIO_GPU_CMD_GET_CAPSET_INFO,
+        VIRTIO_GPU_CMD_GET_CAPSET,
+
+        /* 3d commands */
+        VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
+        VIRTIO_GPU_CMD_CTX_DESTROY,
+        VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
+        VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
+        VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
+        VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
+        VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
+        VIRTIO_GPU_CMD_SUBMIT_3D,
 
         /* cursor commands */
         VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
@@ -60,6 +74,8 @@ enum virtio_gpu_ctrl_type {
         /* success responses */
         VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
         VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
+        VIRTIO_GPU_RESP_OK_CAPSET_INFO,
+        VIRTIO_GPU_RESP_OK_CAPSET,
 
         /* error responses */
         VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
@@ -180,13 +196,107 @@ struct virtio_gpu_resp_display_info {
         } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
 };
 
+/* data passed in the control vq, 3d related */
+
+struct virtio_gpu_box {
+        __le32 x, y, z;
+        __le32 w, h, d;
+};
+
+/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
+struct virtio_gpu_transfer_host_3d {
+        struct virtio_gpu_ctrl_hdr hdr;
+        struct virtio_gpu_box box;
+        __le64 offset;
+        __le32 resource_id;
+        __le32 level;
+        __le32 stride;
+        __le32 layer_stride;
+};
+
+/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
+#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
+struct virtio_gpu_resource_create_3d {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 resource_id;
+        __le32 target;
+        __le32 format;
+        __le32 bind;
+        __le32 width;
+        __le32 height;
+        __le32 depth;
+        __le32 array_size;
+        __le32 last_level;
+        __le32 nr_samples;
+        __le32 flags;
+        __le32 padding;
+};
+
+/* VIRTIO_GPU_CMD_CTX_CREATE */
+struct virtio_gpu_ctx_create {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 nlen;
+        __le32 padding;
+        char debug_name[64];
+};
+
+/* VIRTIO_GPU_CMD_CTX_DESTROY */
+struct virtio_gpu_ctx_destroy {
+        struct virtio_gpu_ctrl_hdr hdr;
+};
+
+/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
+struct virtio_gpu_ctx_resource {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 resource_id;
+        __le32 padding;
+};
+
+/* VIRTIO_GPU_CMD_SUBMIT_3D */
+struct virtio_gpu_cmd_submit {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 size;
+        __le32 padding;
+};
+
+#define VIRTIO_GPU_CAPSET_VIRGL 1
+
+/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
+struct virtio_gpu_get_capset_info {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 capset_index;
+        __le32 padding;
+};
+
+/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
+struct virtio_gpu_resp_capset_info {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 capset_id;
+        __le32 capset_max_version;
+        __le32 capset_max_size;
+        __le32 padding;
+};
+
+/* VIRTIO_GPU_CMD_GET_CAPSET */
+struct virtio_gpu_get_capset {
+        struct virtio_gpu_ctrl_hdr hdr;
+        __le32 capset_id;
+        __le32 capset_version;
+};
+
+/* VIRTIO_GPU_RESP_OK_CAPSET */
+struct virtio_gpu_resp_capset {
+        struct virtio_gpu_ctrl_hdr hdr;
+        uint8_t capset_data[];
+};
+
 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
 
 struct virtio_gpu_config {
         __u32 events_read;
         __u32 events_clear;
         __u32 num_scanouts;
-        __u32 reserved;
+        __u32 num_capsets;
 };
 
 /* simple formats for fbcon/X use */