aboutsummaryrefslogtreecommitdiffstats
path: root/include/uapi/linux/fpga-dfl.h
diff options
context:
space:
mode:
authorWu Hao <hao.wu@intel.com>2018-06-29 20:53:32 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-07-15 07:55:47 -0400
commite4664c0ee4ac44993c62d10b048ab0a960691da5 (patch)
treef40f47fa0c5ddadc371ff4772479c9b4a8306149 /include/uapi/linux/fpga-dfl.h
parent47c1b19c160fe1641469c145dba78fbbe48b996a (diff)
fpga: dfl: afu: add header sub feature support
The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/id Read-only. Port ID. Ioctl interface: * DFL_FPGA_PORT_RESET Reset the FPGA Port and its AFU. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/fpga-dfl.h')
-rw-r--r--include/uapi/linux/fpga-dfl.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
index 9666af85a8f5..e6b4dd26cc68 100644
--- a/include/uapi/linux/fpga-dfl.h
+++ b/include/uapi/linux/fpga-dfl.h
@@ -29,8 +29,11 @@
29#define DFL_FPGA_MAGIC 0xB6 29#define DFL_FPGA_MAGIC 0xB6
30 30
31#define DFL_FPGA_BASE 0 31#define DFL_FPGA_BASE 0
32#define DFL_PORT_BASE 0x40
32#define DFL_FME_BASE 0x80 33#define DFL_FME_BASE 0x80
33 34
35/* Common IOCTLs for both FME and AFU file descriptor */
36
34/** 37/**
35 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) 38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
36 * 39 *
@@ -49,6 +52,20 @@
49 52
50#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) 53#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
51 54
55/* IOCTLs for AFU file descriptor */
56
57/**
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
59 *
60 * Reset the FPGA Port and its AFU. No parameters are supported.
61 * Userspace can do Port reset at any time, e.g. during DMA or PR. But
62 * it should never cause any system level issue, only functional failure
63 * (e.g. DMA or PR operation failure) and be recoverable from the failure.
64 * Return: 0 on success, -errno of failure
65 */
66
67#define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
68
52/* IOCTLs for FME file descriptor */ 69/* IOCTLs for FME file descriptor */
53 70
54/** 71/**