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authorLinus Torvalds <torvalds@linux-foundation.org>2018-10-29 18:16:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-10-29 18:16:01 -0400
commitb22b6beae6116e3a9c46ced312c626f6737a3fa6 (patch)
treec92228669e0444d91fd1445bc562351fd69b58cc /include/linux
parent53b7a3b7ec00f207c18e71f58ef2bca48635c622 (diff)
parentc1a92909dbc2090753ff6224971d9b8ae5f93c97 (diff)
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "The most noteworthy SoC driver changes this time include: - The TEE subsystem gains an in-kernel interface to access the TEE from device drivers. - The reset controller subsystem gains a driver for the Qualcomm Snapdragon 845 Power Domain Controller. - The Xilinx Zynq platform now has a firmware interface for its platform management unit. This contains a firmware "ioctl" interface that was a little controversial at first, but the version we merged solved that by not exposing arbitrary firmware calls to user space. - The Amlogic Meson platform gains a "canvas" driver that is used for video processing and shared between different high-level drivers. The rest is more of the usual, mostly related to SoC specific power management support and core drivers in drivers/soc: - Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new features related to power and reset control. - The Mediatek mt8183 and mt6765 SoC platforms gain support for their respective power management chips. - A new driver for NXP i.MX8, which need a firmware interface for power management. - The SCPI firmware interface now contains support estimating power usage of performance states - The NVIDIA Tegra "pmc" driver gains a few new features, in particular a pinctrl interface for configuring the pads. - Lots of small changes for Qualcomm, in particular the "smem" device driver. - Some cleanups for the TI OMAP series related to their sysc controller. Additional cleanups and bugfixes in SoC specific drivers include the Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits) firmware: tegra: bpmp: Implement suspend/resume support drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs MAINTAINERS: imx: include drivers/firmware/imx path firmware: imx: add misc svc support firmware: imx: add SCU firmware driver support reset: Fix potential use-after-free in __of_reset_control_get() dt-bindings: arm: fsl: add scu binding doc soc: fsl: qbman: add interrupt coalesce changing APIs soc: fsl: bman_portals: defer probe after bman's probe soc: fsl: qbman: Use last response to determine valid bit soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers soc: fsl: qbman: Check if CPU is offline when initializing portals reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/firmware/imx/ipc.h59
-rw-r--r--include/linux/firmware/imx/sci.h17
-rw-r--r--include/linux/firmware/imx/svc/misc.h55
-rw-r--r--include/linux/firmware/imx/types.h617
-rw-r--r--include/linux/firmware/meson/meson_sm.h1
-rw-r--r--include/linux/firmware/xlnx-zynqmp.h116
-rw-r--r--include/linux/platform_data/ti-sysc.h1
-rw-r--r--include/linux/reset.h2
-rw-r--r--include/linux/scmi_protocol.h4
-rw-r--r--include/linux/soc/amlogic/meson-canvas.h65
-rw-r--r--include/linux/soc/qcom/llcc-qcom.h30
-rw-r--r--include/linux/tee_drv.h73
12 files changed, 1036 insertions, 4 deletions
diff --git a/include/linux/firmware/imx/ipc.h b/include/linux/firmware/imx/ipc.h
new file mode 100644
index 000000000000..6312c8cb084a
--- /dev/null
+++ b/include/linux/firmware/imx/ipc.h
@@ -0,0 +1,59 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 *
5 * Header file for the IPC implementation.
6 */
7
8#ifndef _SC_IPC_H
9#define _SC_IPC_H
10
11#include <linux/device.h>
12#include <linux/types.h>
13
14#define IMX_SC_RPC_VERSION 1
15#define IMX_SC_RPC_MAX_MSG 8
16
17struct imx_sc_ipc;
18
19enum imx_sc_rpc_svc {
20 IMX_SC_RPC_SVC_UNKNOWN = 0,
21 IMX_SC_RPC_SVC_RETURN = 1,
22 IMX_SC_RPC_SVC_PM = 2,
23 IMX_SC_RPC_SVC_RM = 3,
24 IMX_SC_RPC_SVC_TIMER = 5,
25 IMX_SC_RPC_SVC_PAD = 6,
26 IMX_SC_RPC_SVC_MISC = 7,
27 IMX_SC_RPC_SVC_IRQ = 8,
28 IMX_SC_RPC_SVC_ABORT = 9
29};
30
31struct imx_sc_rpc_msg {
32 uint8_t ver;
33 uint8_t size;
34 uint8_t svc;
35 uint8_t func;
36};
37
38/*
39 * This is an function to send an RPC message over an IPC channel.
40 * It is called by client-side SCFW API function shims.
41 *
42 * @param[in] ipc IPC handle
43 * @param[in,out] msg handle to a message
44 * @param[in] have_resp response flag
45 *
46 * If have_resp is true then this function waits for a response
47 * and returns the result in msg.
48 */
49int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, bool have_resp);
50
51/*
52 * This function gets the default ipc handle used by SCU
53 *
54 * @param[out] ipc sc ipc handle
55 *
56 * @return Returns an error code (0 = success, failed if < 0)
57 */
58int imx_scu_get_handle(struct imx_sc_ipc **ipc);
59#endif /* _SC_IPC_H */
diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h
new file mode 100644
index 000000000000..29ada609de03
--- /dev/null
+++ b/include/linux/firmware/imx/sci.h
@@ -0,0 +1,17 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017~2018 NXP
5 *
6 * Header file containing the public System Controller Interface (SCI)
7 * definitions.
8 */
9
10#ifndef _SC_SCI_H
11#define _SC_SCI_H
12
13#include <linux/firmware/imx/ipc.h>
14#include <linux/firmware/imx/types.h>
15
16#include <linux/firmware/imx/svc/misc.h>
17#endif /* _SC_SCI_H */
diff --git a/include/linux/firmware/imx/svc/misc.h b/include/linux/firmware/imx/svc/misc.h
new file mode 100644
index 000000000000..e21c49aba92f
--- /dev/null
+++ b/include/linux/firmware/imx/svc/misc.h
@@ -0,0 +1,55 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017~2018 NXP
5 *
6 * Header file containing the public API for the System Controller (SC)
7 * Miscellaneous (MISC) function.
8 *
9 * MISC_SVC (SVC) Miscellaneous Service
10 *
11 * Module for the Miscellaneous (MISC) service.
12 */
13
14#ifndef _SC_MISC_API_H
15#define _SC_MISC_API_H
16
17#include <linux/firmware/imx/sci.h>
18
19/*
20 * This type is used to indicate RPC MISC function calls.
21 */
22enum imx_misc_func {
23 IMX_SC_MISC_FUNC_UNKNOWN = 0,
24 IMX_SC_MISC_FUNC_SET_CONTROL = 1,
25 IMX_SC_MISC_FUNC_GET_CONTROL = 2,
26 IMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP = 4,
27 IMX_SC_MISC_FUNC_SET_DMA_GROUP = 5,
28 IMX_SC_MISC_FUNC_SECO_IMAGE_LOAD = 8,
29 IMX_SC_MISC_FUNC_SECO_AUTHENTICATE = 9,
30 IMX_SC_MISC_FUNC_DEBUG_OUT = 10,
31 IMX_SC_MISC_FUNC_WAVEFORM_CAPTURE = 6,
32 IMX_SC_MISC_FUNC_BUILD_INFO = 15,
33 IMX_SC_MISC_FUNC_UNIQUE_ID = 19,
34 IMX_SC_MISC_FUNC_SET_ARI = 3,
35 IMX_SC_MISC_FUNC_BOOT_STATUS = 7,
36 IMX_SC_MISC_FUNC_BOOT_DONE = 14,
37 IMX_SC_MISC_FUNC_OTP_FUSE_READ = 11,
38 IMX_SC_MISC_FUNC_OTP_FUSE_WRITE = 17,
39 IMX_SC_MISC_FUNC_SET_TEMP = 12,
40 IMX_SC_MISC_FUNC_GET_TEMP = 13,
41 IMX_SC_MISC_FUNC_GET_BOOT_DEV = 16,
42 IMX_SC_MISC_FUNC_GET_BUTTON_STATUS = 18,
43};
44
45/*
46 * Control Functions
47 */
48
49int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
50 u8 ctrl, u32 val);
51
52int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
53 u8 ctrl, u32 *val);
54
55#endif /* _SC_MISC_API_H */
diff --git a/include/linux/firmware/imx/types.h b/include/linux/firmware/imx/types.h
new file mode 100644
index 000000000000..9cbf0c4a6069
--- /dev/null
+++ b/include/linux/firmware/imx/types.h
@@ -0,0 +1,617 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017~2018 NXP
5 *
6 * Header file containing types used across multiple service APIs.
7 */
8
9#ifndef _SC_TYPES_H
10#define _SC_TYPES_H
11
12/*
13 * This type is used to indicate a resource. Resources include peripherals
14 * and bus masters (but not memory regions). Note items from list should
15 * never be changed or removed (only added to at the end of the list).
16 */
17enum imx_sc_rsrc {
18 IMX_SC_R_A53 = 0,
19 IMX_SC_R_A53_0 = 1,
20 IMX_SC_R_A53_1 = 2,
21 IMX_SC_R_A53_2 = 3,
22 IMX_SC_R_A53_3 = 4,
23 IMX_SC_R_A72 = 5,
24 IMX_SC_R_A72_0 = 6,
25 IMX_SC_R_A72_1 = 7,
26 IMX_SC_R_A72_2 = 8,
27 IMX_SC_R_A72_3 = 9,
28 IMX_SC_R_CCI = 10,
29 IMX_SC_R_DB = 11,
30 IMX_SC_R_DRC_0 = 12,
31 IMX_SC_R_DRC_1 = 13,
32 IMX_SC_R_GIC_SMMU = 14,
33 IMX_SC_R_IRQSTR_M4_0 = 15,
34 IMX_SC_R_IRQSTR_M4_1 = 16,
35 IMX_SC_R_SMMU = 17,
36 IMX_SC_R_GIC = 18,
37 IMX_SC_R_DC_0_BLIT0 = 19,
38 IMX_SC_R_DC_0_BLIT1 = 20,
39 IMX_SC_R_DC_0_BLIT2 = 21,
40 IMX_SC_R_DC_0_BLIT_OUT = 22,
41 IMX_SC_R_DC_0_CAPTURE0 = 23,
42 IMX_SC_R_DC_0_CAPTURE1 = 24,
43 IMX_SC_R_DC_0_WARP = 25,
44 IMX_SC_R_DC_0_INTEGRAL0 = 26,
45 IMX_SC_R_DC_0_INTEGRAL1 = 27,
46 IMX_SC_R_DC_0_VIDEO0 = 28,
47 IMX_SC_R_DC_0_VIDEO1 = 29,
48 IMX_SC_R_DC_0_FRAC0 = 30,
49 IMX_SC_R_DC_0_FRAC1 = 31,
50 IMX_SC_R_DC_0 = 32,
51 IMX_SC_R_GPU_2_PID0 = 33,
52 IMX_SC_R_DC_0_PLL_0 = 34,
53 IMX_SC_R_DC_0_PLL_1 = 35,
54 IMX_SC_R_DC_1_BLIT0 = 36,
55 IMX_SC_R_DC_1_BLIT1 = 37,
56 IMX_SC_R_DC_1_BLIT2 = 38,
57 IMX_SC_R_DC_1_BLIT_OUT = 39,
58 IMX_SC_R_DC_1_CAPTURE0 = 40,
59 IMX_SC_R_DC_1_CAPTURE1 = 41,
60 IMX_SC_R_DC_1_WARP = 42,
61 IMX_SC_R_DC_1_INTEGRAL0 = 43,
62 IMX_SC_R_DC_1_INTEGRAL1 = 44,
63 IMX_SC_R_DC_1_VIDEO0 = 45,
64 IMX_SC_R_DC_1_VIDEO1 = 46,
65 IMX_SC_R_DC_1_FRAC0 = 47,
66 IMX_SC_R_DC_1_FRAC1 = 48,
67 IMX_SC_R_DC_1 = 49,
68 IMX_SC_R_GPU_3_PID0 = 50,
69 IMX_SC_R_DC_1_PLL_0 = 51,
70 IMX_SC_R_DC_1_PLL_1 = 52,
71 IMX_SC_R_SPI_0 = 53,
72 IMX_SC_R_SPI_1 = 54,
73 IMX_SC_R_SPI_2 = 55,
74 IMX_SC_R_SPI_3 = 56,
75 IMX_SC_R_UART_0 = 57,
76 IMX_SC_R_UART_1 = 58,
77 IMX_SC_R_UART_2 = 59,
78 IMX_SC_R_UART_3 = 60,
79 IMX_SC_R_UART_4 = 61,
80 IMX_SC_R_EMVSIM_0 = 62,
81 IMX_SC_R_EMVSIM_1 = 63,
82 IMX_SC_R_DMA_0_CH0 = 64,
83 IMX_SC_R_DMA_0_CH1 = 65,
84 IMX_SC_R_DMA_0_CH2 = 66,
85 IMX_SC_R_DMA_0_CH3 = 67,
86 IMX_SC_R_DMA_0_CH4 = 68,
87 IMX_SC_R_DMA_0_CH5 = 69,
88 IMX_SC_R_DMA_0_CH6 = 70,
89 IMX_SC_R_DMA_0_CH7 = 71,
90 IMX_SC_R_DMA_0_CH8 = 72,
91 IMX_SC_R_DMA_0_CH9 = 73,
92 IMX_SC_R_DMA_0_CH10 = 74,
93 IMX_SC_R_DMA_0_CH11 = 75,
94 IMX_SC_R_DMA_0_CH12 = 76,
95 IMX_SC_R_DMA_0_CH13 = 77,
96 IMX_SC_R_DMA_0_CH14 = 78,
97 IMX_SC_R_DMA_0_CH15 = 79,
98 IMX_SC_R_DMA_0_CH16 = 80,
99 IMX_SC_R_DMA_0_CH17 = 81,
100 IMX_SC_R_DMA_0_CH18 = 82,
101 IMX_SC_R_DMA_0_CH19 = 83,
102 IMX_SC_R_DMA_0_CH20 = 84,
103 IMX_SC_R_DMA_0_CH21 = 85,
104 IMX_SC_R_DMA_0_CH22 = 86,
105 IMX_SC_R_DMA_0_CH23 = 87,
106 IMX_SC_R_DMA_0_CH24 = 88,
107 IMX_SC_R_DMA_0_CH25 = 89,
108 IMX_SC_R_DMA_0_CH26 = 90,
109 IMX_SC_R_DMA_0_CH27 = 91,
110 IMX_SC_R_DMA_0_CH28 = 92,
111 IMX_SC_R_DMA_0_CH29 = 93,
112 IMX_SC_R_DMA_0_CH30 = 94,
113 IMX_SC_R_DMA_0_CH31 = 95,
114 IMX_SC_R_I2C_0 = 96,
115 IMX_SC_R_I2C_1 = 97,
116 IMX_SC_R_I2C_2 = 98,
117 IMX_SC_R_I2C_3 = 99,
118 IMX_SC_R_I2C_4 = 100,
119 IMX_SC_R_ADC_0 = 101,
120 IMX_SC_R_ADC_1 = 102,
121 IMX_SC_R_FTM_0 = 103,
122 IMX_SC_R_FTM_1 = 104,
123 IMX_SC_R_CAN_0 = 105,
124 IMX_SC_R_CAN_1 = 106,
125 IMX_SC_R_CAN_2 = 107,
126 IMX_SC_R_DMA_1_CH0 = 108,
127 IMX_SC_R_DMA_1_CH1 = 109,
128 IMX_SC_R_DMA_1_CH2 = 110,
129 IMX_SC_R_DMA_1_CH3 = 111,
130 IMX_SC_R_DMA_1_CH4 = 112,
131 IMX_SC_R_DMA_1_CH5 = 113,
132 IMX_SC_R_DMA_1_CH6 = 114,
133 IMX_SC_R_DMA_1_CH7 = 115,
134 IMX_SC_R_DMA_1_CH8 = 116,
135 IMX_SC_R_DMA_1_CH9 = 117,
136 IMX_SC_R_DMA_1_CH10 = 118,
137 IMX_SC_R_DMA_1_CH11 = 119,
138 IMX_SC_R_DMA_1_CH12 = 120,
139 IMX_SC_R_DMA_1_CH13 = 121,
140 IMX_SC_R_DMA_1_CH14 = 122,
141 IMX_SC_R_DMA_1_CH15 = 123,
142 IMX_SC_R_DMA_1_CH16 = 124,
143 IMX_SC_R_DMA_1_CH17 = 125,
144 IMX_SC_R_DMA_1_CH18 = 126,
145 IMX_SC_R_DMA_1_CH19 = 127,
146 IMX_SC_R_DMA_1_CH20 = 128,
147 IMX_SC_R_DMA_1_CH21 = 129,
148 IMX_SC_R_DMA_1_CH22 = 130,
149 IMX_SC_R_DMA_1_CH23 = 131,
150 IMX_SC_R_DMA_1_CH24 = 132,
151 IMX_SC_R_DMA_1_CH25 = 133,
152 IMX_SC_R_DMA_1_CH26 = 134,
153 IMX_SC_R_DMA_1_CH27 = 135,
154 IMX_SC_R_DMA_1_CH28 = 136,
155 IMX_SC_R_DMA_1_CH29 = 137,
156 IMX_SC_R_DMA_1_CH30 = 138,
157 IMX_SC_R_DMA_1_CH31 = 139,
158 IMX_SC_R_UNUSED1 = 140,
159 IMX_SC_R_UNUSED2 = 141,
160 IMX_SC_R_UNUSED3 = 142,
161 IMX_SC_R_UNUSED4 = 143,
162 IMX_SC_R_GPU_0_PID0 = 144,
163 IMX_SC_R_GPU_0_PID1 = 145,
164 IMX_SC_R_GPU_0_PID2 = 146,
165 IMX_SC_R_GPU_0_PID3 = 147,
166 IMX_SC_R_GPU_1_PID0 = 148,
167 IMX_SC_R_GPU_1_PID1 = 149,
168 IMX_SC_R_GPU_1_PID2 = 150,
169 IMX_SC_R_GPU_1_PID3 = 151,
170 IMX_SC_R_PCIE_A = 152,
171 IMX_SC_R_SERDES_0 = 153,
172 IMX_SC_R_MATCH_0 = 154,
173 IMX_SC_R_MATCH_1 = 155,
174 IMX_SC_R_MATCH_2 = 156,
175 IMX_SC_R_MATCH_3 = 157,
176 IMX_SC_R_MATCH_4 = 158,
177 IMX_SC_R_MATCH_5 = 159,
178 IMX_SC_R_MATCH_6 = 160,
179 IMX_SC_R_MATCH_7 = 161,
180 IMX_SC_R_MATCH_8 = 162,
181 IMX_SC_R_MATCH_9 = 163,
182 IMX_SC_R_MATCH_10 = 164,
183 IMX_SC_R_MATCH_11 = 165,
184 IMX_SC_R_MATCH_12 = 166,
185 IMX_SC_R_MATCH_13 = 167,
186 IMX_SC_R_MATCH_14 = 168,
187 IMX_SC_R_PCIE_B = 169,
188 IMX_SC_R_SATA_0 = 170,
189 IMX_SC_R_SERDES_1 = 171,
190 IMX_SC_R_HSIO_GPIO = 172,
191 IMX_SC_R_MATCH_15 = 173,
192 IMX_SC_R_MATCH_16 = 174,
193 IMX_SC_R_MATCH_17 = 175,
194 IMX_SC_R_MATCH_18 = 176,
195 IMX_SC_R_MATCH_19 = 177,
196 IMX_SC_R_MATCH_20 = 178,
197 IMX_SC_R_MATCH_21 = 179,
198 IMX_SC_R_MATCH_22 = 180,
199 IMX_SC_R_MATCH_23 = 181,
200 IMX_SC_R_MATCH_24 = 182,
201 IMX_SC_R_MATCH_25 = 183,
202 IMX_SC_R_MATCH_26 = 184,
203 IMX_SC_R_MATCH_27 = 185,
204 IMX_SC_R_MATCH_28 = 186,
205 IMX_SC_R_LCD_0 = 187,
206 IMX_SC_R_LCD_0_PWM_0 = 188,
207 IMX_SC_R_LCD_0_I2C_0 = 189,
208 IMX_SC_R_LCD_0_I2C_1 = 190,
209 IMX_SC_R_PWM_0 = 191,
210 IMX_SC_R_PWM_1 = 192,
211 IMX_SC_R_PWM_2 = 193,
212 IMX_SC_R_PWM_3 = 194,
213 IMX_SC_R_PWM_4 = 195,
214 IMX_SC_R_PWM_5 = 196,
215 IMX_SC_R_PWM_6 = 197,
216 IMX_SC_R_PWM_7 = 198,
217 IMX_SC_R_GPIO_0 = 199,
218 IMX_SC_R_GPIO_1 = 200,
219 IMX_SC_R_GPIO_2 = 201,
220 IMX_SC_R_GPIO_3 = 202,
221 IMX_SC_R_GPIO_4 = 203,
222 IMX_SC_R_GPIO_5 = 204,
223 IMX_SC_R_GPIO_6 = 205,
224 IMX_SC_R_GPIO_7 = 206,
225 IMX_SC_R_GPT_0 = 207,
226 IMX_SC_R_GPT_1 = 208,
227 IMX_SC_R_GPT_2 = 209,
228 IMX_SC_R_GPT_3 = 210,
229 IMX_SC_R_GPT_4 = 211,
230 IMX_SC_R_KPP = 212,
231 IMX_SC_R_MU_0A = 213,
232 IMX_SC_R_MU_1A = 214,
233 IMX_SC_R_MU_2A = 215,
234 IMX_SC_R_MU_3A = 216,
235 IMX_SC_R_MU_4A = 217,
236 IMX_SC_R_MU_5A = 218,
237 IMX_SC_R_MU_6A = 219,
238 IMX_SC_R_MU_7A = 220,
239 IMX_SC_R_MU_8A = 221,
240 IMX_SC_R_MU_9A = 222,
241 IMX_SC_R_MU_10A = 223,
242 IMX_SC_R_MU_11A = 224,
243 IMX_SC_R_MU_12A = 225,
244 IMX_SC_R_MU_13A = 226,
245 IMX_SC_R_MU_5B = 227,
246 IMX_SC_R_MU_6B = 228,
247 IMX_SC_R_MU_7B = 229,
248 IMX_SC_R_MU_8B = 230,
249 IMX_SC_R_MU_9B = 231,
250 IMX_SC_R_MU_10B = 232,
251 IMX_SC_R_MU_11B = 233,
252 IMX_SC_R_MU_12B = 234,
253 IMX_SC_R_MU_13B = 235,
254 IMX_SC_R_ROM_0 = 236,
255 IMX_SC_R_FSPI_0 = 237,
256 IMX_SC_R_FSPI_1 = 238,
257 IMX_SC_R_IEE = 239,
258 IMX_SC_R_IEE_R0 = 240,
259 IMX_SC_R_IEE_R1 = 241,
260 IMX_SC_R_IEE_R2 = 242,
261 IMX_SC_R_IEE_R3 = 243,
262 IMX_SC_R_IEE_R4 = 244,
263 IMX_SC_R_IEE_R5 = 245,
264 IMX_SC_R_IEE_R6 = 246,
265 IMX_SC_R_IEE_R7 = 247,
266 IMX_SC_R_SDHC_0 = 248,
267 IMX_SC_R_SDHC_1 = 249,
268 IMX_SC_R_SDHC_2 = 250,
269 IMX_SC_R_ENET_0 = 251,
270 IMX_SC_R_ENET_1 = 252,
271 IMX_SC_R_MLB_0 = 253,
272 IMX_SC_R_DMA_2_CH0 = 254,
273 IMX_SC_R_DMA_2_CH1 = 255,
274 IMX_SC_R_DMA_2_CH2 = 256,
275 IMX_SC_R_DMA_2_CH3 = 257,
276 IMX_SC_R_DMA_2_CH4 = 258,
277 IMX_SC_R_USB_0 = 259,
278 IMX_SC_R_USB_1 = 260,
279 IMX_SC_R_USB_0_PHY = 261,
280 IMX_SC_R_USB_2 = 262,
281 IMX_SC_R_USB_2_PHY = 263,
282 IMX_SC_R_DTCP = 264,
283 IMX_SC_R_NAND = 265,
284 IMX_SC_R_LVDS_0 = 266,
285 IMX_SC_R_LVDS_0_PWM_0 = 267,
286 IMX_SC_R_LVDS_0_I2C_0 = 268,
287 IMX_SC_R_LVDS_0_I2C_1 = 269,
288 IMX_SC_R_LVDS_1 = 270,
289 IMX_SC_R_LVDS_1_PWM_0 = 271,
290 IMX_SC_R_LVDS_1_I2C_0 = 272,
291 IMX_SC_R_LVDS_1_I2C_1 = 273,
292 IMX_SC_R_LVDS_2 = 274,
293 IMX_SC_R_LVDS_2_PWM_0 = 275,
294 IMX_SC_R_LVDS_2_I2C_0 = 276,
295 IMX_SC_R_LVDS_2_I2C_1 = 277,
296 IMX_SC_R_M4_0_PID0 = 278,
297 IMX_SC_R_M4_0_PID1 = 279,
298 IMX_SC_R_M4_0_PID2 = 280,
299 IMX_SC_R_M4_0_PID3 = 281,
300 IMX_SC_R_M4_0_PID4 = 282,
301 IMX_SC_R_M4_0_RGPIO = 283,
302 IMX_SC_R_M4_0_SEMA42 = 284,
303 IMX_SC_R_M4_0_TPM = 285,
304 IMX_SC_R_M4_0_PIT = 286,
305 IMX_SC_R_M4_0_UART = 287,
306 IMX_SC_R_M4_0_I2C = 288,
307 IMX_SC_R_M4_0_INTMUX = 289,
308 IMX_SC_R_M4_0_SIM = 290,
309 IMX_SC_R_M4_0_WDOG = 291,
310 IMX_SC_R_M4_0_MU_0B = 292,
311 IMX_SC_R_M4_0_MU_0A0 = 293,
312 IMX_SC_R_M4_0_MU_0A1 = 294,
313 IMX_SC_R_M4_0_MU_0A2 = 295,
314 IMX_SC_R_M4_0_MU_0A3 = 296,
315 IMX_SC_R_M4_0_MU_1A = 297,
316 IMX_SC_R_M4_1_PID0 = 298,
317 IMX_SC_R_M4_1_PID1 = 299,
318 IMX_SC_R_M4_1_PID2 = 300,
319 IMX_SC_R_M4_1_PID3 = 301,
320 IMX_SC_R_M4_1_PID4 = 302,
321 IMX_SC_R_M4_1_RGPIO = 303,
322 IMX_SC_R_M4_1_SEMA42 = 304,
323 IMX_SC_R_M4_1_TPM = 305,
324 IMX_SC_R_M4_1_PIT = 306,
325 IMX_SC_R_M4_1_UART = 307,
326 IMX_SC_R_M4_1_I2C = 308,
327 IMX_SC_R_M4_1_INTMUX = 309,
328 IMX_SC_R_M4_1_SIM = 310,
329 IMX_SC_R_M4_1_WDOG = 311,
330 IMX_SC_R_M4_1_MU_0B = 312,
331 IMX_SC_R_M4_1_MU_0A0 = 313,
332 IMX_SC_R_M4_1_MU_0A1 = 314,
333 IMX_SC_R_M4_1_MU_0A2 = 315,
334 IMX_SC_R_M4_1_MU_0A3 = 316,
335 IMX_SC_R_M4_1_MU_1A = 317,
336 IMX_SC_R_SAI_0 = 318,
337 IMX_SC_R_SAI_1 = 319,
338 IMX_SC_R_SAI_2 = 320,
339 IMX_SC_R_IRQSTR_SCU2 = 321,
340 IMX_SC_R_IRQSTR_DSP = 322,
341 IMX_SC_R_UNUSED5 = 323,
342 IMX_SC_R_UNUSED6 = 324,
343 IMX_SC_R_AUDIO_PLL_0 = 325,
344 IMX_SC_R_PI_0 = 326,
345 IMX_SC_R_PI_0_PWM_0 = 327,
346 IMX_SC_R_PI_0_PWM_1 = 328,
347 IMX_SC_R_PI_0_I2C_0 = 329,
348 IMX_SC_R_PI_0_PLL = 330,
349 IMX_SC_R_PI_1 = 331,
350 IMX_SC_R_PI_1_PWM_0 = 332,
351 IMX_SC_R_PI_1_PWM_1 = 333,
352 IMX_SC_R_PI_1_I2C_0 = 334,
353 IMX_SC_R_PI_1_PLL = 335,
354 IMX_SC_R_SC_PID0 = 336,
355 IMX_SC_R_SC_PID1 = 337,
356 IMX_SC_R_SC_PID2 = 338,
357 IMX_SC_R_SC_PID3 = 339,
358 IMX_SC_R_SC_PID4 = 340,
359 IMX_SC_R_SC_SEMA42 = 341,
360 IMX_SC_R_SC_TPM = 342,
361 IMX_SC_R_SC_PIT = 343,
362 IMX_SC_R_SC_UART = 344,
363 IMX_SC_R_SC_I2C = 345,
364 IMX_SC_R_SC_MU_0B = 346,
365 IMX_SC_R_SC_MU_0A0 = 347,
366 IMX_SC_R_SC_MU_0A1 = 348,
367 IMX_SC_R_SC_MU_0A2 = 349,
368 IMX_SC_R_SC_MU_0A3 = 350,
369 IMX_SC_R_SC_MU_1A = 351,
370 IMX_SC_R_SYSCNT_RD = 352,
371 IMX_SC_R_SYSCNT_CMP = 353,
372 IMX_SC_R_DEBUG = 354,
373 IMX_SC_R_SYSTEM = 355,
374 IMX_SC_R_SNVS = 356,
375 IMX_SC_R_OTP = 357,
376 IMX_SC_R_VPU_PID0 = 358,
377 IMX_SC_R_VPU_PID1 = 359,
378 IMX_SC_R_VPU_PID2 = 360,
379 IMX_SC_R_VPU_PID3 = 361,
380 IMX_SC_R_VPU_PID4 = 362,
381 IMX_SC_R_VPU_PID5 = 363,
382 IMX_SC_R_VPU_PID6 = 364,
383 IMX_SC_R_VPU_PID7 = 365,
384 IMX_SC_R_VPU_UART = 366,
385 IMX_SC_R_VPUCORE = 367,
386 IMX_SC_R_VPUCORE_0 = 368,
387 IMX_SC_R_VPUCORE_1 = 369,
388 IMX_SC_R_VPUCORE_2 = 370,
389 IMX_SC_R_VPUCORE_3 = 371,
390 IMX_SC_R_DMA_4_CH0 = 372,
391 IMX_SC_R_DMA_4_CH1 = 373,
392 IMX_SC_R_DMA_4_CH2 = 374,
393 IMX_SC_R_DMA_4_CH3 = 375,
394 IMX_SC_R_DMA_4_CH4 = 376,
395 IMX_SC_R_ISI_CH0 = 377,
396 IMX_SC_R_ISI_CH1 = 378,
397 IMX_SC_R_ISI_CH2 = 379,
398 IMX_SC_R_ISI_CH3 = 380,
399 IMX_SC_R_ISI_CH4 = 381,
400 IMX_SC_R_ISI_CH5 = 382,
401 IMX_SC_R_ISI_CH6 = 383,
402 IMX_SC_R_ISI_CH7 = 384,
403 IMX_SC_R_MJPEG_DEC_S0 = 385,
404 IMX_SC_R_MJPEG_DEC_S1 = 386,
405 IMX_SC_R_MJPEG_DEC_S2 = 387,
406 IMX_SC_R_MJPEG_DEC_S3 = 388,
407 IMX_SC_R_MJPEG_ENC_S0 = 389,
408 IMX_SC_R_MJPEG_ENC_S1 = 390,
409 IMX_SC_R_MJPEG_ENC_S2 = 391,
410 IMX_SC_R_MJPEG_ENC_S3 = 392,
411 IMX_SC_R_MIPI_0 = 393,
412 IMX_SC_R_MIPI_0_PWM_0 = 394,
413 IMX_SC_R_MIPI_0_I2C_0 = 395,
414 IMX_SC_R_MIPI_0_I2C_1 = 396,
415 IMX_SC_R_MIPI_1 = 397,
416 IMX_SC_R_MIPI_1_PWM_0 = 398,
417 IMX_SC_R_MIPI_1_I2C_0 = 399,
418 IMX_SC_R_MIPI_1_I2C_1 = 400,
419 IMX_SC_R_CSI_0 = 401,
420 IMX_SC_R_CSI_0_PWM_0 = 402,
421 IMX_SC_R_CSI_0_I2C_0 = 403,
422 IMX_SC_R_CSI_1 = 404,
423 IMX_SC_R_CSI_1_PWM_0 = 405,
424 IMX_SC_R_CSI_1_I2C_0 = 406,
425 IMX_SC_R_HDMI = 407,
426 IMX_SC_R_HDMI_I2S = 408,
427 IMX_SC_R_HDMI_I2C_0 = 409,
428 IMX_SC_R_HDMI_PLL_0 = 410,
429 IMX_SC_R_HDMI_RX = 411,
430 IMX_SC_R_HDMI_RX_BYPASS = 412,
431 IMX_SC_R_HDMI_RX_I2C_0 = 413,
432 IMX_SC_R_ASRC_0 = 414,
433 IMX_SC_R_ESAI_0 = 415,
434 IMX_SC_R_SPDIF_0 = 416,
435 IMX_SC_R_SPDIF_1 = 417,
436 IMX_SC_R_SAI_3 = 418,
437 IMX_SC_R_SAI_4 = 419,
438 IMX_SC_R_SAI_5 = 420,
439 IMX_SC_R_GPT_5 = 421,
440 IMX_SC_R_GPT_6 = 422,
441 IMX_SC_R_GPT_7 = 423,
442 IMX_SC_R_GPT_8 = 424,
443 IMX_SC_R_GPT_9 = 425,
444 IMX_SC_R_GPT_10 = 426,
445 IMX_SC_R_DMA_2_CH5 = 427,
446 IMX_SC_R_DMA_2_CH6 = 428,
447 IMX_SC_R_DMA_2_CH7 = 429,
448 IMX_SC_R_DMA_2_CH8 = 430,
449 IMX_SC_R_DMA_2_CH9 = 431,
450 IMX_SC_R_DMA_2_CH10 = 432,
451 IMX_SC_R_DMA_2_CH11 = 433,
452 IMX_SC_R_DMA_2_CH12 = 434,
453 IMX_SC_R_DMA_2_CH13 = 435,
454 IMX_SC_R_DMA_2_CH14 = 436,
455 IMX_SC_R_DMA_2_CH15 = 437,
456 IMX_SC_R_DMA_2_CH16 = 438,
457 IMX_SC_R_DMA_2_CH17 = 439,
458 IMX_SC_R_DMA_2_CH18 = 440,
459 IMX_SC_R_DMA_2_CH19 = 441,
460 IMX_SC_R_DMA_2_CH20 = 442,
461 IMX_SC_R_DMA_2_CH21 = 443,
462 IMX_SC_R_DMA_2_CH22 = 444,
463 IMX_SC_R_DMA_2_CH23 = 445,
464 IMX_SC_R_DMA_2_CH24 = 446,
465 IMX_SC_R_DMA_2_CH25 = 447,
466 IMX_SC_R_DMA_2_CH26 = 448,
467 IMX_SC_R_DMA_2_CH27 = 449,
468 IMX_SC_R_DMA_2_CH28 = 450,
469 IMX_SC_R_DMA_2_CH29 = 451,
470 IMX_SC_R_DMA_2_CH30 = 452,
471 IMX_SC_R_DMA_2_CH31 = 453,
472 IMX_SC_R_ASRC_1 = 454,
473 IMX_SC_R_ESAI_1 = 455,
474 IMX_SC_R_SAI_6 = 456,
475 IMX_SC_R_SAI_7 = 457,
476 IMX_SC_R_AMIX = 458,
477 IMX_SC_R_MQS_0 = 459,
478 IMX_SC_R_DMA_3_CH0 = 460,
479 IMX_SC_R_DMA_3_CH1 = 461,
480 IMX_SC_R_DMA_3_CH2 = 462,
481 IMX_SC_R_DMA_3_CH3 = 463,
482 IMX_SC_R_DMA_3_CH4 = 464,
483 IMX_SC_R_DMA_3_CH5 = 465,
484 IMX_SC_R_DMA_3_CH6 = 466,
485 IMX_SC_R_DMA_3_CH7 = 467,
486 IMX_SC_R_DMA_3_CH8 = 468,
487 IMX_SC_R_DMA_3_CH9 = 469,
488 IMX_SC_R_DMA_3_CH10 = 470,
489 IMX_SC_R_DMA_3_CH11 = 471,
490 IMX_SC_R_DMA_3_CH12 = 472,
491 IMX_SC_R_DMA_3_CH13 = 473,
492 IMX_SC_R_DMA_3_CH14 = 474,
493 IMX_SC_R_DMA_3_CH15 = 475,
494 IMX_SC_R_DMA_3_CH16 = 476,
495 IMX_SC_R_DMA_3_CH17 = 477,
496 IMX_SC_R_DMA_3_CH18 = 478,
497 IMX_SC_R_DMA_3_CH19 = 479,
498 IMX_SC_R_DMA_3_CH20 = 480,
499 IMX_SC_R_DMA_3_CH21 = 481,
500 IMX_SC_R_DMA_3_CH22 = 482,
501 IMX_SC_R_DMA_3_CH23 = 483,
502 IMX_SC_R_DMA_3_CH24 = 484,
503 IMX_SC_R_DMA_3_CH25 = 485,
504 IMX_SC_R_DMA_3_CH26 = 486,
505 IMX_SC_R_DMA_3_CH27 = 487,
506 IMX_SC_R_DMA_3_CH28 = 488,
507 IMX_SC_R_DMA_3_CH29 = 489,
508 IMX_SC_R_DMA_3_CH30 = 490,
509 IMX_SC_R_DMA_3_CH31 = 491,
510 IMX_SC_R_AUDIO_PLL_1 = 492,
511 IMX_SC_R_AUDIO_CLK_0 = 493,
512 IMX_SC_R_AUDIO_CLK_1 = 494,
513 IMX_SC_R_MCLK_OUT_0 = 495,
514 IMX_SC_R_MCLK_OUT_1 = 496,
515 IMX_SC_R_PMIC_0 = 497,
516 IMX_SC_R_PMIC_1 = 498,
517 IMX_SC_R_SECO = 499,
518 IMX_SC_R_CAAM_JR1 = 500,
519 IMX_SC_R_CAAM_JR2 = 501,
520 IMX_SC_R_CAAM_JR3 = 502,
521 IMX_SC_R_SECO_MU_2 = 503,
522 IMX_SC_R_SECO_MU_3 = 504,
523 IMX_SC_R_SECO_MU_4 = 505,
524 IMX_SC_R_HDMI_RX_PWM_0 = 506,
525 IMX_SC_R_A35 = 507,
526 IMX_SC_R_A35_0 = 508,
527 IMX_SC_R_A35_1 = 509,
528 IMX_SC_R_A35_2 = 510,
529 IMX_SC_R_A35_3 = 511,
530 IMX_SC_R_DSP = 512,
531 IMX_SC_R_DSP_RAM = 513,
532 IMX_SC_R_CAAM_JR1_OUT = 514,
533 IMX_SC_R_CAAM_JR2_OUT = 515,
534 IMX_SC_R_CAAM_JR3_OUT = 516,
535 IMX_SC_R_VPU_DEC_0 = 517,
536 IMX_SC_R_VPU_ENC_0 = 518,
537 IMX_SC_R_CAAM_JR0 = 519,
538 IMX_SC_R_CAAM_JR0_OUT = 520,
539 IMX_SC_R_PMIC_2 = 521,
540 IMX_SC_R_DBLOGIC = 522,
541 IMX_SC_R_HDMI_PLL_1 = 523,
542 IMX_SC_R_BOARD_R0 = 524,
543 IMX_SC_R_BOARD_R1 = 525,
544 IMX_SC_R_BOARD_R2 = 526,
545 IMX_SC_R_BOARD_R3 = 527,
546 IMX_SC_R_BOARD_R4 = 528,
547 IMX_SC_R_BOARD_R5 = 529,
548 IMX_SC_R_BOARD_R6 = 530,
549 IMX_SC_R_BOARD_R7 = 531,
550 IMX_SC_R_MJPEG_DEC_MP = 532,
551 IMX_SC_R_MJPEG_ENC_MP = 533,
552 IMX_SC_R_VPU_TS_0 = 534,
553 IMX_SC_R_VPU_MU_0 = 535,
554 IMX_SC_R_VPU_MU_1 = 536,
555 IMX_SC_R_VPU_MU_2 = 537,
556 IMX_SC_R_VPU_MU_3 = 538,
557 IMX_SC_R_VPU_ENC_1 = 539,
558 IMX_SC_R_VPU = 540,
559 IMX_SC_R_LAST
560};
561
562/* NOTE - please add by replacing some of the UNUSED from above! */
563
564/*
565 * This type is used to indicate a control.
566 */
567enum imx_sc_ctrl {
568 IMX_SC_C_TEMP = 0,
569 IMX_SC_C_TEMP_HI = 1,
570 IMX_SC_C_TEMP_LOW = 2,
571 IMX_SC_C_PXL_LINK_MST1_ADDR = 3,
572 IMX_SC_C_PXL_LINK_MST2_ADDR = 4,
573 IMX_SC_C_PXL_LINK_MST_ENB = 5,
574 IMX_SC_C_PXL_LINK_MST1_ENB = 6,
575 IMX_SC_C_PXL_LINK_MST2_ENB = 7,
576 IMX_SC_C_PXL_LINK_SLV1_ADDR = 8,
577 IMX_SC_C_PXL_LINK_SLV2_ADDR = 9,
578 IMX_SC_C_PXL_LINK_MST_VLD = 10,
579 IMX_SC_C_PXL_LINK_MST1_VLD = 11,
580 IMX_SC_C_PXL_LINK_MST2_VLD = 12,
581 IMX_SC_C_SINGLE_MODE = 13,
582 IMX_SC_C_ID = 14,
583 IMX_SC_C_PXL_CLK_POLARITY = 15,
584 IMX_SC_C_LINESTATE = 16,
585 IMX_SC_C_PCIE_G_RST = 17,
586 IMX_SC_C_PCIE_BUTTON_RST = 18,
587 IMX_SC_C_PCIE_PERST = 19,
588 IMX_SC_C_PHY_RESET = 20,
589 IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21,
590 IMX_SC_C_PANIC = 22,
591 IMX_SC_C_PRIORITY_GROUP = 23,
592 IMX_SC_C_TXCLK = 24,
593 IMX_SC_C_CLKDIV = 25,
594 IMX_SC_C_DISABLE_50 = 26,
595 IMX_SC_C_DISABLE_125 = 27,
596 IMX_SC_C_SEL_125 = 28,
597 IMX_SC_C_MODE = 29,
598 IMX_SC_C_SYNC_CTRL0 = 30,
599 IMX_SC_C_KACHUNK_CNT = 31,
600 IMX_SC_C_KACHUNK_SEL = 32,
601 IMX_SC_C_SYNC_CTRL1 = 33,
602 IMX_SC_C_DPI_RESET = 34,
603 IMX_SC_C_MIPI_RESET = 35,
604 IMX_SC_C_DUAL_MODE = 36,
605 IMX_SC_C_VOLTAGE = 37,
606 IMX_SC_C_PXL_LINK_SEL = 38,
607 IMX_SC_C_OFS_SEL = 39,
608 IMX_SC_C_OFS_AUDIO = 40,
609 IMX_SC_C_OFS_PERIPH = 41,
610 IMX_SC_C_OFS_IRQ = 42,
611 IMX_SC_C_RST0 = 43,
612 IMX_SC_C_RST1 = 44,
613 IMX_SC_C_SEL0 = 45,
614 IMX_SC_C_LAST
615};
616
617#endif /* _SC_TYPES_H */
diff --git a/include/linux/firmware/meson/meson_sm.h b/include/linux/firmware/meson/meson_sm.h
index 37a5eaea69dd..f98c20dd266e 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -17,6 +17,7 @@ enum {
17 SM_EFUSE_READ, 17 SM_EFUSE_READ,
18 SM_EFUSE_WRITE, 18 SM_EFUSE_WRITE,
19 SM_EFUSE_USER_MAX, 19 SM_EFUSE_USER_MAX,
20 SM_GET_CHIP_ID,
20}; 21};
21 22
22struct meson_sm_firmware; 23struct meson_sm_firmware;
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
new file mode 100644
index 000000000000..3c3c28eff56a
--- /dev/null
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -0,0 +1,116 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2018 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#define ZYNQMP_PM_VERSION_MAJOR 1
17#define ZYNQMP_PM_VERSION_MINOR 0
18
19#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22#define ZYNQMP_TZ_VERSION_MAJOR 1
23#define ZYNQMP_TZ_VERSION_MINOR 0
24
25#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28/* SMC SIP service Call Function Identifier Prefix */
29#define PM_SIP_SVC 0xC2000000
30#define PM_GET_TRUSTZONE_VERSION 0xa03
31
32/* Number of 32bits values in payload */
33#define PAYLOAD_ARG_CNT 4U
34
35enum pm_api_id {
36 PM_GET_API_VERSION = 1,
37 PM_IOCTL = 34,
38 PM_QUERY_DATA,
39 PM_CLOCK_ENABLE,
40 PM_CLOCK_DISABLE,
41 PM_CLOCK_GETSTATE,
42 PM_CLOCK_SETDIVIDER,
43 PM_CLOCK_GETDIVIDER,
44 PM_CLOCK_SETRATE,
45 PM_CLOCK_GETRATE,
46 PM_CLOCK_SETPARENT,
47 PM_CLOCK_GETPARENT,
48};
49
50/* PMU-FW return status codes */
51enum pm_ret_status {
52 XST_PM_SUCCESS = 0,
53 XST_PM_INTERNAL = 2000,
54 XST_PM_CONFLICT,
55 XST_PM_NO_ACCESS,
56 XST_PM_INVALID_NODE,
57 XST_PM_DOUBLE_REQ,
58 XST_PM_ABORT_SUSPEND,
59};
60
61enum pm_ioctl_id {
62 IOCTL_SET_PLL_FRAC_MODE = 8,
63 IOCTL_GET_PLL_FRAC_MODE,
64 IOCTL_SET_PLL_FRAC_DATA,
65 IOCTL_GET_PLL_FRAC_DATA,
66};
67
68enum pm_query_id {
69 PM_QID_INVALID,
70 PM_QID_CLOCK_GET_NAME,
71 PM_QID_CLOCK_GET_TOPOLOGY,
72 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
73 PM_QID_CLOCK_GET_PARENTS,
74 PM_QID_CLOCK_GET_ATTRIBUTES,
75 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
76};
77
78/**
79 * struct zynqmp_pm_query_data - PM query data
80 * @qid: query ID
81 * @arg1: Argument 1 of query data
82 * @arg2: Argument 2 of query data
83 * @arg3: Argument 3 of query data
84 */
85struct zynqmp_pm_query_data {
86 u32 qid;
87 u32 arg1;
88 u32 arg2;
89 u32 arg3;
90};
91
92struct zynqmp_eemi_ops {
93 int (*get_api_version)(u32 *version);
94 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
95 int (*clock_enable)(u32 clock_id);
96 int (*clock_disable)(u32 clock_id);
97 int (*clock_getstate)(u32 clock_id, u32 *state);
98 int (*clock_setdivider)(u32 clock_id, u32 divider);
99 int (*clock_getdivider)(u32 clock_id, u32 *divider);
100 int (*clock_setrate)(u32 clock_id, u64 rate);
101 int (*clock_getrate)(u32 clock_id, u64 *rate);
102 int (*clock_setparent)(u32 clock_id, u32 parent_id);
103 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
104 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
105};
106
107#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
108const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
109#else
110static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
111{
112 return NULL;
113}
114#endif
115
116#endif /* __FIRMWARE_ZYNQMP_H__ */
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
index 2efa3470a451..1ea3aab972b4 100644
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -46,7 +46,6 @@ struct sysc_regbits {
46 s8 emufree_shift; 46 s8 emufree_shift;
47}; 47};
48 48
49#define SYSC_QUIRK_RESOURCE_PROVIDER BIT(9)
50#define SYSC_QUIRK_LEGACY_IDLE BIT(8) 49#define SYSC_QUIRK_LEGACY_IDLE BIT(8)
51#define SYSC_QUIRK_RESET_STATUS BIT(7) 50#define SYSC_QUIRK_RESET_STATUS BIT(7)
52#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 51#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 09732c36f351..29af6d6b2f4b 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -116,7 +116,7 @@ static inline int device_reset_optional(struct device *dev)
116 * @id: reset line name 116 * @id: reset line name
117 * 117 *
118 * Returns a struct reset_control or IS_ERR() condition containing errno. 118 * Returns a struct reset_control or IS_ERR() condition containing errno.
119 * If this function is called more then once for the same reset_control it will 119 * If this function is called more than once for the same reset_control it will
120 * return -EBUSY. 120 * return -EBUSY.
121 * 121 *
122 * See reset_control_get_shared for details on shared references to 122 * See reset_control_get_shared for details on shared references to
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index f4c9fc0fc755..3105055c00a7 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -91,6 +91,8 @@ struct scmi_clk_ops {
91 * to sustained performance level mapping 91 * to sustained performance level mapping
92 * @freq_get: gets the frequency for a given device using sustained frequency 92 * @freq_get: gets the frequency for a given device using sustained frequency
93 * to sustained performance level mapping 93 * to sustained performance level mapping
94 * @est_power_get: gets the estimated power cost for a given performance domain
95 * at a given frequency
94 */ 96 */
95struct scmi_perf_ops { 97struct scmi_perf_ops {
96 int (*limits_set)(const struct scmi_handle *handle, u32 domain, 98 int (*limits_set)(const struct scmi_handle *handle, u32 domain,
@@ -110,6 +112,8 @@ struct scmi_perf_ops {
110 unsigned long rate, bool poll); 112 unsigned long rate, bool poll);
111 int (*freq_get)(const struct scmi_handle *handle, u32 domain, 113 int (*freq_get)(const struct scmi_handle *handle, u32 domain,
112 unsigned long *rate, bool poll); 114 unsigned long *rate, bool poll);
115 int (*est_power_get)(const struct scmi_handle *handle, u32 domain,
116 unsigned long *rate, unsigned long *power);
113}; 117};
114 118
115/** 119/**
diff --git a/include/linux/soc/amlogic/meson-canvas.h b/include/linux/soc/amlogic/meson-canvas.h
new file mode 100644
index 000000000000..b4dde2fbeb3f
--- /dev/null
+++ b/include/linux/soc/amlogic/meson-canvas.h
@@ -0,0 +1,65 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 BayLibre, SAS
4 */
5#ifndef __SOC_MESON_CANVAS_H
6#define __SOC_MESON_CANVAS_H
7
8#include <linux/kernel.h>
9
10#define MESON_CANVAS_WRAP_NONE 0x00
11#define MESON_CANVAS_WRAP_X 0x01
12#define MESON_CANVAS_WRAP_Y 0x02
13
14#define MESON_CANVAS_BLKMODE_LINEAR 0x00
15#define MESON_CANVAS_BLKMODE_32x32 0x01
16#define MESON_CANVAS_BLKMODE_64x64 0x02
17
18#define MESON_CANVAS_ENDIAN_SWAP16 0x1
19#define MESON_CANVAS_ENDIAN_SWAP32 0x3
20#define MESON_CANVAS_ENDIAN_SWAP64 0x7
21#define MESON_CANVAS_ENDIAN_SWAP128 0xf
22
23struct meson_canvas;
24
25/**
26 * meson_canvas_get() - get a canvas provider instance
27 *
28 * @dev: consumer device pointer
29 */
30struct meson_canvas *meson_canvas_get(struct device *dev);
31
32/**
33 * meson_canvas_alloc() - take ownership of a canvas
34 *
35 * @canvas: canvas provider instance retrieved from meson_canvas_get()
36 * @canvas_index: will be filled with the canvas ID
37 */
38int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index);
39
40/**
41 * meson_canvas_free() - remove ownership from a canvas
42 *
43 * @canvas: canvas provider instance retrieved from meson_canvas_get()
44 * @canvas_index: canvas ID that was obtained via meson_canvas_alloc()
45 */
46int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index);
47
48/**
49 * meson_canvas_config() - configure a canvas
50 *
51 * @canvas: canvas provider instance retrieved from meson_canvas_get()
52 * @canvas_index: canvas ID that was obtained via meson_canvas_alloc()
53 * @addr: physical address to the pixel buffer
54 * @stride: width of the buffer
55 * @height: height of the buffer
56 * @wrap: undocumented
57 * @blkmode: block mode (linear, 32x32, 64x64)
58 * @endian: byte swapping (swap16, swap32, swap64, swap128)
59 */
60int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index,
61 u32 addr, u32 stride, u32 height,
62 unsigned int wrap, unsigned int blkmode,
63 unsigned int endian);
64
65#endif
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 7e3b9c605ab2..69c285b1c990 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -70,25 +70,51 @@ struct llcc_slice_config {
70/** 70/**
71 * llcc_drv_data - Data associated with the llcc driver 71 * llcc_drv_data - Data associated with the llcc driver
72 * @regmap: regmap associated with the llcc device 72 * @regmap: regmap associated with the llcc device
73 * @bcast_regmap: regmap associated with llcc broadcast offset
73 * @cfg: pointer to the data structure for slice configuration 74 * @cfg: pointer to the data structure for slice configuration
74 * @lock: mutex associated with each slice 75 * @lock: mutex associated with each slice
75 * @cfg_size: size of the config data table 76 * @cfg_size: size of the config data table
76 * @max_slices: max slices as read from device tree 77 * @max_slices: max slices as read from device tree
77 * @bcast_off: Offset of the broadcast bank
78 * @num_banks: Number of llcc banks 78 * @num_banks: Number of llcc banks
79 * @bitmap: Bit map to track the active slice ids 79 * @bitmap: Bit map to track the active slice ids
80 * @offsets: Pointer to the bank offsets array 80 * @offsets: Pointer to the bank offsets array
81 * @ecc_irq: interrupt for llcc cache error detection and reporting
81 */ 82 */
82struct llcc_drv_data { 83struct llcc_drv_data {
83 struct regmap *regmap; 84 struct regmap *regmap;
85 struct regmap *bcast_regmap;
84 const struct llcc_slice_config *cfg; 86 const struct llcc_slice_config *cfg;
85 struct mutex lock; 87 struct mutex lock;
86 u32 cfg_size; 88 u32 cfg_size;
87 u32 max_slices; 89 u32 max_slices;
88 u32 bcast_off;
89 u32 num_banks; 90 u32 num_banks;
90 unsigned long *bitmap; 91 unsigned long *bitmap;
91 u32 *offsets; 92 u32 *offsets;
93 int ecc_irq;
94};
95
96/**
97 * llcc_edac_reg_data - llcc edac registers data for each error type
98 * @name: Name of the error
99 * @synd_reg: Syndrome register address
100 * @count_status_reg: Status register address to read the error count
101 * @ways_status_reg: Status register address to read the error ways
102 * @reg_cnt: Number of registers
103 * @count_mask: Mask value to get the error count
104 * @ways_mask: Mask value to get the error ways
105 * @count_shift: Shift value to get the error count
106 * @ways_shift: Shift value to get the error ways
107 */
108struct llcc_edac_reg_data {
109 char *name;
110 u64 synd_reg;
111 u64 count_status_reg;
112 u64 ways_status_reg;
113 u32 reg_cnt;
114 u32 count_mask;
115 u32 ways_mask;
116 u8 count_shift;
117 u8 ways_shift;
92}; 118};
93 119
94#if IS_ENABLED(CONFIG_QCOM_LLCC) 120#if IS_ENABLED(CONFIG_QCOM_LLCC)
diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h
index a2b3dfcee0b5..6cfe05893a76 100644
--- a/include/linux/tee_drv.h
+++ b/include/linux/tee_drv.h
@@ -453,6 +453,79 @@ static inline int tee_shm_get_id(struct tee_shm *shm)
453 */ 453 */
454struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); 454struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id);
455 455
456/**
457 * tee_client_open_context() - Open a TEE context
458 * @start: if not NULL, continue search after this context
459 * @match: function to check TEE device
460 * @data: data for match function
461 * @vers: if not NULL, version data of TEE device of the context returned
462 *
463 * This function does an operation similar to open("/dev/teeX") in user space.
464 * A returned context must be released with tee_client_close_context().
465 *
466 * Returns a TEE context of the first TEE device matched by the match()
467 * callback or an ERR_PTR.
468 */
469struct tee_context *
470tee_client_open_context(struct tee_context *start,
471 int (*match)(struct tee_ioctl_version_data *,
472 const void *),
473 const void *data, struct tee_ioctl_version_data *vers);
474
475/**
476 * tee_client_close_context() - Close a TEE context
477 * @ctx: TEE context to close
478 *
479 * Note that all sessions previously opened with this context will be
480 * closed when this function is called.
481 */
482void tee_client_close_context(struct tee_context *ctx);
483
484/**
485 * tee_client_get_version() - Query version of TEE
486 * @ctx: TEE context to TEE to query
487 * @vers: Pointer to version data
488 */
489void tee_client_get_version(struct tee_context *ctx,
490 struct tee_ioctl_version_data *vers);
491
492/**
493 * tee_client_open_session() - Open a session to a Trusted Application
494 * @ctx: TEE context
495 * @arg: Open session arguments, see description of
496 * struct tee_ioctl_open_session_arg
497 * @param: Parameters passed to the Trusted Application
498 *
499 * Returns < 0 on error else see @arg->ret for result. If @arg->ret
500 * is TEEC_SUCCESS the session identifier is available in @arg->session.
501 */
502int tee_client_open_session(struct tee_context *ctx,
503 struct tee_ioctl_open_session_arg *arg,
504 struct tee_param *param);
505
506/**
507 * tee_client_close_session() - Close a session to a Trusted Application
508 * @ctx: TEE Context
509 * @session: Session id
510 *
511 * Return < 0 on error else 0, regardless the session will not be
512 * valid after this function has returned.
513 */
514int tee_client_close_session(struct tee_context *ctx, u32 session);
515
516/**
517 * tee_client_invoke_func() - Invoke a function in a Trusted Application
518 * @ctx: TEE Context
519 * @arg: Invoke arguments, see description of
520 * struct tee_ioctl_invoke_arg
521 * @param: Parameters passed to the Trusted Application
522 *
523 * Returns < 0 on error else see @arg->ret for result.
524 */
525int tee_client_invoke_func(struct tee_context *ctx,
526 struct tee_ioctl_invoke_arg *arg,
527 struct tee_param *param);
528
456static inline bool tee_param_is_memref(struct tee_param *param) 529static inline bool tee_param_is_memref(struct tee_param *param)
457{ 530{
458 switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { 531 switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) {
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-12 04:00:32 -0400