diff options
| author | Krzysztof Kozlowski <k.kozlowski.k@gmail.com> | 2015-07-15 08:59:53 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-07-16 16:39:30 -0400 |
| commit | 309a3e00a511a233acb25eec567a4b11c99d016a (patch) | |
| tree | 58e5f5ada4c558ddf481bb2845888ef01fa65c63 /include/linux | |
| parent | cceb433a1e2930301b33c79016eff147eb555cea (diff) | |
mfd/extcon: max77843: Rename defines to allow inclusion with max77693
Add MAX77843_MUIC prefix to some of the defines used in max77843 extcon
driver so the max77693-private.h can be included simultaneously with
max77843-private.h.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mfd/max77843-private.h | 154 |
1 files changed, 77 insertions, 77 deletions
diff --git a/include/linux/mfd/max77843-private.h b/include/linux/mfd/max77843-private.h index 0121d9440340..c19303b0ccfd 100644 --- a/include/linux/mfd/max77843-private.h +++ b/include/linux/mfd/max77843-private.h | |||
| @@ -318,62 +318,62 @@ enum max77843_irq_muic { | |||
| 318 | MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK) | 318 | MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK) |
| 319 | 319 | ||
| 320 | /* MAX77843 STATUS register*/ | 320 | /* MAX77843 STATUS register*/ |
| 321 | #define STATUS1_ADC_SHIFT 0 | 321 | #define MAX77843_MUIC_STATUS1_ADC_SHIFT 0 |
| 322 | #define STATUS1_ADCERROR_SHIFT 6 | 322 | #define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6 |
| 323 | #define STATUS1_ADC1K_SHIFT 7 | 323 | #define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7 |
| 324 | #define STATUS2_CHGTYP_SHIFT 0 | 324 | #define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0 |
| 325 | #define STATUS2_CHGDETRUN_SHIFT 3 | 325 | #define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3 |
| 326 | #define STATUS2_DCDTMR_SHIFT 4 | 326 | #define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4 |
| 327 | #define STATUS2_DXOVP_SHIFT 5 | 327 | #define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5 |
| 328 | #define STATUS2_VBVOLT_SHIFT 6 | 328 | #define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6 |
| 329 | #define STATUS3_VBADC_SHIFT 0 | 329 | #define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0 |
| 330 | #define STATUS3_VDNMON_SHIFT 4 | 330 | #define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4 |
| 331 | #define STATUS3_DNRES_SHIFT 5 | 331 | #define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5 |
| 332 | #define STATUS3_MPNACK_SHIFT 6 | 332 | #define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6 |
| 333 | 333 | ||
| 334 | #define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) | 334 | #define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT) |
| 335 | #define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(STATUS1_ADCERROR_SHIFT) | 335 | #define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT) |
| 336 | #define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(STATUS1_ADC1K_SHIFT) | 336 | #define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT) |
| 337 | #define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) | 337 | #define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT) |
| 338 | #define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT) | 338 | #define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT) |
| 339 | #define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT) | 339 | #define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT) |
| 340 | #define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(STATUS2_DXOVP_SHIFT) | 340 | #define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT) |
| 341 | #define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT) | 341 | #define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT) |
| 342 | #define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT) | 342 | #define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT) |
| 343 | #define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(STATUS3_VDNMON_SHIFT) | 343 | #define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT) |
| 344 | #define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(STATUS3_DNRES_SHIFT) | 344 | #define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT) |
| 345 | #define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(STATUS3_MPNACK_SHIFT) | 345 | #define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT) |
| 346 | 346 | ||
| 347 | /* MAX77843 CONTROL register */ | 347 | /* MAX77843 CONTROL register */ |
| 348 | #define CONTROL1_COMP1SW_SHIFT 0 | 348 | #define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0 |
| 349 | #define CONTROL1_COMP2SW_SHIFT 3 | 349 | #define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3 |
| 350 | #define CONTROL1_IDBEN_SHIFT 7 | 350 | #define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7 |
| 351 | #define CONTROL2_LOWPWR_SHIFT 0 | 351 | #define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0 |
| 352 | #define CONTROL2_ADCEN_SHIFT 1 | 352 | #define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1 |
| 353 | #define CONTROL2_CPEN_SHIFT 2 | 353 | #define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2 |
| 354 | #define CONTROL2_ACC_DET_SHIFT 5 | 354 | #define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5 |
| 355 | #define CONTROL2_USBCPINT_SHIFT 6 | 355 | #define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6 |
| 356 | #define CONTROL2_RCPS_SHIFT 7 | 356 | #define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7 |
| 357 | #define CONTROL3_JIGSET_SHIFT 0 | 357 | #define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0 |
| 358 | #define CONTROL4_ADCDBSET_SHIFT 0 | 358 | #define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0 |
| 359 | #define CONTROL4_USBAUTO_SHIFT 4 | 359 | #define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4 |
| 360 | #define CONTROL4_FCTAUTO_SHIFT 5 | 360 | #define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5 |
| 361 | #define CONTROL4_ADCMODE_SHIFT 6 | 361 | #define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6 |
| 362 | 362 | ||
| 363 | #define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << CONTROL1_COMP1SW_SHIFT) | 363 | #define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT) |
| 364 | #define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << CONTROL1_COMP2SW_SHIFT) | 364 | #define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT) |
| 365 | #define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(CONTROL1_IDBEN_SHIFT) | 365 | #define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT) |
| 366 | #define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(CONTROL2_LOWPWR_SHIFT) | 366 | #define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT) |
| 367 | #define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(CONTROL2_ADCEN_SHIFT) | 367 | #define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT) |
| 368 | #define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(CONTROL2_CPEN_SHIFT) | 368 | #define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT) |
| 369 | #define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(CONTROL2_ACC_DET_SHIFT) | 369 | #define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT) |
| 370 | #define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(CONTROL2_USBCPINT_SHIFT) | 370 | #define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT) |
| 371 | #define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(CONTROL2_RCPS_SHIFT) | 371 | #define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT) |
| 372 | #define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT) | 372 | #define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT) |
| 373 | #define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << CONTROL4_ADCDBSET_SHIFT) | 373 | #define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT) |
| 374 | #define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(CONTROL4_USBAUTO_SHIFT) | 374 | #define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) |
| 375 | #define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(CONTROL4_FCTAUTO_SHIFT) | 375 | #define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT) |
| 376 | #define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << CONTROL4_ADCMODE_SHIFT) | 376 | #define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT) |
| 377 | 377 | ||
| 378 | /* MAX77843 switch port */ | 378 | /* MAX77843 switch port */ |
| 379 | #define COM_OPEN 0 | 379 | #define COM_OPEN 0 |
| @@ -383,38 +383,38 @@ enum max77843_irq_muic { | |||
| 383 | #define COM_AUX_USB 4 | 383 | #define COM_AUX_USB 4 |
| 384 | #define COM_AUX_UART 5 | 384 | #define COM_AUX_UART 5 |
| 385 | 385 | ||
| 386 | #define CONTROL1_COM_SW \ | 386 | #define MAX77843_MUIC_CONTROL1_COM_SW \ |
| 387 | ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \ | 387 | ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \ |
| 388 | MAX77843_MUIC_CONTROL1_COMP2SW_MASK)) | 388 | MAX77843_MUIC_CONTROL1_COMP2SW_MASK)) |
| 389 | 389 | ||
| 390 | #define CONTROL1_SW_OPEN \ | 390 | #define MAX77843_MUIC_CONTROL1_SW_OPEN \ |
| 391 | ((COM_OPEN << CONTROL1_COMP1SW_SHIFT | \ | 391 | ((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 392 | COM_OPEN << CONTROL1_COMP2SW_SHIFT)) | 392 | COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 393 | #define CONTROL1_SW_USB \ | 393 | #define MAX77843_MUIC_CONTROL1_SW_USB \ |
| 394 | ((COM_USB << CONTROL1_COMP1SW_SHIFT | \ | 394 | ((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 395 | COM_USB << CONTROL1_COMP2SW_SHIFT)) | 395 | COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 396 | #define CONTROL1_SW_AUDIO \ | 396 | #define MAX77843_MUIC_CONTROL1_SW_AUDIO \ |
| 397 | ((COM_AUDIO << CONTROL1_COMP1SW_SHIFT | \ | 397 | ((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 398 | COM_AUDIO << CONTROL1_COMP2SW_SHIFT)) | 398 | COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 399 | #define CONTROL1_SW_UART \ | 399 | #define MAX77843_MUIC_CONTROL1_SW_UART \ |
| 400 | ((COM_UART << CONTROL1_COMP1SW_SHIFT | \ | 400 | ((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 401 | COM_UART << CONTROL1_COMP2SW_SHIFT)) | 401 | COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 402 | #define CONTROL1_SW_AUX_USB \ | 402 | #define MAX77843_MUIC_CONTROL1_SW_AUX_USB \ |
| 403 | ((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT | \ | 403 | ((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 404 | COM_AUX_USB << CONTROL1_COMP2SW_SHIFT)) | 404 | COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 405 | #define CONTROL1_SW_AUX_UART \ | 405 | #define MAX77843_MUIC_CONTROL1_SW_AUX_UART \ |
| 406 | ((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT | \ | 406 | ((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ |
| 407 | COM_AUX_UART << CONTROL1_COMP2SW_SHIFT)) | 407 | COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) |
| 408 | 408 | ||
| 409 | #define MAX77843_DISABLE 0 | 409 | #define MAX77843_DISABLE 0 |
| 410 | #define MAX77843_ENABLE 1 | 410 | #define MAX77843_ENABLE 1 |
| 411 | 411 | ||
| 412 | #define CONTROL4_AUTO_DISABLE \ | 412 | #define CONTROL4_AUTO_DISABLE \ |
| 413 | ((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) | \ | 413 | ((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ |
| 414 | (MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT)) | 414 | (MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) |
| 415 | #define CONTROL4_AUTO_ENABLE \ | 415 | #define CONTROL4_AUTO_ENABLE \ |
| 416 | ((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) | \ | 416 | ((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ |
| 417 | (MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT)) | 417 | (MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) |
| 418 | 418 | ||
| 419 | /* MAX77843 SAFEOUT LDO Control register */ | 419 | /* MAX77843 SAFEOUT LDO Control register */ |
| 420 | #define SAFEOUTCTRL_SAFEOUT1_SHIFT 0 | 420 | #define SAFEOUTCTRL_SAFEOUT1_SHIFT 0 |
