Merge tag 'v4.4-rc2' into drm-intel-next-queued

Linux 4.4-rc2

Backmerge to get at

commit 1b0e3a049efe471c399674fd954500ce97438d30
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Nov 5 23:04:11 2015 +0200

    drm/i915/skl: disable display side power well support for now

so that we can proplery re-eanble skl power wells in -next.

Conflicts are just adjacent lines changed, except for intel_fbdev.c
where we need to interleave the changs. Nothing nefarious.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index a41833cd184c..5dd75fa47dd8 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -5,9 +5,28 @@
 #ifndef __LINUX_USB_CHIPIDEA_H
 #define __LINUX_USB_CHIPIDEA_H
 
+#include <linux/extcon.h>
 #include <linux/usb/otg.h>
 
 struct ci_hdrc;
+
+/**
+ * struct ci_hdrc_cable - structure for external connector cable state tracking
+ * @state: current state of the line
+ * @changed: set to true when extcon event happen
+ * @edev: device which generate events
+ * @ci: driver state of the chipidea device
+ * @nb: hold event notification callback
+ * @conn: used for notification registration
+ */
+struct ci_hdrc_cable {
+        bool                            state;
+        bool                            changed;
+        struct extcon_dev               *edev;
+        struct ci_hdrc                  *ci;
+        struct notifier_block           nb;
+};
+
 struct ci_hdrc_platform_data {
         const char      *name;
         /* offset of the capability registers */
@@ -48,6 +67,11 @@ struct ci_hdrc_platform_data {
         u32                     ahb_burst_config;
         u32                     tx_burst_size;
         u32                     rx_burst_size;
+
+        /* VBUS and ID signal state tracking, using extcon framework */
+        struct ci_hdrc_cable            vbus_extcon;
+        struct ci_hdrc_cable            id_extcon;
+        u32                     phy_clkgate_delay_us;
 };
 
 /* Default offset of capability registers */